diff options
47 files changed, 11597 insertions, 1 deletions
diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 2ecdfbf415..39f375cf84 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -258,6 +258,7 @@ "nxp/imx/imxrt/imxrt1180-nxp-evk/cm7", "nxp/mcx/mcxn/frdm-mcxn947", "nxp/mcx/mcxn/frdm-mcxn236", + "nxp/mcx/mcxc/frdm-mcxc162", "nxp/mcx/mcxc/frdm-mcxc444", "nxp/mcx/mcxa/frdm-mcxa153", "nxp/mcx/mcxa/frdm-mcxa156", diff --git a/bsp/README.md b/bsp/README.md index 39703eddc3..da23db8e15 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -197,6 +197,7 @@ This document is based on the RT-Thread mainline repository and categorizes the | [frdm-mcxa153](nxp/mcx/mcxa/frdm-mcxa153) | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | - | - | ✅ | - | - | - | - | - | - | ✅ | - | - | - | ✅ | | [frdm-mcxa156](nxp/mcx/mcxa/frdm-mcxa156) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | ✅ | | [frdm-mcxa346](nxp/mcx/mcxa/frdm-mcxa346) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | - | ✅ | ✅ | - | - | - | - | - | ✅ | - | - | - | ✅ | +| [frdm-mcxc162](nxp/mcx/mcxc/frdm-mcxc162) | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | - | - | ✅ | ✅ | - | - | - | - | - | ✅ | - | - | - | ✅ | | [frdm-mcxc444](nxp/mcx/mcxc/frdm-mcxc444) | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | - | - | ✅ | ✅ | - | - | - | - | - | ✅ | - | - | - | ✅ | | [frdm-mcxe247](nxp/mcx/mcxe/frdm-mcxe247) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | - | ✅ | ✅ | - | - | - | - | - | ✅ | - | - | - | ✅ | | [frdm-mcxn236](nxp/mcx/mcxn/frdm-mcxn236) | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | ✅ | ✅ | - | - | ✅ | ✅ | - | - | - | - | - | ✅ | - | - | - | ✅ | diff --git a/bsp/nxp/README.md b/bsp/nxp/README.md index aa7f37dc03..1635f794a3 100644 --- a/bsp/nxp/README.md +++ b/bsp/nxp/README.md @@ -13,6 +13,7 @@ NXP 系列 BSP 目前支持情况如下表所示： | [frdm-mcxa346](mcx/mcxa/frdm-mcxa346) | NXP 官方 FRDM-MCXA346 开发板 | | [frdm-mcxa344](mcx/mcxa/frdm-mcxa344) | NXP 官方 FRDM-MCXA344 开发板 | | **MCXC 系列** | | +| [frdm-mcxc162](mcx/mcxc/frdm-mcxc162) | NXP 官方 FRDM-MCXC162 开发板 | | [frdm-mcxc444](mcx/mcxc/frdm-mcxc444) | NXP 官方 FRDM-MCXC444 开发板 | | **LPC 系列** | | | [lpc43xx](lpc/lpc43xx) | NXP LPC43xx 系列开发板 | diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/mcx/mcxc/frdm-mcxc162/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 0000000000..7c67ad7568 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,23 @@ +peripheral.communication: + scons_arg: &scons + - '--strict' + kconfig: + - CONFIG_BSP_USING_UART1=y + - CONFIG_BSP_USING_UART2=y + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C0=y + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI0=y + +peripheral.timing_control: + scons_arg: *scons + kconfig: + - CONFIG_RT_USING_EVENT=y + - CONFIG_RT_USING_ALARM=y + - CONFIG_BSP_USING_RTC=y + - CONFIG_BSP_USING_WDT=y + - CONFIG_BSP_USING_CLOCK_TIMER=y + - CONFIG_BSP_USING_CTIMER0=y + - CONFIG_BSP_USING_CTIMER1=y + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM0=y diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/.config b/bsp/nxp/mcx/mcxc/frdm-mcxc162/.config new file mode 100644 index 0000000000..5110684b06 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/.config @@ -0,0 +1,1449 @@ +CONFIG_SOC_MCX=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +# CONFIG_RT_USING_OVERFLOW_CHECK is not set +# CONFIG_RT_USING_HOOK is not set +# CONFIG_RT_USING_HOOKLIST is not set +# CONFIG_RT_USING_IDLE_HOOK is not set +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +# CONFIG_RT_USING_DEBUG is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +# CONFIG_RT_USING_EVENT is not set +# CONFIG_RT_USING_MAILBOX is not set +# CONFIG_RT_USING_MESSAGEQUEUE is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +# CONFIG_RT_USING_MEMPOOL is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_USING_HW_ATOMIC_8=y +CONFIG_ARCH_USING_HW_ATOMIC_16=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M23=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=2048 +# CONFIG_FINSH_USING_HISTORY is not set +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +# CONFIG_FINSH_USING_DESCRIPTION is not set +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_FINSH_USING_OPTION_COMPLETION is not set + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER=y +CONFIG_PKG_NXP_MCX_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-mcx-cmsis" +CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NXP_MCX_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER=y +CONFIG_PKG_NXP_MCX_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-mcx-series" +CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NXP_MCX_SERIES_DRIVER_VER="latest" +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# Hardware Drivers Config +# +CONFIG_SOC_MCXC162=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_CLOCK_TIMER is not set +# CONFIG_BSP_USING_PWM is not set +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/.gitignore b/bsp/nxp/mcx/mcxc/frdm-mcxc162/.gitignore new file mode 100644 index 0000000000..3c29aee77e --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/.gitignore @@ -0,0 +1,4 @@ +JLinkLog.txt +JLinkSettings.ini +project.uvoptx +RTE/ diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/Kconfig b/bsp/nxp/mcx/mcxc/frdm-mcxc162/Kconfig new file mode 100644 index 0000000000..07cf908ccd --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/Kconfig @@ -0,0 +1,15 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . +RTT_DIR := ../../../../.. +PKGS_DIR := packages + +config SOC_MCX + bool + select ARCH_ARM_CORTEX_M23 + default y + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/README.md b/bsp/nxp/mcx/mcxc/frdm-mcxc162/README.md new file mode 100644 index 0000000000..241d0c097c --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/README.md @@ -0,0 +1,188 @@ +# FRDM-MCXC162 BSP + +## Overview + +This BSP targets the production FRDM-MCXC162 board fitted with an +`MCXC162VFT` Cortex-M23 MCU. The core runs from the 72 MHz FRO with no FPU, +TrustZone, or MPU enabled. + +The linker uses only the 64 KiB Program Flash at `0x00000000` and 12 KiB SRAM +at `0x20000000`. The non-contiguous Data Flash at `0x0001C000` is not part of +the program image. + +## Supported interfaces + +| RT-Thread device | Peripheral | Board pins | Default | +| --- | --- | --- | --- | +| `pin` | GPIO0-GPIO3 | `GET_PINS(port, pin)` | Enabled | +| `uart0` | LPUART0 | P0_2 RX, P0_3 TX | Enabled, console | +| `uart1` | LPUART1 | P2_12 RX, P2_13 TX | Disabled | +| `uart2` | LPUART2 | P3_13 RX, P3_12 TX | Disabled | +| `i2c0` | LPI2C0 | P3_27 SCL, P3_28 SDA | Disabled | +| `spi0` | LPSPI0 | P3_10 SCK, P3_8 SDO, P3_9 SDI, P3_11 software CS | Disabled | +| `rtc` | RTC0 | Internal | Disabled | +| `wdt` | WWDT0 | Internal | Disabled | +| `timer0`, `timer1` | CTIMER0, CTIMER1 | Internal | Disabled | +| `pwm0` channel 0/1 | FLEXPWM0 SM0 A/B | P3_0, P3_1 | Disabled | + +The two PWM channels share one period. Changing the period while the other +channel is enabled returns `-RT_EINVAL`. + +UART3, LPADC0, DMA, Data Flash, TRDC, low-power modes, and tickless operation +are outside this BSP version. + +## Build + +Install or update the NXP MCX CMSIS and series packages first: + +```console +pkgs --update +``` + +Set `RTT_EXEC_PATH` to the compiler binary directory, then build: + +```console +set RTT_CC=gcc +set RTT_EXEC_PATH=C:\path\to\arm-none-eabi\bin +scons -j8 +``` + +The primary GCC baseline is Arm GNU Toolchain 14.2 from MCUXpresso IDE 25.06. +GCC 10.3.1 is retained as a compatibility build. Keil MDK 5.43a with +`MCXC162_DFP 26.06.00` and IAR EWARM 9.70.4 are the SDK 26.06 reference +versions. + +The final generated projects are verified with Keil MDK 5.42 and Arm Compiler +6.23, and with IAR EWARM 9.60.3.422. The SDK reference Keil 5.43a and IAR +9.70.4 versions have not been repeated locally. + +Project files can be regenerated with: + +```console +set RTT_CC=keil +scons --target=mdk5 +set RTT_CC=iar +scons --target=iar +``` + +Build the generated `project.uvprojx` with `uVision.com` and `project.ewp` with +`IarBuild.exe`; the `template.*` files are generator inputs, not build targets. + +```console +uVision.com -b project.uvprojx -j0 +IarBuild.exe project.ewp -build Debug +``` + +## Default behavior + +The default configuration provides a 1 kHz system tick and a 115200-8-N-1 +`uart0` console with MSH. The active-low red LED on P2_3 toggles every 500 ms. +No periodic application log is emitted. + +Run `button_irq_test`, then press both SW2 and SW3 during its 10-second window. +It must report non-zero falling-edge interrupt counts for both buttons. The wait +also provides a simple observable check of the 1 kHz RT-Thread tick. +Run `reboot` and confirm that the banner and MSH prompt return after a software +reset; use the RESET button for the matching hardware-reset check. + +The validation commands below are compiled only when their corresponding +optional BSP driver is enabled. They add no code to the default PIN + UART0 +image. + +Build the two CI validation configurations with: + +```console +scons --attach=peripheral.communication +scons -j8 +scons --attach=default +scons --attach=peripheral.timing_control +scons -j8 +scons --attach=default +``` + +## Peripheral validation commands + +Use `uart0` for the MSH console while testing the other UARTs. + +| Test | Wiring | Command | Pass criterion | +| --- | --- | --- | --- | +| UART1 | Jumper Arduino D1/P2_13 TX to D0/P2_12 RX | `uart_loop uart1` | `PASS` after an 8-byte 115200-8-N-1 loopback | +| UART2 | Jumper mikroBUS TX/P3_12 to RX/P3_13 | `uart_loop uart2` | `PASS` after an 8-byte 115200-8-N-1 loopback | +| P3T1755 | None; the sensor is already connected to P3_27 SCL and P3_28 SDA | `p3t1755` | Address `0x48` acknowledges and one temperature is printed | +| SPI0 | Jumper Arduino D11/P3_8 SDO to D12/P3_9 SDI; probe D13/P3_10 SCK and D10/P3_11 CS | `spi_loop` | `PASS`; the analyzer also shows mode 0, 1 MHz SCK, and active-low CS | +| CTIMER0 | None | `ctimer0_test` | The RT-Thread clock-time backend reports one 100 ms one-shot completion | +| CTIMER1 | None | `ctimer_test timer1 oneshot`, then `ctimer_test timer1 periodic` | One interrupt, then 4-6 interrupts in 550 ms | + +`timer0` is opened exclusively by the RT-Thread clock-time subsystem and must +not be opened or controlled as a regular timer device. Use `timer1` for direct +one-shot and periodic device tests. + +P3_11 is driven as the RT-Thread software chip select. LPSPI uses an unrouted +internal PCS, so P3_11 remains asserted across compound SPI messages. This BSP +supports active-low software chip select only. + +`p3t1755` sends the temperature-register pointer and the two-byte read as one +two-message transaction. The bus therefore emits a repeated START, as required +by ERR053261. + +The v1 I2C adapter requires each `rt_i2c_transfer()` call to begin with START +and end with STOP. A first-message `RT_I2C_NO_START` or final-message +`RT_I2C_NO_STOP` request is rejected. `RT_I2C_NO_START` is accepted only when +joining consecutive writes to the same addressed slave. + +WWDT tests must be run separately after each reset. `wwdt refresh` starts a +3-second watchdog and refreshes it once per second without periodic output; let +it run for at least 10 seconds and press RESET to end the test. `wwdt timeout` +does not refresh the watchdog: the MCU must reset in about 3 seconds, and the +next boot must report `last reset was caused by WWDT0`. + +RTC set/get and PWM control reuse the standard MSH commands: + +```console +date 2026 9 3 12 0 0 +date +rtc_alarm_test + +pwm probe pwm0 +pwm set 0 1000000 250000 +pwm enable 0 +pwm set 1 1000000 500000 +pwm enable 1 +pwm get 0 +pwm get 1 +pwm disable 0 +pwm disable 1 +``` + +`rtc_alarm_test` requires `RT_USING_ALARM` and must report `PASS` after about +3 seconds. For PWM, probe Arduino D5/P3_0 (channel 0) and D6/P3_1 (channel 1) +against GND; expect 1 kHz at 25% and 50% duty respectively. While channel 0 is +enabled, `pwm set 1 2000000 1000000` must return `-RT_EINVAL` and must not +change the shared 1 ms period. + +## Hardware validation + +The following checks have been completed on a production FRDM-MCXC162 Rev 1: + +- banner, MSH, red LED, SW2 P3_14 and SW3 P3_29 interrupts, reset behavior, + 1 kHz tick, and a 10-minute run; +- UART1/UART2 loopback; +- the onboard P3T1755 at address `0x48` and temperature reads on `i2c0`; +- SPI0 SDO-to-SDI loopback, including SCK and CS; +- RTC time/alarm, WWDT refresh and timeout reset, CTIMER one-shot/periodic, + and PWM frequency, duty, start/stop, and shared-period rejection; +- download, startup, tick, console, and GPIO with both Keil and IAR. + +For MCXC162 erratum ERR053261, do not issue consecutive LPI2C read commands +without a STOP/START or repeated START between them. + +Board programming and the MCUXpresso IDE debug configuration are performed by +the board owner. + +## References + +- [FRDM-MCXC162 board](https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXC162) +- [MCXC162 data sheet](https://www.nxp.com/docs/en/data-sheet/MCXCP048M072F20.pdf) +- [MCXC162 errata](https://www.nxp.com/docs/en/errata/MCXC162VFT_0P18R.pdf) +- [NXP MCXC162 device files](https://github.com/nxp-mcuxpresso/mcux-devices-mcx/tree/main/MCXC/MCXC162) +- [MCUX SDK 26.06 release notes](https://docs.mcuxpresso.nxp.com/mcuxsdk/26.06.00/html/boards/MCX/frdmmcxc162/releaseNotes/rnindex.html) diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/README_zh.md b/bsp/nxp/mcx/mcxc/frdm-mcxc162/README_zh.md new file mode 100644 index 0000000000..1f5249bc19 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/README_zh.md @@ -0,0 +1,172 @@ +# FRDM-MCXC162 BSP 说明 + +## 简介 + +本 BSP 面向量产版 FRDM-MCXC162，固定使用 `MCXC162VFT` Cortex-M23，内核运行 +在 72 MHz FRO；不启用 FPU、TrustZone 和 MPU。 + +链接器只使用 `0x00000000` 起始的 64 KiB Program Flash，以及 +`0x20000000` 起始的 12 KiB SRAM。位于 `0x0001C000` 的非连续 Data Flash 不会 +拼入程序区。 + +## 支持接口 + +| RT-Thread 设备 | 芯片外设 | 板级引脚 | 默认状态 | +| --- | --- | --- | --- | +| `pin` | GPIO0-GPIO3 | `GET_PINS(port, pin)` | 开启 | +| `uart0` | LPUART0 | P0_2 RX、P0_3 TX | 开启，作为控制台 | +| `uart1` | LPUART1 | P2_12 RX、P2_13 TX | 关闭 | +| `uart2` | LPUART2 | P3_13 RX、P3_12 TX | 关闭 | +| `i2c0` | LPI2C0 | P3_27 SCL、P3_28 SDA | 关闭 | +| `spi0` | LPSPI0 | P3_10 SCK、P3_8 SDO、P3_9 SDI、P3_11 软件 CS | 关闭 | +| `rtc` | RTC0 | 内部 | 关闭 | +| `wdt` | WWDT0 | 内部 | 关闭 | +| `timer0`、`timer1` | CTIMER0、CTIMER1 | 内部 | 关闭 | +| `pwm0` 通道 0/1 | FLEXPWM0 SM0 A/B | P3_0、P3_1 | 关闭 | + +PWM 两个通道共用周期。另一通道已经启用时，如果提交不同周期，驱动返回 +`-RT_EINVAL`。 + +本版不支持 UART3、LPADC0、DMA、Data Flash、TRDC、低功耗和 tickless。 + +## 编译 + +先安装或更新 NXP MCX CMSIS 与 series package： + +```console +pkgs --update +``` + +将 `RTT_EXEC_PATH` 指向编译器的可执行文件目录后编译： + +```console +set RTT_CC=gcc +set RTT_EXEC_PATH=C:\path\to\arm-none-eabi\bin +scons -j8 +``` + +主 GCC 基线为 MCUXpresso IDE 25.06 内置 Arm GNU Toolchain 14.2；另用 GCC +10.3.1 做兼容回归。SDK 26.06 的参考版本是 Keil MDK 5.43a（配合 +`MCXC162_DFP 26.06.00`）和 IAR EWARM 9.70.4。工程可重新生成： + +最终生成工程已使用 Keil MDK 5.42 + Arm Compiler 6.23 和 IAR EWARM +9.60.3.422 完成验证。本地未重复 SDK 参考版本 Keil 5.43a 与 IAR 9.70.4 的验证。 + +```console +set RTT_CC=keil +scons --target=mdk5 +set RTT_CC=iar +scons --target=iar +``` + +Keil 应构建生成的 `project.uvprojx`，IAR 应构建生成的 `project.ewp`； +`template.*` 仅是工程生成器输入，不是构建目标。 + +```console +uVision.com -b project.uvprojx -j0 +IarBuild.exe project.ewp -build Debug +``` + +## 默认运行现象 + +默认配置提供 1 kHz 系统 tick、115200-8-N-1 的 `uart0` 控制台和 MSH。低有效 +红灯 P2_3 每 500 ms 翻转一次，应用不输出周期日志。 + +执行 `button_irq_test`，并在 10 秒窗口内分别按下 SW2 和 SW3；命令必须报告两键 +都有非零下降沿中断计数。该等待窗口也可直观检查 RT-Thread 的 1 kHz tick。 +执行 `reboot` 后，banner 和 MSH 提示符必须在软件复位后重新出现；硬复位则使用 +板载 RESET 键做同样检查。 + +以下验收命令只在对应的可选 BSP 驱动开启后参与编译；默认 PIN + UART0 固件 +不会带入额外测试代码。 + +两组 CI 验收配置可按下列命令构建： + +```console +scons --attach=peripheral.communication +scons -j8 +scons --attach=default +scons --attach=peripheral.timing_control +scons -j8 +scons --attach=default +``` + +## 外设验收命令 + +测试其他 UART 时，继续用 `uart0` 作为 MSH 控制台。 + +| 项目 | 接线 | 命令 | 通过判据 | +| --- | --- | --- | --- | +| UART1 | Arduino D1/P2_13 TX 短接 D0/P2_12 RX | `uart_loop uart1` | 115200-8-N-1 回环 8 字节并输出 `PASS` | +| UART2 | mikroBUS TX/P3_12 短接 RX/P3_13 | `uart_loop uart2` | 115200-8-N-1 回环 8 字节并输出 `PASS` | +| P3T1755 | 无需接线；板载器件已连接 P3_27 SCL、P3_28 SDA | `p3t1755` | `0x48` 应答并打印一次温度 | +| SPI0 | Arduino D11/P3_8 SDO 短接 D12/P3_9 SDI；在 D13/P3_10 SCK、D10/P3_11 CS 测量 | `spi_loop` | 输出 `PASS`，且波形为 mode 0、1 MHz SCK、低有效 CS | +| CTIMER0 | 无需接线 | `ctimer0_test` | RT-Thread clock-time 后端完成一次 100 ms 单次定时 | +| CTIMER1 | 无需接线 | `ctimer_test timer1 oneshot`，再运行 `ctimer_test timer1 periodic` | 单次模式 1 次中断；周期模式 550 ms 内 4-6 次中断 | + +`timer0` 由 RT-Thread clock-time 子系统独占打开，不能作为普通定时器设备再次 +打开或控制。直接验证单次/周期设备接口时使用 `timer1`。 + +P3_11 由 RT-Thread 软件控制片选；LPSPI 内部改用未路由的 PCS，因此复合 SPI +消息之间 P3_11 会保持有效。本 BSP 只支持低有效软件片选。 + +`p3t1755` 把温度寄存器指针写入和两字节读取放在同一个双消息事务中，线上会 +产生 repeated START，满足 ERR053261 的要求。 + +v1 I2C 适配要求每次 `rt_i2c_transfer()` 以 START 开始、以 STOP 结束；若首条 +消息设置 `RT_I2C_NO_START`，或末条消息设置 `RT_I2C_NO_STOP`，请求会被拒绝。 +仅发往同一地址的连续写消息允许使用 `RT_I2C_NO_START` 拼接。 + +WWDT 两种测试应分别在复位后执行。`wwdt refresh` 启动 3 秒看门狗并每秒喂狗， +期间没有周期输出；至少稳定运行 10 秒后按 RESET 结束。`wwdt timeout` 不喂狗， +MCU 应在约 3 秒后复位，下一次启动应打印 +`last reset was caused by WWDT0`。 + +RTC set/get 和 PWM 控制直接复用 RT-Thread 标准 MSH 命令： + +```console +date 2026 9 3 12 0 0 +date +rtc_alarm_test + +pwm probe pwm0 +pwm set 0 1000000 250000 +pwm enable 0 +pwm set 1 1000000 500000 +pwm enable 1 +pwm get 0 +pwm get 1 +pwm disable 0 +pwm disable 1 +``` + +`rtc_alarm_test` 还需开启 `RT_USING_ALARM`，约 3 秒后应输出 `PASS`。PWM 测量点 +为 Arduino D5/P3_0（通道 0）和 D6/P3_1（通道 1），相对 GND 应分别得到 1 kHz、 +25% 和 50% 占空比。通道 0 已启用时执行 +`pwm set 1 2000000 1000000`，必须返回 `-RT_EINVAL`，共享的 1 ms 周期不得改变。 + +## 实板验收 + +以下验证已在量产版 FRDM-MCXC162 Rev 1 实板上完成： + +- banner、MSH、红灯、SW2 P3_14/SW3 P3_29 中断、软硬复位、1 kHz tick 和 + 10 分钟稳定运行； +- UART1/UART2 跳线回环； +- `i2c0` 上板载 P3T1755 地址 `0x48` 应答及温度读取； +- SPI0 SDO→SDI 回环，并检查 SCK/CS； +- RTC 走时/alarm、WWDT refresh/故意超时复位、CTIMER 单次/周期模式，以及 + PWM 频率、占空比、启停和共享周期拒绝； +- Keil 与 IAR 分别完成下载、启动、tick、console 和 GPIO 验证。 + +针对 MCXC162 勘误 ERR053261，连续 LPI2C 读命令之间必须插入 STOP/START 或 +repeated START。 + +实板烧写及 MCUXpresso IDE 下载配置由板卡使用者完成。 + +## 参考资料 + +- [FRDM-MCXC162 官方页](https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXC162) +- [MCXC162 数据手册](https://www.nxp.com/docs/en/data-sheet/MCXCP048M072F20.pdf) +- [MCXC162 芯片勘误](https://www.nxp.com/docs/en/errata/MCXC162VFT_0P18R.pdf) +- [NXP MCXC162 device 文件](https://github.com/nxp-mcuxpresso/mcux-devices-mcx/tree/main/MCXC/MCXC162) +- [MCUX SDK 26.06 release notes](https://docs.mcuxpresso.nxp.com/mcuxsdk/26.06.00/html/boards/MCX/frdmmcxc162/releaseNotes/rnindex.html) diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/SConscript b/bsp/nxp/mcx/mcxc/frdm-mcxc162/SConscript new file mode 100644 index 0000000000..775d9f678d --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/SConscript @@ -0,0 +1,12 @@ +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for name in os.listdir(cwd): + path = os.path.join(cwd, name) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs += SConscript(os.path.join(name, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/SConstruct b/bsp/nxp/mcx/mcxc/frdm-mcxc162/SConstruct new file mode 100644 index 0000000000..fa7be46383 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/SConstruct @@ -0,0 +1,67 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../..') + +sys.path.append(os.path.join(RTT_ROOT, 'tools')) +try: + from building import * +except ImportError: + print('Cannot find the RT-Thread root directory:') + print(RTT_ROOT) + exit(-1) + + +def bsp_pkg_check(): + package_files = [ + os.path.join(rtconfig.NXP_MCX_CMSIS_ROOT, 'Core', 'Include', 'core_cm23.h'), + os.path.join(rtconfig.NXP_MCX_SERIES_ROOT, 'MCXC162', 'gcc', 'MCXC162_flash.ld'), + ] + if not all(os.path.isfile(path) for path in package_files): + print('Required NXP packages are missing. Run pkgs --update first.') + exit(1) + + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +env = Environment( + tools=['mingw'], + AS=rtconfig.AS, + ASFLAGS=rtconfig.AFLAGS, + CC=rtconfig.CC, + CFLAGS=rtconfig.CFLAGS, + CXX=rtconfig.CXX, + CXXFLAGS=rtconfig.CXXFLAGS, + AR=rtconfig.AR, + ARFLAGS='-rc', + LINK=rtconfig.LINK, + LINKFLAGS=rtconfig.LFLAGS, + CXXCOM='$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES', +) + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iccarm': + env.Replace(CCCOM=['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS=[]) + env.Replace(LINKCOM=env['LINKCOM'] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('.') +libraries_path = SDK_ROOT + '/libraries' if os.path.exists(SDK_ROOT + '/libraries') else os.path.dirname(SDK_ROOT) + '/libraries' +SDK_LIB = libraries_path +Export('SDK_LIB') + +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) +if rtconfig.PLATFORM == 'iccarm': + env.Replace(ASCOM='$AS $ASFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES') +objs.extend(SConscript(os.path.join(libraries_path, 'drivers', 'SConscript'), + variant_dir='build/libraries/drivers', duplicate=0)) +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/applications/SConscript b/bsp/nxp/mcx/mcxc/frdm-mcxc162/applications/SConscript new file mode 100644 index 0000000000..bff421e216 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/applications/SConscript @@ -0,0 +1,14 @@ +from building import * + +cwd = GetCurrentDir() +src = ['main.c'] + +if (GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or + GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_SPI0') or + GetDepend('BSP_USING_RTC') or GetDepend('BSP_USING_WDT') or + GetDepend('BSP_USING_CLOCK_TIMER')): + src += ['peripheral_test.c'] + +group = DefineGroup('Applications', src, depend=[''], CPPPATH=[cwd]) + +Return('group') diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/applications/main.c b/bsp/nxp/mcx/mcxc/frdm-mcxc162/applications/main.c new file mode 100644 index 0000000000..91daf2f2f6 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/applications/main.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <rtdevice.h> +#include "board.h" + +#ifdef RT_USING_FINSH +#include <finsh.h> + +static volatile rt_uint32_t sw2_irq_count; +static volatile rt_uint32_t sw3_irq_count; + +static void button_irq(void *args) +{ + (*(volatile rt_uint32_t *)args)++; +} + +static int button_irq_test(void) +{ + rt_err_t result; + rt_uint32_t sw2_count; + rt_uint32_t sw3_count; + + sw2_irq_count = 0; + sw3_irq_count = 0; + rt_pin_mode(SW2_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_mode(SW3_PIN, PIN_MODE_INPUT_PULLUP); + + result = rt_pin_attach_irq(SW2_PIN, PIN_IRQ_MODE_FALLING, + button_irq, (void *)&sw2_irq_count); + if (result != RT_EOK) + { + return result; + } + + result = rt_pin_attach_irq(SW3_PIN, PIN_IRQ_MODE_FALLING, + button_irq, (void *)&sw3_irq_count); + if (result != RT_EOK) + { + rt_pin_detach_irq(SW2_PIN); + return result; + } + + rt_pin_irq_enable(SW2_PIN, PIN_IRQ_ENABLE); + rt_pin_irq_enable(SW3_PIN, PIN_IRQ_ENABLE); + rt_kprintf("Press SW2 and SW3 within 10 seconds\n"); + rt_thread_mdelay(10000); + rt_pin_irq_enable(SW2_PIN, PIN_IRQ_DISABLE); + rt_pin_irq_enable(SW3_PIN, PIN_IRQ_DISABLE); + rt_pin_detach_irq(SW2_PIN); + rt_pin_detach_irq(SW3_PIN); + sw2_count = sw2_irq_count; + sw3_count = sw3_irq_count; + + rt_kprintf("%s: SW2=%u, SW3=%u interrupt(s)\n", + sw2_count != 0U && sw3_count != 0U ? "PASS" : "FAIL", + (unsigned int)sw2_count, (unsigned int)sw3_count); + + return sw2_count != 0U && sw3_count != 0U ? RT_EOK : -RT_ERROR; +} +MSH_CMD_EXPORT(button_irq_test, count SW2 and SW3 falling-edge interrupts for 10 seconds); + +static void reboot(void) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, reset the MCU); +#endif + +int main(void) +{ + rt_pin_write(LED_RED_PIN, PIN_HIGH); + rt_pin_mode(LED_RED_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_RED_PIN, !rt_pin_read(LED_RED_PIN)); + rt_thread_mdelay(500); + } +} diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/applications/peripheral_test.c b/bsp/nxp/mcx/mcxc/frdm-mcxc162/applications/peripheral_test.c new file mode 100644 index 0000000000..d7d24a62a7 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/applications/peripheral_test.c @@ -0,0 +1,405 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <rtdevice.h> +#include "board.h" +#include "drv_spi.h" + +#ifdef RT_USING_FINSH +#include <finsh.h> + +#if defined(BSP_USING_UART1) || defined(BSP_USING_UART2) +static int uart_loop(int argc, char **argv) +{ + static const rt_uint8_t pattern[] = { + 0x55, 0xAA, 0x00, 0xFF, 0x31, 0xC3, 0x7E, 0x81 + }; + rt_uint8_t received[sizeof(pattern)]; + rt_uint8_t discard; + rt_device_t device; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_size_t length = 0; + rt_tick_t start; + + if (argc != 2 || + (rt_strcmp(argv[1], "uart1") != 0 && rt_strcmp(argv[1], "uart2") != 0)) + { + rt_kprintf("Usage: uart_loop uart1|uart2\n"); + return -RT_EINVAL; + } + + device = rt_device_find(argv[1]); + if (device == RT_NULL) + { + rt_kprintf("FAIL: %s is not enabled\n", argv[1]); + return -RT_ENOSYS; + } + if (rt_device_open(device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX) != RT_EOK) + { + rt_kprintf("FAIL: cannot open %s\n", argv[1]); + return -RT_ERROR; + } + if (rt_device_control(device, RT_DEVICE_CTRL_CONFIG, &config) != RT_EOK) + { + rt_device_close(device); + rt_kprintf("FAIL: cannot configure %s\n", argv[1]); + return -RT_ERROR; + } + + while (rt_device_read(device, 0, &discard, 1) == 1) + { + } + if (rt_device_write(device, 0, pattern, sizeof(pattern)) != sizeof(pattern)) + { + rt_device_close(device); + rt_kprintf("FAIL: %s write\n", argv[1]); + return -RT_EIO; + } + + start = rt_tick_get(); + while (length < sizeof(pattern) && + rt_tick_get() - start < rt_tick_from_millisecond(1000)) + { + length += rt_device_read(device, 0, &received[length], sizeof(pattern) - length); + if (length < sizeof(pattern)) + { + rt_thread_mdelay(1); + } + } + rt_device_close(device); + + if (length != sizeof(pattern) || rt_memcmp(pattern, received, sizeof(pattern)) != 0) + { + rt_kprintf("FAIL: %s loopback received %u/%u bytes\n", argv[1], + (unsigned int)length, (unsigned int)sizeof(pattern)); + return -RT_EIO; + } + + rt_kprintf("PASS: %s 115200-8-N-1 loopback\n", argv[1]); + return RT_EOK; +} +MSH_CMD_EXPORT(uart_loop, test uart1 or uart2 TX to RX loopback); +#endif + +#ifdef BSP_USING_I2C0 +static int p3t1755(void) +{ + struct rt_i2c_bus_device *bus; + rt_uint8_t reg = 0; + rt_uint8_t data[2]; + struct rt_i2c_msg messages[2] = { + { + .addr = 0x48, + .flags = RT_I2C_WR, + .len = 1, + .buf = ®, + }, + { + .addr = 0x48, + .flags = RT_I2C_RD, + .len = sizeof(data), + .buf = data, + }, + }; + rt_int32_t sixteenths; + rt_uint32_t magnitude; + + bus = rt_i2c_bus_device_find("i2c0"); + if (bus == RT_NULL || rt_i2c_transfer(bus, messages, 2) != 2) + { + rt_kprintf("FAIL: P3T1755 did not acknowledge at 0x48\n"); + return -RT_EIO; + } + + sixteenths = (rt_int16_t)(((rt_uint16_t)data[0] << 8) | data[1]) / 16; + magnitude = sixteenths < 0 ? (rt_uint32_t)-sixteenths : (rt_uint32_t)sixteenths; + rt_kprintf("PASS: P3T1755 0x48 temperature %s%u.%04u C\n", + sixteenths < 0 ? "-" : "", (unsigned int)(magnitude / 16), + (unsigned int)((magnitude % 16) * 625)); + + return RT_EOK; +} +MSH_CMD_EXPORT(p3t1755, read onboard P3T1755 temperature with repeated START); +#endif + +#ifdef BSP_USING_SPI0 +static struct rt_spi_device *spi_loop_device; + +static int spi_loop(void) +{ + static const rt_uint8_t transmitted[] = { + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF + }; + struct rt_spi_configuration config = { + .mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB, + .data_width = 8, + .max_hz = 1000000, + }; + rt_uint8_t received[sizeof(transmitted)]; + struct rt_spi_message second = { + .send_buf = &transmitted[8], + .recv_buf = &received[8], + .length = 8, + .cs_take = 0, + .cs_release = 1, + .next = RT_NULL, + }; + struct rt_spi_message first = { + .send_buf = transmitted, + .recv_buf = received, + .length = 8, + .cs_take = 1, + .cs_release = 0, + .next = &second, + }; + + if (spi_loop_device == RT_NULL) + { + if (rt_hw_spi_device_attach("spi0", "spi0_test", GET_PINS(3, 11)) != RT_EOK) + { + rt_kprintf("FAIL: cannot attach spi0_test\n"); + return -RT_ERROR; + } + spi_loop_device = (struct rt_spi_device *)rt_device_find("spi0_test"); + } + + if (rt_spi_configure(spi_loop_device, &config) != RT_EOK) + { + rt_kprintf("FAIL: cannot configure spi0_test\n"); + return -RT_ERROR; + } + + if (rt_spi_transfer_message(spi_loop_device, &first) != RT_NULL || + rt_memcmp(transmitted, received, sizeof(transmitted)) != 0) + { + rt_kprintf("FAIL: spi0 loopback mismatch\n"); + return -RT_EIO; + } + + rt_kprintf("PASS: spi0 compound data loopback\n"); + return RT_EOK; +} +MSH_CMD_EXPORT(spi_loop, test spi0 SDO to SDI compound loopback); +#endif + +#ifdef BSP_USING_WDT +static int wwdt(int argc, char **argv) +{ + rt_device_t device; + rt_uint32_t timeout = 3; + + if (argc != 2 || + (rt_strcmp(argv[1], "refresh") != 0 && rt_strcmp(argv[1], "timeout") != 0)) + { + rt_kprintf("Usage: wwdt refresh|timeout\n"); + return -RT_EINVAL; + } + + device = rt_device_find("wdt"); + if (device == RT_NULL || rt_device_open(device, RT_DEVICE_OFLAG_RDWR) != RT_EOK || + rt_device_control(device, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout) != RT_EOK || + rt_device_control(device, RT_DEVICE_CTRL_WDT_START, RT_NULL) != RT_EOK) + { + rt_kprintf("FAIL: cannot start WWDT0\n"); + return -RT_ERROR; + } + + if (rt_strcmp(argv[1], "timeout") == 0) + { + rt_kprintf("WWDT0 is not refreshed; reset is expected in 3 seconds\n"); + rt_thread_mdelay(5000); + rt_kprintf("FAIL: WWDT0 did not reset the MCU\n"); + return -RT_ERROR; + } + + rt_kprintf("WWDT0 is refreshed every second; press RESET to stop the test\n"); + while (1) + { + rt_device_control(device, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL); + rt_thread_mdelay(1000); + } +} +MSH_CMD_EXPORT(wwdt, test WWDT0 refresh or timeout reset); +#endif + +#ifdef BSP_USING_CTIMER1 +static volatile rt_uint32_t ctimer_events; + +static rt_err_t ctimer_timeout(rt_device_t device, rt_size_t size) +{ + RT_UNUSED(device); + RT_UNUSED(size); + + ctimer_events++; + return RT_EOK; +} + +static int ctimer_test(int argc, char **argv) +{ + rt_clock_timerval_t timeout = { + .sec = 0, + .usec = 100000, + }; + rt_clock_timer_mode_t mode; + rt_device_t device; + rt_uint32_t frequency = 1000000; + rt_uint32_t minimum; + rt_uint32_t maximum; + rt_err_t result; + + if (argc != 3 || rt_strcmp(argv[1], "timer1") != 0 || + (rt_strcmp(argv[2], "oneshot") != 0 && rt_strcmp(argv[2], "periodic") != 0)) + { + rt_kprintf("Usage: ctimer_test timer1 oneshot|periodic\n"); + rt_kprintf("timer0 is reserved for the RT-Thread clock-time backend\n"); + return -RT_EINVAL; + } + + device = rt_device_find(argv[1]); + if (device == RT_NULL || rt_device_open(device, RT_DEVICE_OFLAG_RDWR) != RT_EOK) + { + rt_kprintf("FAIL: %s is not enabled\n", argv[1]); + return -RT_ENOSYS; + } + + mode = rt_strcmp(argv[2], "oneshot") == 0 ? CLOCK_TIMER_MODE_ONESHOT : CLOCK_TIMER_MODE_PERIOD; + minimum = mode == CLOCK_TIMER_MODE_ONESHOT ? 1 : 4; + maximum = mode == CLOCK_TIMER_MODE_ONESHOT ? 1 : 6; + ctimer_events = 0; + rt_device_set_rx_indicate(device, ctimer_timeout); + + result = rt_device_control(device, CLOCK_TIMER_CTRL_FREQ_SET, &frequency); + if (result == RT_EOK) + { + result = rt_device_control(device, CLOCK_TIMER_CTRL_MODE_SET, &mode); + } + if (result == RT_EOK && + rt_device_write(device, 0, &timeout, sizeof(timeout)) != sizeof(timeout)) + { + result = -RT_EIO; + } + if (result == RT_EOK) + { + rt_thread_mdelay(mode == CLOCK_TIMER_MODE_ONESHOT ? 350 : 550); + rt_device_control(device, CLOCK_TIMER_CTRL_STOP, RT_NULL); + } + rt_device_set_rx_indicate(device, RT_NULL); + rt_device_close(device); + + if (result != RT_EOK || ctimer_events < minimum || ctimer_events > maximum) + { + rt_kprintf("FAIL: %s %s generated %u interrupts\n", argv[1], argv[2], + (unsigned int)ctimer_events); + return -RT_ERROR; + } + + rt_kprintf("PASS: %s %s generated %u interrupt(s)\n", argv[1], argv[2], + (unsigned int)ctimer_events); + return RT_EOK; +} +MSH_CMD_EXPORT(ctimer_test, test CTIMER1 one - shot or periodic mode); +#endif + +#ifdef BSP_USING_CTIMER0 +static int ctimer0_test(void) +{ + struct rt_clock_hrtimer timer; + rt_tick_t start; + rt_tick_t elapsed; + rt_err_t result; + + rt_clock_hrtimer_delay_init(&timer); + start = rt_tick_get(); + result = rt_clock_hrtimer_start(&timer, rt_clock_time_get_freq() / 10U); + if (result == RT_EOK) + { + result = rt_completion_wait(&timer.completion, rt_tick_from_millisecond(1000)); + } + elapsed = rt_tick_get() - start; + if (result != RT_EOK) + { + rt_clock_hrtimer_stop(&timer); + } + rt_clock_hrtimer_delay_detach(&timer); + + if (result != RT_EOK || elapsed < rt_tick_from_millisecond(90) || + elapsed > rt_tick_from_millisecond(200)) + { + rt_kprintf("FAIL: timer0 clock-time one-shot took %u ticks\n", + (unsigned int)elapsed); + return -RT_ERROR; + } + + rt_kprintf("PASS: timer0 clock-time one-shot took %u ticks\n", + (unsigned int)elapsed); + return RT_EOK; +} +MSH_CMD_EXPORT(ctimer0_test, test CTIMER0 through the RT - Thread clock - time backend); +#endif + +#if defined(BSP_USING_RTC) && defined(RT_USING_ALARM) +static struct rt_completion rtc_alarm_completion; + +static void rtc_alarm_callback(rt_alarm_t alarm, time_t timestamp) +{ + RT_UNUSED(alarm); + RT_UNUSED(timestamp); + + rt_completion_done(&rtc_alarm_completion); +} + +static int rtc_alarm_test(void) +{ + struct rt_alarm_setup setup = { + .flag = RT_ALARM_ONESHOT, + }; + rt_device_t device; + rt_alarm_t alarm; + time_t timestamp; + rt_err_t result; + + device = rt_device_find("rtc"); + if (device == RT_NULL || rt_device_open(device, RT_DEVICE_OFLAG_RDWR) != RT_EOK || + get_timestamp(×tamp) != RT_EOK) + { + rt_kprintf("FAIL: cannot open rtc\n"); + return -RT_ERROR; + } + + timestamp += 3; +#ifdef RT_ALARM_USING_LOCAL_TIME + localtime_r(×tamp, &setup.wktime); +#else + gmtime_r(×tamp, &setup.wktime); +#endif + rt_completion_init(&rtc_alarm_completion); + alarm = rt_alarm_create(rtc_alarm_callback, &setup); + if (alarm == RT_NULL) + { + rt_kprintf("FAIL: cannot create RTC0 alarm\n"); + rt_device_close(device); + return -RT_ERROR; + } + if (rt_alarm_start(alarm) != RT_EOK) + { + rt_kprintf("FAIL: cannot start RTC0 alarm\n"); + rt_alarm_delete(alarm); + rt_device_close(device); + return -RT_ERROR; + } + + result = rt_completion_wait(&rtc_alarm_completion, rt_tick_from_millisecond(6000)); + rt_alarm_delete(alarm); + rt_device_close(device); + rt_kprintf("%s: RTC0 one-shot alarm\n", result == RT_EOK ? "PASS" : "FAIL"); + + return result; +} +MSH_CMD_EXPORT(rtc_alarm_test, test RTC0 one - shot alarm after 3 seconds); +#endif + +#endif /* RT_USING_FINSH */ diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/Kconfig b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/Kconfig new file mode 100644 index 0000000000..28518a5ab5 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/Kconfig @@ -0,0 +1,96 @@ +menu "Hardware Drivers Config" + +config SOC_MCXC162 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + +config BSP_USING_PIN + bool "Enable GPIO" + select RT_USING_PIN + default y + +menuconfig BSP_USING_UART + bool "Enable LPUART" + select RT_USING_SERIAL + default y + +if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable LPUART0 as uart0" + default y + + config BSP_USING_UART1 + bool "Enable LPUART1 as uart1" + default n + + config BSP_USING_UART2 + bool "Enable LPUART2 as uart2" + default n +endif + +menuconfig BSP_USING_I2C + bool "Enable LPI2C" + select RT_USING_I2C + default n + +if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable LPI2C0 as i2c0" + default y +endif + +menuconfig BSP_USING_SPI + bool "Enable LPSPI" + select BSP_USING_PIN + select RT_USING_SPI + default n + +if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable LPSPI0 as spi0" + default y +endif + +config BSP_USING_RTC + bool "Enable RTC0 as rtc" + select RT_USING_RTC + default n + +config BSP_USING_WDT + bool "Enable WWDT0 as wdt" + select RT_USING_WDT + default n + +menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CTIMER hardware timers" + select RT_USING_CLOCK_TIME + default n + +if BSP_USING_CLOCK_TIMER + config BSP_USING_CTIMER0 + bool "Enable CTIMER0 as timer0" + default y + + config BSP_USING_CTIMER1 + bool "Enable CTIMER1 as timer1" + depends on BSP_USING_CTIMER0 + default n +endif + +menuconfig BSP_USING_PWM + bool "Enable FLEXPWM" + select RT_USING_PWM + default n + +if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable FLEXPWM0 SM0 as pwm0" + default y +endif + +endmenu +endmenu diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/clock_config.c b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/clock_config.c new file mode 100644 index 0000000000..61fe425adc --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/clock_config.c @@ -0,0 +1,29 @@ +/* + * Copyright 2026 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +#include "fsl_clock.h" + +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockFROHF72M(); +} + +void BOARD_BootClockFROHF72M(void) +{ + /* One wait state is required before raising the core clock to 72 MHz. */ + FMU0->FCTRL = (FMU0->FCTRL & ~FMU_FCTRL_RWSC_MASK) | FMU_FCTRL_RWSC(1U); + + CLOCK_SetClockDiv(kCLOCK_DivFRO_LF, 1U); + CLOCK_SetupFRO12MClocking(); + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 1U); + CLOCK_SetupFROHFClocking(BOARD_BOOTCLOCKFROHF72M_CORE_CLOCK); + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); + + SystemCoreClock = BOARD_BOOTCLOCKFROHF72M_CORE_CLOCK; +} diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/clock_config.h b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/clock_config.h new file mode 100644 index 0000000000..5b46b01267 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/clock_config.h @@ -0,0 +1,17 @@ +/* + * Copyright 2026 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +#define BOARD_BOOTCLOCKFROHF72M_CORE_CLOCK 72000000U + +void BOARD_InitBootClocks(void); +void BOARD_BootClockFROHF72M(void); + +#endif diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/pin_mux.c new file mode 100644 index 0000000000..60dc5d33f8 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/pin_mux.c @@ -0,0 +1,135 @@ +/* + * Copyright 2026 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" + +#include "fsl_clock.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_reset.h" +#include "rtconfig.h" + +static void configure_pin(PORT_Type *port, uint32_t pin, port_mux_t mux, + uint16_t pull, uint16_t drive) +{ + const port_pin_config_t config = { + .pullSelect = pull, + .pullValueSelect = kPORT_LowPullResistor, + .slewRate = kPORT_FastSlewRate, + .passiveFilterEnable = kPORT_PassiveFilterDisable, + .openDrainEnable = kPORT_OpenDrainDisable, + .driveStrength = drive, + .driveStrength1 = kPORT_NormalDriveStrength, + .mux = mux, + .inputBuffer = kPORT_InputBufferEnable, + .invertInput = kPORT_InputNormal, + .lockRegister = kPORT_UnlockRegister, + }; + + PORT_SetPinConfig(port, pin, &config); +} + +#ifdef BSP_USING_UART0 +static void init_uart0_pins(void) +{ + CLOCK_EnableClock(kCLOCK_GatePORT0); + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); + + configure_pin(PORT0, 2U, kPORT_MuxAlt2, kPORT_PullDisable, kPORT_HighDriveStrength); + configure_pin(PORT0, 3U, kPORT_MuxAlt2, kPORT_PullUp, kPORT_LowDriveStrength); +} +#endif + +#ifdef BSP_USING_UART1 +static void init_uart1_pins(void) +{ + CLOCK_EnableClock(kCLOCK_GatePORT2); + RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn); + + configure_pin(PORT2, 12U, kPORT_MuxAlt3, kPORT_PullDisable, kPORT_LowDriveStrength); + configure_pin(PORT2, 13U, kPORT_MuxAlt3, kPORT_PullDisable, kPORT_LowDriveStrength); +} +#endif + +#ifdef BSP_USING_UART2 +static void init_uart2_pins(void) +{ + CLOCK_EnableClock(kCLOCK_GatePORT3); + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn); + + configure_pin(PORT3, 12U, kPORT_MuxAlt3, kPORT_PullDisable, kPORT_LowDriveStrength); + configure_pin(PORT3, 13U, kPORT_MuxAlt3, kPORT_PullDisable, kPORT_LowDriveStrength); +} +#endif + +#ifdef BSP_USING_I2C0 +static void init_i2c0_pins(void) +{ + CLOCK_EnableClock(kCLOCK_GatePORT3); + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kLPI2C0_RST_SHIFT_RSTn); + + configure_pin(PORT3, 27U, kPORT_MuxAlt2, kPORT_PullDisable, kPORT_LowDriveStrength); + configure_pin(PORT3, 28U, kPORT_MuxAlt2, kPORT_PullDisable, kPORT_LowDriveStrength); +} +#endif + +#ifdef BSP_USING_SPI0 +static void init_spi0_pins(void) +{ + const gpio_pin_config_t cs_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U, + }; + + CLOCK_EnableClock(kCLOCK_GatePORT3); + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kLPSPI0_RST_SHIFT_RSTn); + + configure_pin(PORT3, 8U, kPORT_MuxAlt2, kPORT_PullDisable, kPORT_LowDriveStrength); + configure_pin(PORT3, 9U, kPORT_MuxAlt2, kPORT_PullDisable, kPORT_LowDriveStrength); + configure_pin(PORT3, 10U, kPORT_MuxAlt2, kPORT_PullDisable, kPORT_LowDriveStrength); + configure_pin(PORT3, 11U, kPORT_MuxAsGpio, kPORT_PullDisable, kPORT_LowDriveStrength); + GPIO_PinInit(GPIO3, 11U, &cs_config); +} +#endif + +#ifdef BSP_USING_PWM0 +static void init_pwm0_pins(void) +{ + CLOCK_EnableClock(kCLOCK_GatePORT3); + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kFLEXPWM0_RST_SHIFT_RSTn); + + configure_pin(PORT3, 0U, kPORT_MuxAlt5, kPORT_PullDisable, kPORT_LowDriveStrength); + configure_pin(PORT3, 1U, kPORT_MuxAlt5, kPORT_PullDisable, kPORT_LowDriveStrength); +} +#endif + +void BOARD_InitBootPins(void) +{ +#ifdef BSP_USING_UART0 + init_uart0_pins(); +#endif +#ifdef BSP_USING_UART1 + init_uart1_pins(); +#endif +#ifdef BSP_USING_UART2 + init_uart2_pins(); +#endif +#ifdef BSP_USING_I2C0 + init_i2c0_pins(); +#endif +#ifdef BSP_USING_SPI0 + init_spi0_pins(); +#endif +#ifdef BSP_USING_PWM0 + init_pwm0_pins(); +#endif +} diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/pin_mux.h b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/pin_mux.h new file mode 100644 index 0000000000..3f2697b315 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/MCUX_Config/board/pin_mux.h @@ -0,0 +1,12 @@ +/* + * Copyright 2026 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +void BOARD_InitBootPins(void); + +#endif diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/SConscript b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/SConscript new file mode 100644 index 0000000000..3d47e7f082 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/SConscript @@ -0,0 +1,25 @@ +Import('rtconfig') + +from building import * + +cwd = GetCurrentDir() +src = Split(''' +board.c +MCUX_Config/board/clock_config.c +MCUX_Config/board/pin_mux.c +''') + +linkflags = '' +if rtconfig.PLATFORM == 'armclang': + linkflags = ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + +group = DefineGroup( + 'Drivers', + src, + depend=[''], + CPPPATH=[cwd, cwd + '/MCUX_Config/board'], + CPPDEFINES=['CPU_MCXC162VFT'], + LINKFLAGS=linkflags, +) + +Return('group') diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/board.c b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/board.c new file mode 100644 index 0000000000..76de70a5c8 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/board.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <rthw.h> +#include <rtthread.h> + +#include "board.h" +#include "pin_mux.h" + +void SysTick_Handler(void) +{ + rt_interrupt_enter(); + rt_tick_increase(); + rt_interrupt_leave(); +} + +void rt_hw_board_init(void) +{ + BOARD_InitBootPins(); + BOARD_InitBootClocks(); + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(PendSV_IRQn, (1U << __NVIC_PRIO_BITS) - 1U); + +#ifdef RT_USING_HEAP + rt_system_heap_init(HEAP_BEGIN, HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint32_t cycles = SystemCoreClock / 1000000U * us; + uint32_t start = SysTick->VAL; + uint32_t elapsed = 0; + uint32_t reload = SysTick->LOAD + 1U; + + while (elapsed < cycles) + { + uint32_t now = SysTick->VAL; + elapsed += (start >= now) ? (start - now) : (start + reload - now); + start = now; + } +} + +void rt_hw_cpu_reset(void) +{ + NVIC_SystemReset(); +} diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/board.h b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/board.h new file mode 100644 index 0000000000..5355a34b25 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/board/board.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include <rtthread.h> + +#include "clock_config.h" +#include "fsl_common.h" + +#define GET_PINS(port, pin) ((port) * 32 + (pin)) + +#define LED_RED_PIN GET_PINS(2, 3) +#define LED_GREEN_PIN GET_PINS(2, 7) +#define LED_BLUE_PIN GET_PINS(1, 10) +#define SW2_PIN GET_PINS(3, 14) +#define SW3_PIN GET_PINS(3, 29) + +#if defined(__ARMCC_VERSION) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +extern int Image$$ARM_LIB_STACK$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void *)&Image$$ARM_LIB_STACK$$ZI$$Base) +#elif defined(__ICCARM__) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) +#elif defined(__GNUC__) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) +#endif + +void rt_hw_board_init(void); +void rt_hw_us_delay(rt_uint32_t us); +void rt_hw_cpu_reset(void); + +#endif diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/project.ewp b/bsp/nxp/mcx/mcxc/frdm-mcxc162/project.ewp new file mode 100644 index 0000000000..1227155137 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/project.ewp @@ -0,0 +1,2503 @@ +<project> + <fileVersion>4</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>37</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>ExePath</name> + <state>Debug\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Debug\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Debug\List</state> + </option> + <option> + <name>BrowseInfoPath</name> + <state>Debug\BrowseInfo</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Automatic choice of formatter, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Automatic choice of formatter, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>9.60.3.7274</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>9.60.3.7274</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>MCXC162 NXP MCXC162</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>1</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>1</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>34</version> + <state>58</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + 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<name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state /> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state /> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + <option> + <name>TrustZone</name> + <state>0</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGAarch64Abi</name> + <state>0</state> + </option> + <option> + <name>OG_32_64Device</name> + <state>0</state> + </option> + <option> + <name>BuildFilesPath</name> + <state>Debug\</state> + </option> + <option> + <name>PointerAuthentication</name> + <state>0</state> + </option> + <option> + <name>FPU64</name> + <state>1</state> + </option> + <option> + <name>OG_32_64DeviceCoreSlave</name> + <version>34</version> + <state>58</state> + </option> + <option> + <name>GOutputSo</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>39</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCDefines</name> + <state /> + <state>CPU_MCXC162VFT</state> + <state>__RTTHREAD__</state> + <state>CLOCKS_PER_SEC=RT_TICK_PER_SECOND</state> + <state>RT_USING_DLIBC</state> + <state>RT_USING_LIBC</state> + <state>_DLIB_ADD_EXTRA_SYMBOLS=0</state> + <state>__RT_IPC_SOURCE__</state> + <state>__RT_KERNEL_SOURCE__</state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>1</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + 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<name>$PROJ_DIR$\..\..\..\..\..\src\scheduler_up.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\src\thread.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\src\timer.c</name> + </file> + </group> + <group> + <name>Libc</name> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\common\cctype.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\common\cstdlib.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\common\cstring.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\common\ctime.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\common\cunistd.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\common\cwchar.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\dlib\environ.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\dlib\syscall_close.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\dlib\syscall_open.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\dlib\syscall_read.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\dlib\syscall_write.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\components\libc\compilers\dlib\syscalls.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\src\klibc\kerrno.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\src\klibc\kstdio.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\src\klibc\kstring.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\src\klibc\rt_vsscanf.c</name> + </file> + </group> + <group> + <name>Libraries</name> + <file> + <name>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_clock.c</name> + </file> + <file> + <name>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_common.c</name> + </file> + <file> + <name>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_common_arm.c</name> + </file> + <file> + <name>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_gpio.c</name> + </file> + <file> + <name>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_lpuart.c</name> + </file> + <file> + <name>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_reset.c</name> + </file> + <file> + <name>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_spc.c</name> + </file> + <file> + <name>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\startup_MCXC162.c</name> + </file> + <file> + <name>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\system_MCXC162.c</name> + </file> + </group> + <group> + <name>utc_UTest</name> + </group> + <group> + <name>utestcases</name> + </group> +</project> diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/project.eww b/bsp/nxp/mcx/mcxc/frdm-mcxc162/project.eww new file mode 100644 index 0000000000..48e99341c1 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/project.eww @@ -0,0 +1,8 @@ +<?xml version="1.0" encoding="iso-8859-1"?> + +<workspace> + <project> + <path>$WS_DIR$\project.ewp</path> + </project> + <batchBuild/> +</workspace> diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/project.uvprojx b/bsp/nxp/mcx/mcxc/frdm-mcxc162/project.uvprojx new file mode 100644 index 0000000000..01b1b1dbd9 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/project.uvprojx @@ -0,0 +1,1174 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + <SchemaVersion>2.1</SchemaVersion> + <Header>### uVision Project, (C) Keil Software</Header> + <Targets> + <Target> + <TargetName>rtthread-frdm-mcxc162</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>6230000::V6.23::ARMCLANG</pCCUsed> + <uAC6>1</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>MCXC162VFT</Device> + <Vendor>NXP</Vendor> + <PackID>NXP.MCXC162_DFP.26.06.00</PackID> + <PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL> + <Cpu>IRAM(0x20000000,0x00003000) IROM(0x00000000,0x00010000) CPUTYPE("Cortex-M23") CLOCK(72000000) ELITTLE</Cpu> + <FlashUtilSpec /> + <StartupFile /> + <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FLASH_64 -FS00000000 -FL010000 -FP0($$Device:MCXC162VFT$devices\MCXC162\arm\FLASH_64.FLM))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:MCXC162VFT$devices\MCXC162\fsl_device_registers.h</RegisterFile> + <MemoryEnv /> + <Cmp /> + <Asm /> + <Linker /> + <OHString /> + <InfinionOptionDll /> + <SLE66CMisc /> + <SLE66AMisc /> + <SLE66LinkerMisc /> + <SFDFile>$$Device:MCXC162VFT$devices\MCXC162\MCXC162.xml</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath /> + <IncludePath /> + <LibPath /> + <RegisterFilePath /> + <DBRegisterFilePath /> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>0</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\build\keil\</OutputDirectory> + <OutputName>rtthread</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\build\keil\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name /> + <UserProg2Name /> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name /> + <UserProg2Name /> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name /> + <UserProg2Name /> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString /> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument /> + <IncludeLibraryModules /> + <ComprImg>1</ComprImg> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments> </SimDllArguments> + <SimDlgDll>DARMCM1.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM23</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments> </TargetDllArguments> + <TargetDlgDll>TARMCM1.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM23</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2V8M.DLL</Flash2> + <Flash3>"" ()</Flash3> + <Flash4 /> + <pFcarmOut /> + <pFcarmGrp /> + <pFcArmRoot /> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + 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<StartAddress>0x30060000</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x10000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x3000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector /> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>1</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>3</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> + <VariousControls> + <MiscControls>--target=arm-arm-none-eabi -mcpu=cortex-m23 -mfloat-abi=soft</MiscControls> + <Define>__RTTHREAD__, CPU_MCXC162VFT, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC</Define> + <Undefine /> + <IncludePath>..\..\..\..\..\libcpu\arm\cortex-m23;packages\nxp-mcx-series-latest\MCXC162\periph3;applications;..\..\..\..\..\components\libc\posix\ipc;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\net\utest;board;..\..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\..\libcpu\arm\common;..\..\..\..\..\components\libc\posix\io\poll;..\..\..\..\..\include;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\..\components\libc\compilers\common\include;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\finsh;.;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\drivers\smp_call;..\..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\..\components\drivers\include;packages\nxp-mcx-series-latest\MCXC162\drivers;packages\nxp-mcx-series-latest\MCXC162;board\MCUX_Config\board;packages\nxp-mcx-cmsis-latest\Core\Include;..\..\..\..\..\components\libc\compilers\common\extension;..\libraries\drivers\mcxc162</IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <ClangAsOpt>1</ClangAsOpt> + <VariousControls> + <MiscControls>-x assembler-with-cpp</MiscControls> + <Define /> + <Undefine /> + <IncludePath /> + </VariousControls> + </Aads> + <LDads> + <umfTarg>0</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x00000000</TextAddressRange> + <DataAddressRange>0x02000000</DataAddressRange> + <pXoBase /> + <ScatterFile>.\packages\nxp-mcx-series-latest\MCXC162\arm\MCXC162_flash.scf</ScatterFile> + <IncludeLibs /> + <IncludeLibsPath /> + <Misc> --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)</Misc> + <LinkerInputFile /> + <DisabledWarnings /> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>Applications</GroupName> + <Files> + <File> + <FileName>main.c</FileName> + <FileType>1</FileType> + <FilePath>applications\main.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>CPU</GroupName> + <Files> + <File> + <FileName>atomic_arm.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\libcpu\arm\common\atomic_arm.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>div0.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\libcpu\arm\common\div0.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>showmem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\libcpu\arm\common\showmem.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>context_rvds.S</FileName> + <FileType>2</FileType> + <FilePath>..\..\..\..\..\libcpu\arm\cortex-m23\context_rvds.S</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cpuport.c</FileName> + <FileType>1</FileType> + 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<FilePath>..\libraries\drivers\mcxc162\drv_uart.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Finsh</GroupName> + <Files> + <File> + <FileName>shell.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\finsh\shell.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>msh.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\finsh\msh.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>msh_parse.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\finsh\msh_parse.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cmd.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\finsh\cmd.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Kernel</GroupName> + <Files> + <File> + <FileName>clock.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\clock.c</FilePath> + <FileOption> + <FileArmAds> + <Cads> + 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<VariousControls> + <MiscControls> </MiscControls> + <Define>__RT_KERNEL_SOURCE__</Define> + <Undefine> </Undefine> + <IncludePath> </IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + </Files> + <Files> + <File> + <FileName>irq.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\irq.c</FilePath> + <FileOption> + <FileArmAds> + <Cads> + <VariousControls> + <MiscControls> </MiscControls> + <Define>__RT_KERNEL_SOURCE__</Define> + <Undefine> </Undefine> + <IncludePath> </IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + </Files> + <Files> + <File> + <FileName>kservice.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\kservice.c</FilePath> + <FileOption> + <FileArmAds> + <Cads> + <VariousControls> + <MiscControls> </MiscControls> + <Define>__RT_KERNEL_SOURCE__</Define> + <Undefine> </Undefine> + <IncludePath> </IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + 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+ <Cads> + <VariousControls> + <MiscControls> </MiscControls> + <Define>__RT_KERNEL_SOURCE__</Define> + <Undefine> </Undefine> + <IncludePath> </IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + </Files> + <Files> + <File> + <FileName>scheduler_up.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\scheduler_up.c</FilePath> + <FileOption> + <FileArmAds> + <Cads> + <VariousControls> + <MiscControls> </MiscControls> + <Define>__RT_KERNEL_SOURCE__</Define> + <Undefine> </Undefine> + <IncludePath> </IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + </Files> + <Files> + <File> + <FileName>thread.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\thread.c</FilePath> + <FileOption> + <FileArmAds> + <Cads> + <VariousControls> + <MiscControls> </MiscControls> + <Define>__RT_KERNEL_SOURCE__</Define> + <Undefine> </Undefine> + <IncludePath> </IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + </Files> + <Files> + <File> + <FileName>timer.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\timer.c</FilePath> + <FileOption> + <FileArmAds> + <Cads> + <VariousControls> + <MiscControls> </MiscControls> + <Define>__RT_KERNEL_SOURCE__</Define> + <Undefine> </Undefine> + <IncludePath> </IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + </Files> + </Group> + <Group> + <GroupName>Libc</GroupName> + <Files> + <File> + <FileName>syscall_mem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>syscalls.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cctype.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\libc\compilers\common\cctype.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cstdlib.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\libc\compilers\common\cstdlib.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cstring.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\libc\compilers\common\cstring.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>ctime.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\libc\compilers\common\ctime.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cunistd.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\libc\compilers\common\cunistd.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cwchar.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\components\libc\compilers\common\cwchar.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>kerrno.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\klibc\kerrno.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>kstdio.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\klibc\kstdio.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>kstring.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\klibc\kstring.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>rt_vsnprintf_tiny.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>rt_vsscanf.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\..\src\klibc\rt_vsscanf.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Libraries</GroupName> + <Files> + <File> + <FileName>fsl_clock.c</FileName> + <FileType>1</FileType> + <FilePath>packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_clock.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>fsl_common.c</FileName> + <FileType>1</FileType> + <FilePath>packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_common.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>fsl_common_arm.c</FileName> + <FileType>1</FileType> + <FilePath>packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_common_arm.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>fsl_gpio.c</FileName> + <FileType>1</FileType> + <FilePath>packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_gpio.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>fsl_lpuart.c</FileName> + <FileType>1</FileType> + <FilePath>packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_lpuart.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>fsl_reset.c</FileName> + <FileType>1</FileType> + <FilePath>packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_reset.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>fsl_spc.c</FileName> + <FileType>1</FileType> + <FilePath>packages\nxp-mcx-series-latest\MCXC162\drivers\fsl_spc.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>startup_MCXC162.c</FileName> + <FileType>1</FileType> + <FilePath>packages\nxp-mcx-series-latest\MCXC162\startup_MCXC162.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>system_MCXC162.c</FileName> + <FileType>1</FileType> + <FilePath>packages\nxp-mcx-series-latest\MCXC162\system_MCXC162.c</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + </Targets> + <RTE> + <apis /> + <components /> + <files /> + </RTE> + <LayerInfo> + <Layers> + <Layer> + <LayName>template</LayName> + <LayPrjMark>1</LayPrjMark> + </Layer> + </Layers> + </LayerInfo> +</Project> diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/rtconfig.h b/bsp/nxp/mcx/mcxc/frdm-mcxc162/rtconfig.h new file mode 100644 index 0000000000..b3652cf078 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/rtconfig.h @@ -0,0 +1,407 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +#define SOC_MCX + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice options */ + +/* end of kservice options */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_USING_HW_ATOMIC_8 +#define ARCH_USING_HW_ATOMIC_16 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M23 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 1024 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 2048 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +#define PKG_USING_NXP_MCX_CMSIS_DRIVER +#define PKG_USING_NXP_MCX_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_NXP_MCX_SERIES_DRIVER +#define PKG_USING_NXP_MCX_SERIES_DRIVER_LATEST_VERSION +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Hardware Drivers Config */ + +#define SOC_MCXC162 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_PIN +#define BSP_USING_UART +#define BSP_USING_UART0 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/rtconfig.py b/bsp/nxp/mcx/mcxc/frdm-mcxc162/rtconfig.py new file mode 100644 index 0000000000..f26c4c63b3 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/rtconfig.py @@ -0,0 +1,134 @@ +import os + +ARCH = 'arm' +CPU = 'cortex-m23' +CROSS_TOOL = os.getenv('RTT_CC', 'gcc') +BOARD_NAME = 'frdm-mcxc162' +BSP_LIBRARY_TYPE = 'MCXC162' +EXEC_PATH = os.getenv('RTT_EXEC_PATH', '') +BUILD = 'debug' + + +def _resolve_package_path(package_name, marker): + bsp_root = os.path.dirname(os.path.abspath(__file__)) + search_roots = ['libraries', os.path.join('..', 'libraries'), 'packages'] + + for search_root in search_roots: + package_path = os.path.join(search_root, package_name) + if os.path.isfile(os.path.join(bsp_root, package_path, marker)): + return package_path.replace('\\', '/') + + return os.path.join('packages', package_name).replace('\\', '/') + + +NXP_MCX_CMSIS_ROOT = _resolve_package_path('nxp-mcx-cmsis-latest', 'Core/Include/core_cm23.h') +NXP_MCX_SERIES_ROOT = _resolve_package_path('nxp-mcx-series-latest', 'MCXC162/gcc/MCXC162_flash.ld') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' +else: + raise RuntimeError('Unsupported toolchain: ' + CROSS_TOOL) + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=cortex-m23 -mthumb -mfloat-abi=soft -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -std=c99' + CXXFLAGS = DEVICE + ' -Wall -fno-exceptions -fno-rtti' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + LFLAGS += ' -specs=nano.specs -specs=nosys.specs' + LFLAGS += ' -Wl,--gc-sections,-Map=rtthread.map,--print-memory-usage' + LFLAGS += ' -T"' + NXP_MCX_SERIES_ROOT + '/MCXC162/gcc/MCXC162_flash.ld"' + + if BUILD == 'debug': + CFLAGS += ' -Os -gdwarf-2' + CXXFLAGS += ' -Os -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + CXXFLAGS += ' -Os' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET\n' + CPATH = '' + LPATH = '' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + ' -shared -fPIC -nostartfiles -static-libgcc -Wl,--gc-sections,-z,max-page-size=0x4' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET\n' + +elif PLATFORM == 'armclang': + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M23' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m23 -mfloat-abi=soft' + CFLAGS += ' -funsigned-char -fshort-enums -fshort-wchar -ffunction-sections -std=c99' + CXXFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m23 -mfloat-abi=soft' + CXXFLAGS += ' -funsigned-char -fshort-enums -fshort-wchar -ffunction-sections -fno-exceptions -fno-rtti' + AFLAGS = DEVICE + ' --apcs=interwork' + LFLAGS = DEVICE + ' --strict --info sizes --info totals --info unused --info veneers' + LFLAGS += ' --list rtthread.map' + LFLAGS += ' --scatter "' + NXP_MCX_SERIES_ROOT + '/MCXC162/arm/MCXC162_flash.scf"' + + if BUILD == 'debug': + CFLAGS += ' -O1 -g -gdwarf-3' + CXXFLAGS += ' -O1 -g -gdwarf-3' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + CXXFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin\nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + dlib_config = os.path.normpath(os.path.join(EXEC_PATH, '..', 'inc', 'c', 'DLib_Config_Normal.h')) + CFLAGS = ' --cpu=Cortex-M23 --fpu=None --endian=little -e' + CFLAGS += ' --dlib_config "' + dlib_config + '" --diag_suppress Pa050' + CXXFLAGS = CFLAGS + AFLAGS = ' -s+ -r --cpu Cortex-M23 --fpu None' + LFLAGS = ' --config "' + NXP_MCX_SERIES_ROOT + '/MCXC162/iar/MCXC162_flash.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + if BUILD == 'debug': + CFLAGS += ' --debug -On' + CXXFLAGS += ' --debug -On' + else: + CFLAGS += ' -Oh' + CXXFLAGS += ' -Oh' + + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + + +def dist_handle(BSP_ROOT, dist_dir): + import sys + + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), '..', 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/template.ewp b/bsp/nxp/mcx/mcxc/frdm-mcxc162/template.ewp new file mode 100644 index 0000000000..21658bbdd3 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/template.ewp @@ -0,0 +1,2202 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>4</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>37</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>ExePath</name> + <state>Debug\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Debug\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Debug\List</state> + </option> + <option> + <name>BrowseInfoPath</name> + <state>Debug\BrowseInfo</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Automatic choice of formatter, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Automatic choice of formatter, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>9.60.3.7274</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>9.60.3.7274</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>MCXC162 NXP MCXC162</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>1</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>1</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>34</version> + <state>58</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>34</version> + <state>58</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>MCXC162 NXP MCXC162</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>34</version> + <state>58</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + <option> + <name>TrustZone</name> + <state>0</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGAarch64Abi</name> + <state>0</state> + </option> + <option> + <name>OG_32_64Device</name> + <state>0</state> + </option> + <option> + <name>BuildFilesPath</name> + <state>Debug\</state> + </option> + <option> + <name>PointerAuthentication</name> + <state>0</state> + </option> + <option> + <name>FPU64</name> + <state>1</state> + </option> + <option> + <name>OG_32_64DeviceCoreSlave</name> + <version>34</version> + <state>58</state> + </option> + <option> + <name>GOutputSo</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>39</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCDefines</name> + <state></state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>1</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state></state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>00000000</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>1</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state></state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state></state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CCIncludePath2</name> + <state></state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>1</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + <option> + <name>OICompilerExtraOption</name> + <state>1</state> + </option> + <option> + <name>CCStackProtection</name> + <state>0</state> + </option> + <option> + <name>CCPointerAutentiction</name> + <state>0</state> + </option> + <option> + <name>CCBranchTargetIdentification</name> + <state>0</state> + </option> + <option> + <name>CCPosRadRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosSharedSlave</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>12</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state></state> + </option> + <option> + <name>AWarnRange1</name> + <state></state> + </option> + <option> + <name>AWarnRange2</name> + <state></state> + </option> + <option> + <name>ADebug</name> + <state>1</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state></state> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + 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<name>OOCOutputFile</name> + <state></state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>4</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <buildSequence>inputOutputBased</buildSequence> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>28</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>rtthread.out</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state></state> + </option> + <option> + <name>IlinkDefines</name> + <state></state> + </option> + <option> + <name>IlinkConfigDefines</name> + <state></state> + </option> + <option> + <name>IlinkMapFile</name> + <state>1</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + <state>1</state> + </option> + <option> + <name>IlinkIcfFile</name> + <state>$PROJ_DIR$\packages\nxp-mcx-series-latest\MCXC162\iar\MCXC162_flash.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state></state> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state></state> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state></state> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state></state> + </option> + <option> + <name>IlinkOverrideProgramEntryLabel</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabelSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabel</name> + <state>__iar_program_start</state> + </option> + <option> + <name>DoFill</name> + <state>0</state> + </option> + <option> + <name>FillerByte</name> + <state>0xFF</state> + </option> + <option> + <name>FillerStart</name> + <state>0x0</state> + </option> + <option> + <name>FillerEnd</name> + <state>0x0</state> + </option> + <option> + <name>CrcSize</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CrcAlign</name> + <state>1</state> + </option> + <option> + <name>CrcPoly</name> + <state>0x11021</state> + </option> + <option> + <name>CrcCompl</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + <state>1</state> + </option> + <option> + <name>IlinkOptInline</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsAllow</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state></state> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkTrustzoneImportLibraryOut</name> + <state>###Unitialized###</state> + </option> + <option> + <name>OILinkExtraOption</name> + <state>1</state> + </option> + <option> + <name>IlinkRawBinaryFile2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign2</name> + <state></state> + </option> + <option> + <name>IlinkLogCrtRoutineSelection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFragmentInfo</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInlining</name> + <state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> + <option> + <name>IlinkProcessor</name> + <state>1</state> + </option> + <option> + <name>IlinkFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>IlinkSharedSlave</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>2</archiveVersion> + <data /> + </settings> + </configuration> +</project> diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc162/template.uvprojx b/bsp/nxp/mcx/mcxc/frdm-mcxc162/template.uvprojx new file mode 100644 index 0000000000..c6b16e3b82 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc162/template.uvprojx @@ -0,0 +1,401 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + + <SchemaVersion>2.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>rtthread-frdm-mcxc162</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>6230000::V6.23::ARMCLANG</pCCUsed> + <uAC6>1</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>MCXC162VFT</Device> + <Vendor>NXP</Vendor> + <PackID>NXP.MCXC162_DFP.26.06.00</PackID> + <PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL> + <Cpu>IRAM(0x20000000,0x00003000) IROM(0x00000000,0x00010000) CPUTYPE("Cortex-M23") CLOCK(72000000) ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FLASH_64 -FS00000000 -FL010000 -FP0($$Device:MCXC162VFT$devices\MCXC162\arm\FLASH_64.FLM))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:MCXC162VFT$devices\MCXC162\fsl_device_registers.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:MCXC162VFT$devices\MCXC162\MCXC162.xml</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>0</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\build\keil\</OutputDirectory> + <OutputName>rtthread</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\build\keil\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments> </SimDllArguments> + <SimDlgDll>DARMCM1.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM23</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments> </TargetDllArguments> + <TargetDlgDll>TARMCM1.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM23</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2V8M.DLL</Flash2> + <Flash3>"" ()</Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>0</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M23"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> + <RvdsCdeCp>0</RvdsCdeCp> + <nBranchProt>0</nBranchProt> + <hadIRAM2>0</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <nSecure>0</nSecure> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>0</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x3000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x10000</Size> + </IROM> + <XRAM> + <Type>1</Type> + <StartAddress>0x30060000</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x10000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x3000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>1</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>3</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> + <VariousControls> + <MiscControls>--target=arm-arm-none-eabi -mcpu=cortex-m23 -mfloat-abi=soft</MiscControls> + <Define>RT_USING_ARM_LIBC</Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <ClangAsOpt>1</ClangAsOpt> + <VariousControls> + <MiscControls>-x assembler-with-cpp</MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>0</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x00000000</TextAddressRange> + <DataAddressRange>0x02000000</DataAddressRange> + <pXoBase></pXoBase> + <ScatterFile>.\packages\nxp-mcx-series-latest\MCXC162\arm\MCXC162_flash.scf</ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc>--keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)</Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + </Target> + </Targets> + + <RTE> + <apis/> + <components/> + <files/> + </RTE> + + <LayerInfo> + <Layers> + <Layer> + <LayName>template</LayName> + <LayPrjMark>1</LayPrjMark> + </Layer> + </Layers> + </LayerInfo> + +</Project> diff --git a/bsp/nxp/mcx/mcxc/libraries/Kconfig b/bsp/nxp/mcx/mcxc/libraries/Kconfig index 0230c5b335..c26e76ebed 100644 --- a/bsp/nxp/mcx/mcxc/libraries/Kconfig +++ b/bsp/nxp/mcx/mcxc/libraries/Kconfig @@ -1,5 +1,4 @@ config SOC_MCX bool - select ARCH_ARM_CORTEX_M0 select PKG_USING_NXP_MCX_CMSIS_DRIVER select PKG_USING_NXP_MCX_SERIES_DRIVER diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/SConscript b/bsp/nxp/mcx/mcxc/libraries/drivers/SConscript index 34b64cb75d..9d95d2b478 100644 --- a/bsp/nxp/mcx/mcxc/libraries/drivers/SConscript +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/SConscript @@ -2,6 +2,10 @@ from building import * cwd = GetCurrentDir() +if GetDepend('SOC_MCXC162'): + group = SConscript('mcxc162/SConscript') + Return('group') + src = [] if GetDepend('BSP_USING_PIN'): diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/SConscript b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/SConscript new file mode 100644 index 0000000000..9f6c71b411 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/SConscript @@ -0,0 +1,32 @@ +from building import * + +cwd = GetCurrentDir() +src = [] + +if GetDepend('BSP_USING_PIN'): + src += ['drv_pin.c'] + +if GetDepend('BSP_USING_UART'): + src += ['drv_uart.c'] + +if GetDepend('BSP_USING_I2C'): + src += ['drv_i2c.c'] + +if GetDepend('BSP_USING_SPI'): + src += ['drv_spi.c'] + +if GetDepend('BSP_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('BSP_USING_WDT'): + src += ['drv_wdt.c'] + +if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_hwtimer.c'] + +if GetDepend('BSP_USING_PWM'): + src += ['drv_pwm.c'] + +group = DefineGroup('Drivers', src, depend=[''], CPPPATH=[cwd]) + +Return('group') diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_hwtimer.c b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_hwtimer.c new file mode 100644 index 0000000000..3d4b6ac722 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_hwtimer.c @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-09-03 Alex Yang Add MCXC162 CTIMER0/1 support + */ + +#include <rtthread.h> +#include <rtdevice.h> + +#include "fsl_clock.h" +#include "fsl_ctimer.h" + +#if defined(BSP_USING_CLOCK_TIMER) && \ + (defined(BSP_USING_CTIMER0) || defined(BSP_USING_CTIMER1)) + +#define MCXC162_CTIMER_SOURCE_FREQ 72000000U + +struct mcxc162_hwtimer +{ + rt_clock_timer_t timer; + CTIMER_Type *base; + rt_uint8_t instance; + const char *name; +}; + +enum +{ +#ifdef BSP_USING_CTIMER0 + MCXC162_CTIMER0_INDEX, +#endif +#ifdef BSP_USING_CTIMER1 + MCXC162_CTIMER1_INDEX, +#endif +}; + +static struct mcxc162_hwtimer mcxc162_hwtimers[] = { +#ifdef BSP_USING_CTIMER0 + { + .base = CTIMER0, + .instance = 0U, + .name = "timer0", + }, +#endif +#ifdef BSP_USING_CTIMER1 + { + .base = CTIMER1, + .instance = 1U, + .name = "timer1", + }, +#endif +}; + +static struct mcxc162_hwtimer *mcxc162_hwtimer_from_device(rt_clock_timer_t *timer) +{ + return rt_container_of(timer, struct mcxc162_hwtimer, timer); +} + +static void mcxc162_hwtimer_init(rt_clock_timer_t *timer, rt_uint32_t state) +{ + struct mcxc162_hwtimer *device = mcxc162_hwtimer_from_device(timer); + ctimer_config_t config; + + if (!state) + { + DisableIRQ(device->instance == 0U ? CTIMER0_IRQn : CTIMER1_IRQn); + CTIMER_Deinit(device->base); + return; + } + + if (device->instance == 0U) + { + CLOCK_SetClockDiv(kCLOCK_DivCTIMER0, 1U); + CLOCK_AttachClk(kFRO_HF_to_CTIMER0); + } + else + { + CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1U); + CLOCK_AttachClk(kFRO_HF_to_CTIMER1); + } + + CTIMER_GetDefaultConfig(&config); + CTIMER_Init(device->base, &config); +} + +static rt_err_t mcxc162_hwtimer_start(rt_clock_timer_t *timer, rt_uint32_t count, + rt_clock_timer_mode_t mode) +{ + struct mcxc162_hwtimer *device = mcxc162_hwtimer_from_device(timer); + ctimer_match_config_t match = { + .matchValue = count, + .enableCounterReset = true, + .enableCounterStop = mode == CLOCK_TIMER_MODE_ONESHOT, + .outControl = kCTIMER_Output_NoAction, + .outPinInitState = false, + .enableInterrupt = true, + }; + IRQn_Type irq = device->instance == 0U ? CTIMER0_IRQn : CTIMER1_IRQn; + + DisableIRQ(irq); + CTIMER_StopTimer(device->base); + CTIMER_Reset(device->base); + CTIMER_ClearStatusFlags(device->base, kCTIMER_Match0Flag); + CTIMER_SetupMatch(device->base, kCTIMER_Match_0, &match); + NVIC_ClearPendingIRQ(irq); + EnableIRQ(irq); + CTIMER_StartTimer(device->base); + + return RT_EOK; +} + +static void mcxc162_hwtimer_stop(rt_clock_timer_t *timer) +{ + struct mcxc162_hwtimer *device = mcxc162_hwtimer_from_device(timer); + IRQn_Type irq = device->instance == 0U ? CTIMER0_IRQn : CTIMER1_IRQn; + + DisableIRQ(irq); + CTIMER_StopTimer(device->base); + CTIMER_ClearStatusFlags(device->base, kCTIMER_Match0Flag); + NVIC_ClearPendingIRQ(irq); +} + +static rt_uint32_t mcxc162_hwtimer_count_get(rt_clock_timer_t *timer) +{ + return mcxc162_hwtimer_from_device(timer)->base->TC; +} + +static rt_err_t mcxc162_hwtimer_control(rt_clock_timer_t *timer, rt_uint32_t command, + void *argument) +{ + struct mcxc162_hwtimer *device = mcxc162_hwtimer_from_device(timer); + rt_uint32_t *frequency = (rt_uint32_t *)argument; + uint32_t source; + uint64_t divider; + + if (command != CLOCK_TIMER_CTRL_FREQ_SET) + { + return -RT_ENOSYS; + } + + source = CLOCK_GetCTimerClkFreq(device->instance); + divider = ((uint64_t)source + (*frequency / 2U)) / *frequency; + if ((divider == 0U) || (divider > 0x100000000ULL)) + { + return -RT_EINVAL; + } + + CTIMER_SetPrescale(device->base, (uint32_t)(divider - 1U)); + *frequency = source / (uint32_t)divider; + + return RT_EOK; +} + +static const struct rt_clock_timer_ops mcxc162_hwtimer_ops = { + .init = mcxc162_hwtimer_init, + .start = mcxc162_hwtimer_start, + .stop = mcxc162_hwtimer_stop, + .count_get = mcxc162_hwtimer_count_get, + .control = mcxc162_hwtimer_control, +}; + +static const struct rt_clock_timer_info mcxc162_hwtimer_info = { + .maxfreq = MCXC162_CTIMER_SOURCE_FREQ, + .minfreq = 1, + .maxcnt = 0xFFFFFFFFU, + .cntmode = CLOCK_TIMER_CNTMODE_UP, +}; + +int rt_hw_hwtimer_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t index; + + for (index = 0; index < sizeof(mcxc162_hwtimers) / sizeof(mcxc162_hwtimers[0]); index++) + { + mcxc162_hwtimers[index].timer.info = &mcxc162_hwtimer_info; + mcxc162_hwtimers[index].timer.ops = &mcxc162_hwtimer_ops; + if (rt_clock_timer_register(&mcxc162_hwtimers[index].timer, + mcxc162_hwtimers[index].name, + mcxc162_hwtimers[index].base) != RT_EOK) + { + result = -RT_ERROR; + } + } + + if (result == RT_EOK) + { + result = rt_device_open(&mcxc162_hwtimers[0].timer.parent, + RT_DEVICE_OFLAG_RDWR); + } + + return result; +} +INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); + +#ifdef BSP_USING_CTIMER0 +void CTIMER0_IRQHandler(void) +{ + rt_interrupt_enter(); + + if ((CTIMER_GetStatusFlags(CTIMER0) & kCTIMER_Match0Flag) != 0U) + { + CTIMER_ClearStatusFlags(CTIMER0, kCTIMER_Match0Flag); + rt_clock_timer_isr(&mcxc162_hwtimers[MCXC162_CTIMER0_INDEX].timer); + } + + rt_interrupt_leave(); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#ifdef BSP_USING_CTIMER1 +void CTIMER1_IRQHandler(void) +{ + rt_interrupt_enter(); + + if ((CTIMER_GetStatusFlags(CTIMER1) & kCTIMER_Match0Flag) != 0U) + { + CTIMER_ClearStatusFlags(CTIMER1, kCTIMER_Match0Flag); + rt_clock_timer_isr(&mcxc162_hwtimers[MCXC162_CTIMER1_INDEX].timer); + } + + rt_interrupt_leave(); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_hwtimer.h b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_hwtimer.h new file mode 100644 index 0000000000..8ab2cc1093 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_hwtimer.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_MCXC162_HWTIMER_H__ +#define __DRV_MCXC162_HWTIMER_H__ + +int rt_hw_hwtimer_init(void); + +#endif /* __DRV_MCXC162_HWTIMER_H__ */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_i2c.c b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_i2c.c new file mode 100644 index 0000000000..dc7dfa1443 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_i2c.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <rtdevice.h> + +#include "fsl_clock.h" +#include "fsl_lpi2c.h" + +#if defined(RT_USING_I2C) && defined(BSP_USING_I2C0) + +#define MCXC162_LPI2C_READ_CHUNK 256U +#define MCXC162_LPI2C_START_CMD LPI2C_MTDR_CMD(4U) +#define MCXC162_I2C_UNSUPPORTED (RT_I2C_ADDR_10BIT | RT_I2C_IGNORE_NACK | RT_I2C_NO_READ_ACK) + +static struct rt_i2c_bus_device i2c0_bus; + +static status_t mcxc162_i2c_wait_tx_ready(void) +{ + uint32_t flags; + status_t status; + + do + { + flags = LPI2C_MasterGetStatusFlags(LPI2C0); + status = LPI2C_MasterCheckAndClearError(LPI2C0, flags); + if (status != kStatus_Success) + { + return status; + } + } while ((flags & (uint32_t)kLPI2C_MasterTxReadyFlag) == 0U); + + return kStatus_Success; +} + +static status_t mcxc162_i2c_restart(const struct rt_i2c_msg *msg) +{ + lpi2c_direction_t direction; + status_t status; + + status = mcxc162_i2c_wait_tx_ready(); + if (status != kStatus_Success) + { + return status; + } + + direction = (msg->flags & RT_I2C_RD) != 0U ? kLPI2C_Read : kLPI2C_Write; + LPI2C0->MTDR = MCXC162_LPI2C_START_CMD | + ((uint32_t)msg->addr << 1U) | (uint32_t)direction; + + return kStatus_Success; +} + +static status_t mcxc162_i2c_transfer_message(const struct rt_i2c_msg *msg) +{ + rt_size_t offset = 0U; + rt_size_t remaining = msg->len; + rt_size_t chunk; + status_t status; + + if ((msg->flags & RT_I2C_RD) == 0U) + { + if (remaining == 0U) + { + return kStatus_Success; + } + return LPI2C_MasterSend(LPI2C0, msg->buf, remaining); + } + + while (remaining != 0U) + { + chunk = remaining > MCXC162_LPI2C_READ_CHUNK ? MCXC162_LPI2C_READ_CHUNK : remaining; + if (offset != 0U) + { + status = mcxc162_i2c_restart(msg); + if (status != kStatus_Success) + { + return status; + } + } + + status = LPI2C_MasterReceive(LPI2C0, &msg->buf[offset], chunk); + if (status != kStatus_Success) + { + return status; + } + + offset += chunk; + remaining -= chunk; + } + + return kStatus_Success; +} + +static rt_ssize_t mcxc162_i2c_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + rt_uint32_t i; + status_t status; + + if (num == 0U || (msgs[0].flags & RT_I2C_NO_START) != 0U || + (msgs[num - 1U].flags & RT_I2C_NO_STOP) != 0U) + { + return 0; + } + + for (i = 0U; i < num; i++) + { + if ((msgs[i].flags & MCXC162_I2C_UNSUPPORTED) != 0U) + { + return 0; + } + if (i != 0U && (msgs[i].flags & RT_I2C_NO_START) != 0U && + (((msgs[i - 1U].flags | msgs[i].flags) & RT_I2C_RD) != 0U || + msgs[i - 1U].addr != msgs[i].addr)) + { + return 0; + } + } + + if (bus->config.usage_freq != bus->config.max_hz) + { + LPI2C_MasterSetBaudRate(LPI2C0, CLOCK_GetLpi2cClkFreq(0U), bus->config.max_hz); + bus->config.usage_freq = bus->config.max_hz; + } + + LPI2C_MasterEnable(LPI2C0, true); + LPI2C_SlaveEnable(LPI2C0, false); + status = LPI2C_MasterStart(LPI2C0, msgs[0].addr, + (msgs[0].flags & RT_I2C_RD) != 0U ? kLPI2C_Read : kLPI2C_Write); + if (status != kStatus_Success) + { + return 0; + } + + for (i = 0U; i < num; i++) + { + if (i != 0U && (msgs[i].flags & RT_I2C_NO_START) == 0U) + { + /* ERR053261 requires a START between consecutive receive commands. */ + status = mcxc162_i2c_restart(&msgs[i]); + } + if (status == kStatus_Success) + { + status = mcxc162_i2c_transfer_message(&msgs[i]); + } + if (status != kStatus_Success) + { + break; + } + } + + if (LPI2C_MasterStop(LPI2C0) != kStatus_Success) + { + return 0; + } + + return status == kStatus_Success ? num : i; +} + +static const struct rt_i2c_bus_device_ops mcxc162_i2c_ops = { + .master_xfer = mcxc162_i2c_xfer, +}; + +int rt_hw_i2c_init(void) +{ + lpi2c_master_config_t config; + + CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1U); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C0); + + LPI2C_MasterGetDefaultConfig(&config); + config.baudRate_Hz = 100000U; + LPI2C_MasterInit(LPI2C0, &config, CLOCK_GetLpi2cClkFreq(0U)); + + i2c0_bus.config.max_hz = config.baudRate_Hz; + i2c0_bus.config.usage_freq = config.baudRate_Hz; + i2c0_bus.ops = &mcxc162_i2c_ops; + return rt_i2c_bus_device_register(&i2c0_bus, "i2c0"); +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C && BSP_USING_I2C0 */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pin.c b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pin.c new file mode 100644 index 0000000000..19f04c34af --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pin.c @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "drv_pin.h" + +#include "fsl_clock.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_reset.h" + +#ifdef RT_USING_PIN + +#define PIN_PORT(pin) ((rt_uint32_t)(pin) / 32U) +#define PIN_INDEX(pin) ((rt_uint32_t)(pin) % 32U) +#define PIN_COUNT ((sizeof(gpio_bases) / sizeof(gpio_bases[0])) * 32U) + +struct mcxc162_pin_irq +{ + rt_base_t pin; + gpio_interrupt_config_t mode; + void (*handler)(void *args); + void *args; + struct mcxc162_pin_irq *next; +}; + +static GPIO_Type * const gpio_bases[] = GPIO_BASE_PTRS; +static PORT_Type * const port_bases[] = PORT_BASE_PTRS; +static const IRQn_Type gpio_irqs[] = GPIO_IRQS; +static const clock_ip_name_t port_clocks[] = { + kCLOCK_GatePORT0, + kCLOCK_GatePORT1, + kCLOCK_GatePORT2, + kCLOCK_GatePORT3, +}; +static const reset_ip_name_t port_resets[] = { + kPORT0_RST_SHIFT_RSTn, + kPORT1_RST_SHIFT_RSTn, + kPORT2_RST_SHIFT_RSTn, + kPORT3_RST_SHIFT_RSTn, +}; +static struct mcxc162_pin_irq *pin_irqs; +static rt_uint32_t enabled_masks[4]; + +static rt_bool_t is_valid_pin(rt_base_t pin) +{ + return pin >= 0 && (rt_ubase_t)pin < PIN_COUNT; +} + +static struct mcxc162_pin_irq *find_pin_irq(rt_base_t pin) +{ + struct mcxc162_pin_irq *irq = pin_irqs; + + while (irq != RT_NULL && irq->pin != pin) + { + irq = irq->next; + } + + return irq; +} + +static gpio_interrupt_config_t get_irq_mode(rt_uint8_t mode) +{ + switch (mode) + { + case PIN_IRQ_MODE_RISING: + return kGPIO_InterruptRisingEdge; + case PIN_IRQ_MODE_FALLING: + return kGPIO_InterruptFallingEdge; + case PIN_IRQ_MODE_RISING_FALLING: + return kGPIO_InterruptEitherEdge; + case PIN_IRQ_MODE_HIGH_LEVEL: + return kGPIO_InterruptLogicOne; + case PIN_IRQ_MODE_LOW_LEVEL: + return kGPIO_InterruptLogicZero; + default: + return kGPIO_InterruptStatusFlagDisabled; + } +} + +static void mcxc162_pin_mode(rt_device_t device, rt_base_t pin, rt_uint8_t mode) +{ + gpio_pin_config_t gpio_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U, + }; + port_pin_config_t port_config = { + .pullSelect = kPORT_PullDisable, + .pullValueSelect = kPORT_LowPullResistor, + .slewRate = kPORT_FastSlewRate, + .passiveFilterEnable = kPORT_PassiveFilterDisable, + .openDrainEnable = kPORT_OpenDrainDisable, + .driveStrength = kPORT_LowDriveStrength, + .driveStrength1 = kPORT_NormalDriveStrength, + .mux = kPORT_MuxAsGpio, + .inputBuffer = kPORT_InputBufferEnable, + .invertInput = kPORT_InputNormal, + .lockRegister = kPORT_UnlockRegister, + }; + + (void)device; + + if (!is_valid_pin(pin)) + { + return; + } + + switch (mode) + { + case PIN_MODE_OUTPUT: + gpio_config.pinDirection = kGPIO_DigitalOutput; + gpio_config.outputLogic = + (gpio_bases[PIN_PORT(pin)]->PDOR >> PIN_INDEX(pin)) & 1U; + break; + case PIN_MODE_INPUT_PULLUP: + gpio_config.pinDirection = kGPIO_DigitalInput; + port_config.pullSelect = kPORT_PullUp; + break; + case PIN_MODE_INPUT_PULLDOWN: + gpio_config.pinDirection = kGPIO_DigitalInput; + port_config.pullSelect = kPORT_PullDown; + break; + case PIN_MODE_OUTPUT_OD: + gpio_config.pinDirection = kGPIO_DigitalOutput; + gpio_config.outputLogic = 1U; + port_config.openDrainEnable = kPORT_OpenDrainEnable; + break; + default: + gpio_config.pinDirection = kGPIO_DigitalInput; + break; + } + + PORT_SetPinConfig(port_bases[PIN_PORT(pin)], PIN_INDEX(pin), &port_config); + GPIO_PinInit(gpio_bases[PIN_PORT(pin)], PIN_INDEX(pin), &gpio_config); +} + +static void mcxc162_pin_write(rt_device_t device, rt_base_t pin, rt_uint8_t value) +{ + (void)device; + + if (!is_valid_pin(pin)) + { + return; + } + + GPIO_PinWrite(gpio_bases[PIN_PORT(pin)], PIN_INDEX(pin), value); +} + +static rt_ssize_t mcxc162_pin_read(rt_device_t device, rt_base_t pin) +{ + (void)device; + + if (!is_valid_pin(pin)) + { + return -RT_EINVAL; + } + + return GPIO_PinRead(gpio_bases[PIN_PORT(pin)], PIN_INDEX(pin)); +} + +static rt_err_t mcxc162_pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*handler)(void *args), void *args) +{ + struct mcxc162_pin_irq *irq; + gpio_interrupt_config_t irq_mode = get_irq_mode(mode); + rt_base_t level; + + (void)device; + + if (!is_valid_pin(pin) || handler == RT_NULL || + irq_mode == kGPIO_InterruptStatusFlagDisabled) + { + return -RT_EINVAL; + } + + irq = find_pin_irq(pin); + if (irq != RT_NULL) + { + return irq->mode == irq_mode && irq->handler == handler && irq->args == args ? RT_EOK : -RT_EBUSY; + } + + GPIO_SetPinInterruptConfig(gpio_bases[PIN_PORT(pin)], PIN_INDEX(pin), + kGPIO_InterruptStatusFlagDisabled); + irq = rt_malloc(sizeof(*irq)); + if (irq == RT_NULL) + { + return -RT_ENOMEM; + } + + irq->pin = pin; + irq->mode = irq_mode; + irq->handler = handler; + irq->args = args; + level = rt_hw_interrupt_disable(); + irq->next = pin_irqs; + pin_irqs = irq; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t mcxc162_pin_detach_irq(struct rt_device *device, rt_base_t pin) +{ + struct mcxc162_pin_irq **link = &pin_irqs; + struct mcxc162_pin_irq *irq; + rt_uint32_t port; + rt_uint32_t mask; + rt_base_t level; + + (void)device; + + if (!is_valid_pin(pin)) + { + return -RT_EINVAL; + } + + port = PIN_PORT(pin); + mask = 1UL << PIN_INDEX(pin); + + GPIO_SetPinInterruptConfig(gpio_bases[port], PIN_INDEX(pin), + kGPIO_InterruptStatusFlagDisabled); + enabled_masks[port] &= ~mask; + if (enabled_masks[port] == 0U) + { + DisableIRQ(gpio_irqs[port]); + } + + level = rt_hw_interrupt_disable(); + while (*link != RT_NULL && (*link)->pin != pin) + { + link = &(*link)->next; + } + + irq = *link; + if (irq != RT_NULL) + { + *link = irq->next; + } + rt_hw_interrupt_enable(level); + + if (irq != RT_NULL) + { + rt_free(irq); + } + + return RT_EOK; +} + +static rt_err_t mcxc162_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint8_t enabled) +{ + struct mcxc162_pin_irq *irq; + rt_uint32_t port; + rt_uint32_t mask; + rt_base_t level; + + (void)device; + + if (!is_valid_pin(pin)) + { + return -RT_EINVAL; + } + + irq = find_pin_irq(pin); + if (irq == RT_NULL) + { + return -RT_EINVAL; + } + + port = PIN_PORT(pin); + mask = 1UL << PIN_INDEX(pin); + + level = rt_hw_interrupt_disable(); + if (enabled == PIN_IRQ_ENABLE) + { + GPIO_GpioClearInterruptFlags(gpio_bases[port], mask); + GPIO_SetPinInterruptConfig(gpio_bases[port], PIN_INDEX(pin), irq->mode); + enabled_masks[port] |= mask; + EnableIRQ(gpio_irqs[port]); + } + else + { + GPIO_SetPinInterruptConfig(gpio_bases[port], PIN_INDEX(pin), + kGPIO_InterruptStatusFlagDisabled); + enabled_masks[port] &= ~mask; + if (enabled_masks[port] == 0U) + { + DisableIRQ(gpio_irqs[port]); + } + } + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static void mcxc162_gpio_irq_handler(rt_uint32_t port) +{ + struct mcxc162_pin_irq *irq; + rt_uint32_t flags; + + rt_interrupt_enter(); + + flags = GPIO_GpioGetInterruptFlags(gpio_bases[port]); + GPIO_GpioClearInterruptFlags(gpio_bases[port], flags); + flags &= enabled_masks[port]; + + for (irq = pin_irqs; irq != RT_NULL; irq = irq->next) + { + if (PIN_PORT(irq->pin) == port && + (flags & (1UL << PIN_INDEX(irq->pin))) != 0U) + { + irq->handler(irq->args); + } + } + + rt_interrupt_leave(); +} + +void GPIO0_IRQHandler(void) +{ + mcxc162_gpio_irq_handler(0U); +} + +void GPIO1_IRQHandler(void) +{ + mcxc162_gpio_irq_handler(1U); +} + +void GPIO2_IRQHandler(void) +{ + mcxc162_gpio_irq_handler(2U); +} + +void GPIO3_IRQHandler(void) +{ + mcxc162_gpio_irq_handler(3U); +} + +static const struct rt_pin_ops mcxc162_pin_ops = { + .pin_mode = mcxc162_pin_mode, + .pin_write = mcxc162_pin_write, + .pin_read = mcxc162_pin_read, + .pin_attach_irq = mcxc162_pin_attach_irq, + .pin_detach_irq = mcxc162_pin_detach_irq, + .pin_irq_enable = mcxc162_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + rt_uint32_t port; + + for (port = 0U; port < 4U; port++) + { + CLOCK_EnableClock(port_clocks[port]); + RESET_ReleasePeripheralReset(port_resets[port]); + GPIO_PortInit(gpio_bases[port]); + } + + return rt_device_pin_register("pin", &mcxc162_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pin.h b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pin.h new file mode 100644 index 0000000000..950b622b84 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pin.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_PIN_MCXC162_H__ +#define __DRV_PIN_MCXC162_H__ + +#include <rtdevice.h> + +#define GET_PINS(port, pin) ((port) * 32 + (pin)) + +int rt_hw_pin_init(void); + +#endif /* __DRV_PIN_MCXC162_H__ */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pwm.c b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pwm.c new file mode 100644 index 0000000000..84abac72a7 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pwm.c @@ -0,0 +1,287 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-09-03 Alex Yang Add MCXC162 FLEXPWM0 SM0 support + */ + +#include <rtthread.h> +#include <rtdevice.h> + +#include "fsl_clock.h" +#include "fsl_pwm.h" + +#if defined(BSP_USING_PWM) && defined(BSP_USING_PWM0) + +#define MCXC162_PWM_CHANNEL_COUNT 2U +#define MCXC162_PWM_NSEC_PER_SEC 1000000000ULL + +struct mcxc162_pwm +{ + struct rt_device_pwm device; + struct rt_pwm_configuration configuration[MCXC162_PWM_CHANNEL_COUNT]; + rt_bool_t configured[MCXC162_PWM_CHANNEL_COUNT]; + rt_bool_t enabled[MCXC162_PWM_CHANNEL_COUNT]; + rt_uint32_t period; +}; + +static struct mcxc162_pwm mcxc162_pwm; + +static pwm_channels_t mcxc162_pwm_channel(rt_uint32_t channel) +{ + return channel == 0U ? kPWM_PwmA : kPWM_PwmB; +} + +static rt_bool_t mcxc162_pwm_running(void) +{ + return mcxc162_pwm.enabled[0] || mcxc162_pwm.enabled[1]; +} + +static uint16_t mcxc162_pwm_duty(rt_uint32_t pulse, rt_uint32_t period) +{ + return (uint16_t)(((uint64_t)pulse * 65535U + period / 2U) / period); +} + +static rt_err_t mcxc162_pwm_counts(rt_uint32_t period, pwm_clock_prescale_t *prescale, + uint16_t *counts) +{ + uint32_t source = CLOCK_GetFreq(kCLOCK_BusClk); + uint32_t shift; + + for (shift = 0U; shift <= (uint32_t)kPWM_Prescale_Divide_128; shift++) + { + uint64_t divisor = MCXC162_PWM_NSEC_PER_SEC << shift; + uint64_t value = ((uint64_t)source * period + divisor / 2U) / divisor; + + if ((value > 0U) && (value <= 0xFFFFU)) + { + *prescale = (pwm_clock_prescale_t)shift; + *counts = (uint16_t)value; + return RT_EOK; + } + } + + return -RT_EINVAL; +} + +static rt_err_t mcxc162_pwm_reconfigure(rt_uint32_t period) +{ + pwm_clock_prescale_t prescale; + pwm_config_t config; + pwm_signal_param_t signals[MCXC162_PWM_CHANNEL_COUNT]; + uint32_t source = CLOCK_GetFreq(kCLOCK_BusClk); + uint32_t pwm_clock; + uint32_t setup_frequency; + uint16_t counts; + rt_uint32_t index; + + if (mcxc162_pwm_counts(period, &prescale, &counts) != RT_EOK) + { + return -RT_EINVAL; + } + + PWM_StopTimer(FLEXPWM0, kPWM_Control_Module_0); + PWM_OutputDisable(FLEXPWM0, kPWM_PwmA, kPWM_Module_0); + PWM_OutputDisable(FLEXPWM0, kPWM_PwmB, kPWM_Module_0); + + PWM_GetDefaultConfig(&config); + config.prescale = prescale; + config.pairOperation = kPWM_Independent; + config.reloadLogic = kPWM_ReloadPwmFullCycle; + if (PWM_Init(FLEXPWM0, kPWM_Module_0, &config) != kStatus_Success) + { + return -RT_ERROR; + } + + for (index = 0U; index < MCXC162_PWM_CHANNEL_COUNT; index++) + { + signals[index].pwmChannel = mcxc162_pwm_channel(index); + signals[index].dutyCyclePercent = 0U; + signals[index].level = kPWM_HighTrue; + signals[index].deadtimeValue = 0U; + signals[index].faultState = kPWM_PwmFaultState0; + signals[index].pwmchannelenable = false; + } + + pwm_clock = source >> (uint32_t)prescale; + setup_frequency = (pwm_clock + counts - 1U) / counts; + if (PWM_SetupPwm(FLEXPWM0, kPWM_Module_0, signals, + MCXC162_PWM_CHANNEL_COUNT, kPWM_EdgeAligned, + setup_frequency, source) != kStatus_Success) + { + return -RT_ERROR; + } + + PWM_UpdatePwmPeriodAndDutycycle( + FLEXPWM0, kPWM_Module_0, kPWM_PwmA, kPWM_EdgeAligned, counts, + mcxc162_pwm_duty(mcxc162_pwm.configuration[0].pulse, period)); + PWM_UpdatePwmDutycycleHighAccuracy( + FLEXPWM0, kPWM_Module_0, kPWM_PwmB, kPWM_EdgeAligned, + mcxc162_pwm_duty(mcxc162_pwm.configuration[1].pulse, period)); + + PWM_SetupFaultDisableMap(FLEXPWM0, kPWM_Module_0, kPWM_PwmA, + kPWM_faultchannel_0, 0U); + PWM_SetupFaultDisableMap(FLEXPWM0, kPWM_Module_0, kPWM_PwmB, + kPWM_faultchannel_0, 0U); + + for (index = 0U; index < MCXC162_PWM_CHANNEL_COUNT; index++) + { + if (mcxc162_pwm.enabled[index]) + { + PWM_OutputEnable(FLEXPWM0, mcxc162_pwm_channel(index), kPWM_Module_0); + } + } + + PWM_SetPwmLdok(FLEXPWM0, kPWM_Control_Module_0, true); + if (mcxc162_pwm_running()) + { + PWM_StartTimer(FLEXPWM0, kPWM_Control_Module_0); + } + + return RT_EOK; +} + +static rt_err_t mcxc162_pwm_set(struct rt_pwm_configuration *configuration) +{ + rt_uint32_t channel = configuration->channel; + rt_uint32_t other = channel ^ 1U; + rt_uint32_t index; + + if ((channel >= MCXC162_PWM_CHANNEL_COUNT) || (configuration->period == 0U) || + (configuration->pulse > configuration->period) || configuration->complementary || + (configuration->dead_time != 0U) || (configuration->phase != 0U)) + { + return -RT_EINVAL; + } + + if (mcxc162_pwm.enabled[other] && (mcxc162_pwm.period != configuration->period)) + { + return -RT_EINVAL; + } + + if (mcxc162_pwm.period != configuration->period) + { + pwm_clock_prescale_t prescale; + uint16_t counts; + + if (mcxc162_pwm_counts(configuration->period, &prescale, &counts) != RT_EOK) + { + return -RT_EINVAL; + } + + mcxc162_pwm.period = configuration->period; + for (index = 0U; index < MCXC162_PWM_CHANNEL_COUNT; index++) + { + if (mcxc162_pwm.configured[index]) + { + mcxc162_pwm.configuration[index].period = configuration->period; + if (mcxc162_pwm.configuration[index].pulse > configuration->period) + { + mcxc162_pwm.configuration[index].pulse = configuration->period; + } + } + } + + mcxc162_pwm.configuration[channel] = *configuration; + mcxc162_pwm.configured[channel] = RT_TRUE; + return mcxc162_pwm_reconfigure(configuration->period); + } + + mcxc162_pwm.configuration[channel] = *configuration; + mcxc162_pwm.configured[channel] = RT_TRUE; + PWM_UpdatePwmDutycycleHighAccuracy( + FLEXPWM0, kPWM_Module_0, mcxc162_pwm_channel(channel), kPWM_EdgeAligned, + mcxc162_pwm_duty(configuration->pulse, configuration->period)); + PWM_SetPwmLdok(FLEXPWM0, kPWM_Control_Module_0, true); + + return RT_EOK; +} + +static rt_err_t mcxc162_pwm_control(struct rt_device_pwm *device, int command, void *argument) +{ + struct rt_pwm_configuration *configuration = argument; + rt_uint32_t channel = configuration->channel; + struct rt_pwm_configuration updated; + rt_bool_t was_running; + + RT_UNUSED(device); + + if (channel >= MCXC162_PWM_CHANNEL_COUNT) + { + return -RT_EINVAL; + } + + switch (command) + { + case PWM_CMD_ENABLE: + if (!mcxc162_pwm.configured[channel]) + { + return -RT_EINVAL; + } + was_running = mcxc162_pwm_running(); + PWM_OutputEnable(FLEXPWM0, mcxc162_pwm_channel(channel), kPWM_Module_0); + mcxc162_pwm.enabled[channel] = RT_TRUE; + if (!was_running) + { + PWM_StartTimer(FLEXPWM0, kPWM_Control_Module_0); + } + return RT_EOK; + + case PWM_CMD_DISABLE: + PWM_OutputDisable(FLEXPWM0, mcxc162_pwm_channel(channel), kPWM_Module_0); + mcxc162_pwm.enabled[channel] = RT_FALSE; + if (!mcxc162_pwm_running()) + { + PWM_StopTimer(FLEXPWM0, kPWM_Control_Module_0); + } + return RT_EOK; + + case PWM_CMD_SET: + return mcxc162_pwm_set(configuration); + + case PWM_CMD_SET_PERIOD: + updated = mcxc162_pwm.configuration[channel]; + updated.channel = channel; + updated.period = configuration->period; + return mcxc162_pwm_set(&updated); + + case PWM_CMD_SET_PULSE: + if (!mcxc162_pwm.configured[channel]) + { + return -RT_EINVAL; + } + updated = mcxc162_pwm.configuration[channel]; + updated.pulse = configuration->pulse; + return mcxc162_pwm_set(&updated); + + case PWM_CMD_GET: + if (!mcxc162_pwm.configured[channel]) + { + return -RT_EINVAL; + } + *configuration = mcxc162_pwm.configuration[channel]; + return RT_EOK; + + default: + return -RT_ENOSYS; + } +} + +static const struct rt_pwm_ops mcxc162_pwm_ops = { + .control = mcxc162_pwm_control, +}; + +int rt_hw_pwm_init(void) +{ + mcxc162_pwm.configuration[0].channel = 0U; + mcxc162_pwm.configuration[1].channel = 1U; + + return rt_device_pwm_register(&mcxc162_pwm.device, "pwm0", + &mcxc162_pwm_ops, RT_NULL); +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif /* BSP_USING_PWM && BSP_USING_PWM0 */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pwm.h b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pwm.h new file mode 100644 index 0000000000..d31724ee36 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_pwm.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_MCXC162_PWM_H__ +#define __DRV_MCXC162_PWM_H__ + +int rt_hw_pwm_init(void); + +#endif /* __DRV_MCXC162_PWM_H__ */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_rtc.c b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_rtc.c new file mode 100644 index 0000000000..ca0cd70419 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_rtc.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-09-03 Alex Yang Add MCXC162 RTC0 support + */ + +#include <rtthread.h> +#include <rtdevice.h> +#include <sys/time.h> + +#include "fsl_clock.h" +#include "fsl_rtc.h" + +#ifdef BSP_USING_RTC + +static rt_rtc_dev_t mcxc162_rtc; + +static rt_err_t mcxc162_rtc_init(void) +{ + rtc_config_t config; + + CLOCK_SetupFRO16KClocking(kCLOCK_Clk16kToSysAndCore); + RTC_GetDefaultConfig(&config); + RTC_Init(RTC0, &config); + RTC_StartTimer(RTC0); + + return RT_EOK; +} + +static rt_err_t mcxc162_rtc_get_secs(time_t *seconds) +{ + *seconds = (time_t)RTC0->TSR; + + return RT_EOK; +} + +static rt_err_t mcxc162_rtc_set_secs(time_t *seconds) +{ + if ((rt_uint64_t)*seconds > 0xFFFFFFFFULL) + { + return -RT_EINVAL; + } + + RTC_StopTimer(RTC0); + RTC0->TSR = (uint32_t)*seconds; + RTC_StartTimer(RTC0); +#ifdef RT_USING_ALARM + rt_alarm_update(&mcxc162_rtc.parent, 1U); +#endif + + return RT_EOK; +} + +static rt_err_t mcxc162_rtc_get_alarm(struct rt_rtc_wkalarm *alarm) +{ + time_t timestamp = (time_t)RTC0->TAR; + struct tm date; + +#ifdef RT_ALARM_USING_LOCAL_TIME + localtime_r(×tamp, &date); +#else + gmtime_r(×tamp, &date); +#endif + alarm->enable = (RTC_GetEnabledInterrupts(RTC0) & kRTC_AlarmInterruptEnable) != 0U; + alarm->tm_sec = date.tm_sec; + alarm->tm_min = date.tm_min; + alarm->tm_hour = date.tm_hour; + alarm->tm_mday = date.tm_mday; + alarm->tm_mon = date.tm_mon; + alarm->tm_year = date.tm_year; + + return RT_EOK; +} + +static rt_err_t mcxc162_rtc_set_alarm(struct rt_rtc_wkalarm *alarm) +{ + rtc_datetime_t date; + struct tm calendar = { + .tm_sec = alarm->tm_sec, + .tm_min = alarm->tm_min, + .tm_hour = alarm->tm_hour, + .tm_mday = alarm->tm_mday, + .tm_mon = alarm->tm_mon, + .tm_year = alarm->tm_year, + }; +#ifdef RT_ALARM_USING_LOCAL_TIME + time_t timestamp; +#endif + + if (!alarm->enable) + { + RTC_DisableInterrupts(RTC0, kRTC_AlarmInterruptEnable); + DisableIRQ(RTC_IRQn); + RTC_ClearStatusFlags(RTC0, kRTC_AlarmFlag); + return RT_EOK; + } + +#ifdef RT_ALARM_USING_LOCAL_TIME + calendar.tm_isdst = -1; + timestamp = mktime(&calendar); + if (timestamp == (time_t)-1) + { + return -RT_EINVAL; + } + gmtime_r(×tamp, &calendar); +#endif + date.second = (uint8_t)calendar.tm_sec; + date.minute = (uint8_t)calendar.tm_min; + date.hour = (uint8_t)calendar.tm_hour; + date.day = (uint8_t)calendar.tm_mday; + date.month = (uint8_t)(calendar.tm_mon + 1); + date.year = (uint16_t)(calendar.tm_year + 1900); + + if (RTC_SetAlarm(RTC0, &date) != kStatus_Success || RTC0->TAR <= RTC0->TSR) + { + RTC_DisableInterrupts(RTC0, kRTC_AlarmInterruptEnable); + DisableIRQ(RTC_IRQn); + RTC_ClearStatusFlags(RTC0, kRTC_AlarmFlag); + return -RT_EINVAL; + } + + RTC_ClearStatusFlags(RTC0, kRTC_AlarmFlag); + RTC_EnableInterrupts(RTC0, kRTC_AlarmInterruptEnable); + NVIC_ClearPendingIRQ(RTC_IRQn); + EnableIRQ(RTC_IRQn); + + return RT_EOK; +} + +static const struct rt_rtc_ops mcxc162_rtc_ops = { + .init = mcxc162_rtc_init, + .get_secs = mcxc162_rtc_get_secs, + .set_secs = mcxc162_rtc_set_secs, + .get_alarm = mcxc162_rtc_get_alarm, + .set_alarm = mcxc162_rtc_set_alarm, + .get_timeval = RT_NULL, + .set_timeval = RT_NULL, +}; + +void RTC_IRQHandler(void) +{ + rt_interrupt_enter(); + + if ((RTC_GetStatusFlags(RTC0) & kRTC_AlarmFlag) != 0U) + { + RTC_ClearStatusFlags(RTC0, kRTC_AlarmFlag); +#ifdef RT_USING_ALARM + rt_alarm_update(&mcxc162_rtc.parent, 1U); +#endif + } + + rt_interrupt_leave(); + SDK_ISR_EXIT_BARRIER; +} + +int rt_hw_rtc_init(void) +{ + rt_err_t result; + + mcxc162_rtc.ops = &mcxc162_rtc_ops; + + result = rt_hw_rtc_register(&mcxc162_rtc, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL); + if (result != RT_EOK) + { + return result; + } + + return rt_device_init(&mcxc162_rtc.parent); +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_RTC */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_rtc.h b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_rtc.h new file mode 100644 index 0000000000..1605b326be --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_rtc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_MCXC162_RTC_H__ +#define __DRV_MCXC162_RTC_H__ + +int rt_hw_rtc_init(void); + +#endif /* __DRV_MCXC162_RTC_H__ */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_spi.c b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_spi.c new file mode 100644 index 0000000000..680a9aba9f --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_spi.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <rtdevice.h> + +#include "drv_spi.h" +#include "fsl_clock.h" +#include "fsl_lpspi.h" + +#if defined(RT_USING_SPI) && defined(BSP_USING_SPI0) + +#define MCXC162_LPSPI_INTERNAL_PCS kLPSPI_Pcs3 +#define MCXC162_LPSPI_INTERNAL_PCS_FLAG kLPSPI_MasterPcs3 + +static struct rt_spi_bus spi0_bus; + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, + rt_base_t cs_pin) +{ + struct rt_spi_device *device = rt_calloc(1U, sizeof(*device)); + rt_err_t result; + + if (device == RT_NULL) + { + return -RT_ENOMEM; + } + + if (cs_pin != PIN_NONE) + { + rt_pin_write(cs_pin, PIN_HIGH); + } + result = rt_spi_bus_attach_device_cspin(device, device_name, bus_name, + cs_pin, RT_NULL); + if (result != RT_EOK) + { + rt_free(device); + } + + return result; +} + +static rt_err_t mcxc162_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *cfg) +{ + lpspi_master_config_t config; + uint32_t period_ns; + + (void)device; + + if ((cfg->mode & (RT_SPI_SLAVE | RT_SPI_3WIRE | RT_SPI_READY | + RT_SPI_CS_HIGH)) != 0U || + (cfg->data_width != 8U && cfg->data_width != 16U) || cfg->max_hz == 0U) + { + return -RT_EINVAL; + } + + LPSPI_MasterGetDefaultConfig(&config); + config.baudRate = cfg->max_hz; + config.bitsPerFrame = cfg->data_width; + config.cpol = (cfg->mode & RT_SPI_CPOL) != 0U ? kLPSPI_ClockPolarityActiveLow : kLPSPI_ClockPolarityActiveHigh; + config.cpha = (cfg->mode & RT_SPI_CPHA) != 0U ? kLPSPI_ClockPhaseSecondEdge : kLPSPI_ClockPhaseFirstEdge; + config.direction = (cfg->mode & RT_SPI_MSB) != 0U ? kLPSPI_MsbFirst : kLPSPI_LsbFirst; + config.whichPcs = MCXC162_LPSPI_INTERNAL_PCS; + config.pcsActiveHighOrLow = kLPSPI_PcsActiveLow; + + period_ns = 1000000000U / cfg->max_hz; + config.pcsToSckDelayInNanoSec = period_ns / 2U; + config.lastSckToPcsDelayInNanoSec = period_ns / 2U; + config.betweenTransferDelayInNanoSec = period_ns / 2U; + + LPSPI_MasterInit(LPSPI0, &config, CLOCK_GetLpspiClkFreq(0U)); + return RT_EOK; +} + +static void mcxc162_spi_set_cs(struct rt_spi_device *device, rt_bool_t active) +{ + rt_uint8_t level; + + if (device->cs_pin == PIN_NONE || (device->config.mode & RT_SPI_NO_CS) != 0U) + { + return; + } + + level = (device->config.mode & RT_SPI_CS_HIGH) != 0U ? PIN_HIGH : PIN_LOW; + rt_pin_write(device->cs_pin, active ? level : !level); +} + +static rt_ssize_t mcxc162_spi_xfer(struct rt_spi_device *device, + struct rt_spi_message *message) +{ + lpspi_transfer_t transfer = { + .txData = message->send_buf, + .rxData = message->recv_buf, + .dataSize = message->length, + .configFlags = MCXC162_LPSPI_INTERNAL_PCS_FLAG | kLPSPI_MasterPcsContinuous, + }; + status_t status = kStatus_Success; + + if (message->cs_take != 0U) + { + mcxc162_spi_set_cs(device, true); + } + + if (message->length != 0U) + { + status = LPSPI_MasterTransferBlocking(LPSPI0, &transfer); + } + + if (status != kStatus_Success) + { + mcxc162_spi_set_cs(device, false); + return -RT_EIO; + } + + if (message->cs_release != 0U) + { + mcxc162_spi_set_cs(device, false); + } + + return (rt_ssize_t)message->length; +} + +static const struct rt_spi_ops mcxc162_spi_ops = { + .configure = mcxc162_spi_configure, + .xfer = mcxc162_spi_xfer, +}; + +int rt_hw_spi_init(void) +{ + lpspi_master_config_t config; + + CLOCK_SetClockDiv(kCLOCK_DivLPSPI0, 1U); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI0); + + LPSPI_MasterGetDefaultConfig(&config); + LPSPI_MasterInit(LPSPI0, &config, CLOCK_GetLpspiClkFreq(0U)); + + return rt_spi_bus_register(&spi0_bus, "spi0", &mcxc162_spi_ops); +} +INIT_DEVICE_EXPORT(rt_hw_spi_init); + +#endif /* RT_USING_SPI && BSP_USING_SPI0 */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_spi.h b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_spi.h new file mode 100644 index 0000000000..350be3ad4c --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_spi.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_SPI_MCXC162_H__ +#define __DRV_SPI_MCXC162_H__ + +#include <rtdevice.h> + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, + rt_base_t cs_pin); +int rt_hw_spi_init(void); + +#endif /* __DRV_SPI_MCXC162_H__ */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_uart.c b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_uart.c new file mode 100644 index 0000000000..e303be20d3 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_uart.c @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <rtdevice.h> + +#include "drv_uart.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +#if defined(RT_USING_SERIAL) && \ + (defined(BSP_USING_UART0) || defined(BSP_USING_UART1) || defined(BSP_USING_UART2)) + +struct mcxc162_uart +{ + struct rt_serial_device serial; + LPUART_Type *base; + IRQn_Type irqn; + clock_attach_id_t clock_attach; + clock_div_name_t clock_div; + rt_uint8_t instance; + const char *name; +}; + +static void mcxc162_uart_isr(struct mcxc162_uart *uart); + +#ifdef BSP_USING_UART0 +static struct mcxc162_uart uart0 = { + .base = LPUART0, + .irqn = LPUART0_IRQn, + .clock_attach = kFRO_LF_DIV_to_LPUART0, + .clock_div = kCLOCK_DivLPUART0, + .instance = 0U, + .name = "uart0", +}; + +void LPUART0_IRQHandler(void) +{ + mcxc162_uart_isr(&uart0); +} +#endif + +#ifdef BSP_USING_UART1 +static struct mcxc162_uart uart1 = { + .base = LPUART1, + .irqn = LPUART1_IRQn, + .clock_attach = kFRO_LF_DIV_to_LPUART1, + .clock_div = kCLOCK_DivLPUART1, + .instance = 1U, + .name = "uart1", +}; + +void LPUART1_IRQHandler(void) +{ + mcxc162_uart_isr(&uart1); +} +#endif + +#ifdef BSP_USING_UART2 +static struct mcxc162_uart uart2 = { + .base = LPUART2, + .irqn = LPUART2_IRQn, + .clock_attach = kFRO_LF_DIV_to_LPUART2, + .clock_div = kCLOCK_DivLPUART2, + .instance = 2U, + .name = "uart2", +}; + +void LPUART2_IRQHandler(void) +{ + mcxc162_uart_isr(&uart2); +} +#endif + +static struct mcxc162_uart * const uarts[] = { +#ifdef BSP_USING_UART0 + &uart0, +#endif +#ifdef BSP_USING_UART1 + &uart1, +#endif +#ifdef BSP_USING_UART2 + &uart2, +#endif +}; + +static rt_err_t mcxc162_uart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct mcxc162_uart *uart = serial->parent.user_data; + lpuart_config_t config; + + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = cfg->baud_rate; + config.enableTx = true; + config.enableRx = true; + config.isMsb = cfg->bit_order == BIT_ORDER_MSB; + + if (cfg->invert != NRZ_NORMAL || cfg->flowcontrol != RT_SERIAL_FLOWCONTROL_NONE) + { + return -RT_EINVAL; + } + + switch (cfg->data_bits) + { + case DATA_BITS_7: + config.dataBitsCount = kLPUART_SevenDataBits; + break; + case DATA_BITS_8: + config.dataBitsCount = kLPUART_EightDataBits; + break; + default: + return -RT_EINVAL; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + config.stopBitCount = kLPUART_OneStopBit; + break; + case STOP_BITS_2: + config.stopBitCount = kLPUART_TwoStopBit; + break; + default: + return -RT_EINVAL; + } + + switch (cfg->parity) + { + case PARITY_NONE: + config.parityMode = kLPUART_ParityDisabled; + break; + case PARITY_ODD: + config.parityMode = kLPUART_ParityOdd; + break; + case PARITY_EVEN: + config.parityMode = kLPUART_ParityEven; + break; + default: + return -RT_EINVAL; + } + + CLOCK_SetClockDiv(uart->clock_div, 1U); + CLOCK_AttachClk(uart->clock_attach); + + if (LPUART_Init(uart->base, &config, + CLOCK_GetLpuartClkFreq(uart->instance)) != kStatus_Success) + { + return -RT_ERROR; + } + if ((serial->parent.open_flag & RT_DEVICE_FLAG_INT_RX) != 0U) + { + LPUART_EnableInterrupts(uart->base, kLPUART_RxDataRegFullInterruptEnable); + NVIC_ClearPendingIRQ(uart->irqn); + EnableIRQ(uart->irqn); + } + + return RT_EOK; +} + +static rt_err_t mcxc162_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct mcxc162_uart *uart = serial->parent.user_data; + + (void)arg; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + LPUART_DisableInterrupts(uart->base, kLPUART_RxDataRegFullInterruptEnable); + DisableIRQ(uart->irqn); + break; + case RT_DEVICE_CTRL_SET_INT: + LPUART_EnableInterrupts(uart->base, kLPUART_RxDataRegFullInterruptEnable); + EnableIRQ(uart->irqn); + break; + default: + break; + } + + return RT_EOK; +} + +static int mcxc162_uart_putc(struct rt_serial_device *serial, char ch) +{ + struct mcxc162_uart *uart = serial->parent.user_data; + + while ((LPUART_GetStatusFlags(uart->base) & kLPUART_TxDataRegEmptyFlag) == 0U) + { + } + LPUART_WriteByte(uart->base, (uint8_t)ch); + + return 1; +} + +static int mcxc162_uart_getc(struct rt_serial_device *serial) +{ + struct mcxc162_uart *uart = serial->parent.user_data; + + if ((LPUART_GetStatusFlags(uart->base) & kLPUART_RxDataRegFullFlag) != 0U) + { + return LPUART_ReadByte(uart->base); + } + + return -1; +} + +static void mcxc162_uart_isr(struct mcxc162_uart *uart) +{ + uint32_t status; + uint32_t errors = kLPUART_RxOverrunFlag | kLPUART_NoiseErrorFlag | + kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag; + + rt_interrupt_enter(); + + status = LPUART_GetStatusFlags(uart->base); + if ((status & kLPUART_RxDataRegFullFlag) != 0U) + { + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); + } + if ((status & errors) != 0U) + { + LPUART_ClearStatusFlags(uart->base, status & errors); + } + + rt_interrupt_leave(); +} + +static const struct rt_uart_ops mcxc162_uart_ops = { + .configure = mcxc162_uart_configure, + .control = mcxc162_uart_control, + .putc = mcxc162_uart_putc, + .getc = mcxc162_uart_getc, +}; + +int rt_hw_uart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_uint32_t i; + rt_err_t result; + + for (i = 0U; i < sizeof(uarts) / sizeof(uarts[0]); i++) + { + uarts[i]->serial.ops = &mcxc162_uart_ops; + uarts[i]->serial.config = config; + result = rt_hw_serial_register(&uarts[i]->serial, uarts[i]->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uarts[i]); + if (result != RT_EOK) + { + return result; + } + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* RT_USING_SERIAL && BSP_USING_UARTx */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_uart.h b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_uart.h new file mode 100644 index 0000000000..5b31185faa --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_uart.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_UART_MCXC162_H__ +#define __DRV_UART_MCXC162_H__ + +int rt_hw_uart_init(void); + +#endif /* __DRV_UART_MCXC162_H__ */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_wdt.c b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_wdt.c new file mode 100644 index 0000000000..8af4a5162b --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_wdt.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-09-03 Alex Yang Add MCXC162 WWDT0 support + */ + +#include <rtthread.h> +#include <rtdevice.h> + +#include "fsl_clock.h" +#include "fsl_wwdt.h" + +#ifdef BSP_USING_WDT + +#define DBG_TAG "drv.wwdt" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> + +#define MCXC162_WWDT_DEFAULT_TIMEOUT 5U + +struct mcxc162_wwdt +{ + rt_watchdog_t watchdog; + rt_uint32_t timeout; + rt_bool_t started; +}; + +static struct mcxc162_wwdt mcxc162_wwdt = { + .timeout = MCXC162_WWDT_DEFAULT_TIMEOUT, +}; + +static uint32_t mcxc162_wwdt_ticks_per_second(void) +{ + return CLOCK_GetWwdtClkFreq() / 4U; +} + +static rt_err_t mcxc162_wwdt_set_timeout(rt_uint32_t timeout) +{ + uint64_t count = (uint64_t)mcxc162_wwdt_ticks_per_second() * timeout; + + if ((timeout == 0U) || (count > WWDT_TC_COUNT_MASK)) + { + return -RT_EINVAL; + } + + mcxc162_wwdt.timeout = timeout; + if (mcxc162_wwdt.started) + { + WWDT_SetTimeoutValue(WWDT0, (uint32_t)count); + WWDT_Refresh(WWDT0); + } + + return RT_EOK; +} + +static rt_err_t mcxc162_wwdt_init(rt_watchdog_t *watchdog) +{ + RT_UNUSED(watchdog); + + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); + + return RT_EOK; +} + +static rt_err_t mcxc162_wwdt_control(rt_watchdog_t *watchdog, int command, void *argument) +{ + rt_uint32_t *value = (rt_uint32_t *)argument; + + RT_UNUSED(watchdog); + + switch (command) + { + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + *value = mcxc162_wwdt.timeout; + return RT_EOK; + + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + return mcxc162_wwdt_set_timeout(*value); + + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + *value = (WWDT0->TV + mcxc162_wwdt_ticks_per_second() - 1U) / + mcxc162_wwdt_ticks_per_second(); + return RT_EOK; + + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + WWDT_Refresh(WWDT0); + return RT_EOK; + + case RT_DEVICE_CTRL_WDT_START: + if (!mcxc162_wwdt.started) + { + wwdt_config_t config; + + WWDT_GetDefaultConfig(&config); + config.enableWatchdogReset = true; + config.timeoutValue = mcxc162_wwdt_ticks_per_second() * mcxc162_wwdt.timeout; + config.clockFreq_Hz = CLOCK_GetWwdtClkFreq(); + WWDT_Init(WWDT0, &config); + mcxc162_wwdt.started = RT_TRUE; + } + else + { + WWDT_Refresh(WWDT0); + } + return RT_EOK; + + case RT_DEVICE_CTRL_WDT_STOP: + return -RT_ENOSYS; + + default: + return -RT_EINVAL; + } +} + +static const struct rt_watchdog_ops mcxc162_wwdt_ops = { + .init = mcxc162_wwdt_init, + .control = mcxc162_wwdt_control, +}; + +int rt_hw_wdt_init(void) +{ + mcxc162_wwdt.watchdog.ops = &mcxc162_wwdt_ops; + + if ((CMC->SRS & CMC_SRS_WWDT0_MASK) != 0U) + { + LOG_I("last reset was caused by WWDT0"); + } + + return rt_hw_watchdog_register(&mcxc162_wwdt.watchdog, "wdt", + RT_DEVICE_FLAG_DEACTIVATE, RT_NULL); +} +INIT_DEVICE_EXPORT(rt_hw_wdt_init); + +#endif /* BSP_USING_WDT */ diff --git a/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_wdt.h b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_wdt.h new file mode 100644 index 0000000000..e969e1d964 --- /dev/null +++ b/bsp/nxp/mcx/mcxc/libraries/drivers/mcxc162/drv_wdt.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_MCXC162_WDT_H__ +#define __DRV_MCXC162_WDT_H__ + +int rt_hw_wdt_init(void); + +#endif /* __DRV_MCXC162_WDT_H__ */ |