diff options
Diffstat (limited to 'bsp/apollo2/libraries/startup')
| -rw-r--r-- | bsp/apollo2/libraries/startup/SConscript | 26 | ||||
| -rw-r--r-- | bsp/apollo2/libraries/startup/arm/startup_keil.s | 359 | ||||
| -rw-r--r-- | bsp/apollo2/libraries/startup/gcc/startup_gcc.c | 316 | ||||
| -rw-r--r-- | bsp/apollo2/libraries/startup/iar/startup_iar.c | 312 |
4 files changed, 1013 insertions, 0 deletions
diff --git a/bsp/apollo2/libraries/startup/SConscript b/bsp/apollo2/libraries/startup/SConscript new file mode 100644 index 0000000000..e4758f1e2e --- /dev/null +++ b/bsp/apollo2/libraries/startup/SConscript @@ -0,0 +1,26 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +src = Split(""" + +""") + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['gcc_ride7/' + 'startup_gcc.c'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['arm/' + 'startup_keil.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['iar/' + 'startup_iar.c'] + +path = [cwd] + +CPPDEFINES = ['AM_PACKAGE_BGA', 'AM_PART_APOLLO2', 'keil'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/apollo2/libraries/startup/arm/startup_keil.s b/bsp/apollo2/libraries/startup/arm/startup_keil.s new file mode 100644 index 0000000000..9c14224cc6 --- /dev/null +++ b/bsp/apollo2/libraries/startup/arm/startup_keil.s @@ -0,0 +1,359 @@ +;****************************************************************************** +; +;! @file startup_keil.s +;! +;! @brief Definitions for Apollo2 interrupt handlers, the vector table, and the stack. +; +;****************************************************************************** + +;****************************************************************************** +; +; Copyright (c) 2017, Ambiq Micro +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +; This is part of revision 1.2.9 of the AmbiqSuite Development Package. +; +;****************************************************************************** + +;****************************************************************************** +; +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;************************************************************************ +Stack EQU 0x00001000 + +;****************************************************************************** +; +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** +; +; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and +; am_usagefault_isr does not work if am_fault_isr is defined externally. +; Therefore, we'll explicitly use am_fault_isr in the table for those vectors. +; + + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemoryManagement_Handler ; The MPU fault handler + DCD BusFault_Handler ; The bus fault handler + DCD UsageFault_Handler ; The usage fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall handler + DCD DebugMon_Handler ; Debug monitor handler + DCD 0 ; Reserved + DCD PendSV_Handler ; The PendSV handler + DCD SysTick_Handler ; The SysTick handler + + ; Peripheral Interrupts + DCD am_brownout_isr ; 0: Reserved + DCD am_watchdog_isr ; 1: Reserved + DCD am_clkgen_isr ; 2: CLKGEN + DCD am_vcomp_isr ; 3: Voltage Comparator + DCD am_ioslave_ios_isr ; 4: I/O Slave general + DCD am_ioslave_acc_isr ; 5: I/O Slave access + DCD am_iomaster0_isr ; 6: I/O Master 0 + DCD am_iomaster1_isr ; 7: I/O Master 1 + DCD am_iomaster2_isr ; 8: I/O Master 2 + DCD am_iomaster3_isr ; 9: I/O Master 3 + DCD am_iomaster4_isr ; 10: I/O Master 4 + DCD am_iomaster5_isr ; 11: I/O Master 5 + DCD am_gpio_isr ; 12: GPIO + DCD am_ctimer_isr ; 13: CTIMER + DCD am_uart0_isr ; 14: UART0 + DCD am_uart1_isr ; 15: UART1 + DCD am_adc_isr ; 16: ADC + DCD am_pdm_isr ; 17: PDM + DCD am_stimer_isr ; 18: SYSTEM TIMER + DCD am_stimer_cmpr0_isr ; 19: SYSTEM TIMER COMPARE0 + DCD am_stimer_cmpr1_isr ; 20: SYSTEM TIMER COMPARE1 + DCD am_stimer_cmpr2_isr ; 21: SYSTEM TIMER COMPARE2 + DCD am_stimer_cmpr3_isr ; 22: SYSTEM TIMER COMPARE3 + DCD am_stimer_cmpr4_isr ; 23: SYSTEM TIMER COMPARE4 + DCD am_stimer_cmpr5_isr ; 24: SYSTEM TIMER COMPARE5 + DCD am_stimer_cmpr6_isr ; 25: SYSTEM TIMER COMPARE6 + DCD am_stimer_cmpr7_isr ; 26: SYSTEM TIMER COMPARE7 + DCD am_flash_isr ; 27: FLASH + DCD am_software0_isr ; 28: SOFTWARE0 + DCD am_software1_isr ; 29: SOFTWARE1 + DCD am_software2_isr ; 30: SOFTWARE2 + DCD am_software3_isr ; 31: SOFTWARE3 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Enable the FPU. + MOVW R0, #0xED88 + MOVT R0, #0xE000 + LDR R1, [R0] + ORR R1, #0x00F00000 + STR R1, [R0] + DSB + ISB + + ; Branch to main. + LDR R0, =__main + BX R0 + + ENDP + +;****************************************************************************** +; +; Weak Exception Handlers. +; +;****************************************************************************** +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +am_default_isr PROC + + EXPORT am_brownout_isr [WEAK] + EXPORT am_watchdog_isr [WEAK] + EXPORT am_clkgen_isr [WEAK] + EXPORT am_vcomp_isr [WEAK] + EXPORT am_ioslave_ios_isr [WEAK] + EXPORT am_ioslave_acc_isr [WEAK] + EXPORT am_iomaster0_isr [WEAK] + EXPORT am_iomaster1_isr [WEAK] + EXPORT am_iomaster2_isr [WEAK] + EXPORT am_iomaster3_isr [WEAK] + EXPORT am_iomaster4_isr [WEAK] + EXPORT am_iomaster5_isr [WEAK] + EXPORT am_gpio_isr [WEAK] + EXPORT am_ctimer_isr [WEAK] + EXPORT am_uart0_isr [WEAK] + EXPORT am_uart1_isr [WEAK] + EXPORT am_adc_isr [WEAK] + EXPORT am_pdm_isr [WEAK] + EXPORT am_stimer_isr [WEAK] + EXPORT am_stimer_cmpr0_isr [WEAK] + EXPORT am_stimer_cmpr1_isr [WEAK] + EXPORT am_stimer_cmpr2_isr [WEAK] + EXPORT am_stimer_cmpr3_isr [WEAK] + EXPORT am_stimer_cmpr4_isr [WEAK] + EXPORT am_stimer_cmpr5_isr [WEAK] + EXPORT am_stimer_cmpr6_isr [WEAK] + EXPORT am_stimer_cmpr7_isr [WEAK] + EXPORT am_flash_isr [WEAK] + EXPORT am_software0_isr [WEAK] + EXPORT am_software1_isr [WEAK] + EXPORT am_software2_isr [WEAK] + EXPORT am_software3_isr [WEAK] + +am_brownout_isr +am_watchdog_isr +am_clkgen_isr +am_vcomp_isr +am_ioslave_ios_isr +am_ioslave_acc_isr +am_iomaster0_isr +am_iomaster1_isr +am_iomaster2_isr +am_iomaster3_isr +am_iomaster4_isr +am_iomaster5_isr +am_gpio_isr +am_ctimer_isr +am_uart0_isr +am_uart1_isr +am_adc_isr +am_pdm_isr +am_stimer_isr +am_stimer_cmpr0_isr +am_stimer_cmpr1_isr +am_stimer_cmpr2_isr +am_stimer_cmpr3_isr +am_stimer_cmpr4_isr +am_stimer_cmpr5_isr +am_stimer_cmpr6_isr +am_stimer_cmpr7_isr +am_flash_isr +am_software0_isr +am_software1_isr +am_software2_isr +am_software3_isr + + ; all device interrupts go here unless the weak label is over + ; ridden in the linker hard spin so the debugger will know it + ; was an unhandled interrupt request a come-from-buffer or + ; instruction trace hardware would sure be nice if you get here + B . + + ENDP + +;****************************************************************************** +; +; Align the end of the section. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Initialization of the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; User Initial Stack & Heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap PROC + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + + ENDP + + ENDIF + +;****************************************************************************** +; +; Align the end of the section. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; All Done +; +;****************************************************************************** + END + + diff --git a/bsp/apollo2/libraries/startup/gcc/startup_gcc.c b/bsp/apollo2/libraries/startup/gcc/startup_gcc.c new file mode 100644 index 0000000000..a67dff41f4 --- /dev/null +++ b/bsp/apollo2/libraries/startup/gcc/startup_gcc.c @@ -0,0 +1,316 @@ +//***************************************************************************** +// +//! @file startup_gcc.c +//! +//! @brief Definitions for interrupt handlers, the vector table, and the stack. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2017, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include <stdint.h> + +//***************************************************************************** +// +// Forward declaration of interrupt handlers. +// +//***************************************************************************** +extern void am_reset_isr(void) __attribute ((naked)); +extern void am_nmi_isr(void) __attribute ((weak)); +extern void am_fault_isr(void) __attribute ((weak)); +extern void am_mpufault_isr(void) __attribute ((weak, alias ("am_fault_isr"))); +extern void am_busfault_isr(void) __attribute ((weak, alias ("am_fault_isr"))); +extern void am_usagefault_isr(void) __attribute ((weak, alias ("am_fault_isr"))); +extern void am_svcall_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_debugmon_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_pendsv_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_systick_isr(void) __attribute ((weak, alias ("am_default_isr"))); + +extern void am_brownout_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_watchdog_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_clkgen_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_vcomp_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_ioslave_ios_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_ioslave_acc_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster0_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster1_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster2_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster3_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster4_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster5_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_gpio_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_ctimer_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_uart_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_uart1_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_adc_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_pdm_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr0_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr1_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr2_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr3_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr4_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr5_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr6_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr7_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_flash_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_software0_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_software1_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_software2_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_software3_isr(void) __attribute ((weak, alias ("am_default_isr"))); + +extern void am_default_isr(void) __attribute ((weak)); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +__attribute__ ((section(".stack"))) +static uint32_t g_pui32Stack[1024]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and +// am_usagefault_isr does not work if am_fault_isr is defined externally. +// Therefore, we'll explicitly use am_fault_isr in the table for those vectors. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_am_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)g_pui32Stack + sizeof(g_pui32Stack)), + // The initial stack pointer + am_reset_isr, // The reset handler + am_nmi_isr, // The NMI handler + am_fault_isr, // The hard fault handler + am_fault_isr, // The MPU fault handler + am_fault_isr, // The bus fault handler + am_fault_isr, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + am_svcall_isr, // SVCall handle + am_debugmon_isr, // Debug monitor handler + 0, // Reserved + am_pendsv_isr, // The PendSV handler + am_systick_isr, // The SysTick handler + + // + // Peripheral Interrupts + // + am_brownout_isr, // 0: Brownout + am_watchdog_isr, // 1: Watchdog + am_clkgen_isr, // 2: CLKGEN + am_vcomp_isr, // 3: Voltage Comparator + am_ioslave_ios_isr, // 4: I/O Slave general + am_ioslave_acc_isr, // 5: I/O Slave access + am_iomaster0_isr, // 6: I/O Master 0 + am_iomaster1_isr, // 7: I/O Master 1 + am_iomaster2_isr, // 8: I/O Master 2 + am_iomaster3_isr, // 9: I/O Master 3 + am_iomaster4_isr, // 10: I/O Master 4 + am_iomaster5_isr, // 11: I/O Master 5 + am_gpio_isr, // 12: GPIO + am_ctimer_isr, // 13: CTIMER + am_uart_isr, // 14: UART + am_uart1_isr, // 15: UART + am_adc_isr, // 16: ADC + am_pdm_isr, // 17: ADC + am_stimer_isr, // 18: SYSTEM TIMER + am_stimer_cmpr0_isr, // 19: SYSTEM TIMER COMPARE0 + am_stimer_cmpr1_isr, // 20: SYSTEM TIMER COMPARE1 + am_stimer_cmpr2_isr, // 21: SYSTEM TIMER COMPARE2 + am_stimer_cmpr3_isr, // 22: SYSTEM TIMER COMPARE3 + am_stimer_cmpr4_isr, // 23: SYSTEM TIMER COMPARE4 + am_stimer_cmpr5_isr, // 24: SYSTEM TIMER COMPARE5 + am_stimer_cmpr6_isr, // 25: SYSTEM TIMER COMPARE6 + am_stimer_cmpr7_isr, // 26: SYSTEM TIMER COMPARE7 + am_flash_isr, // 27: FLASH + am_software0_isr, // 28: SOFTWARE0 + am_software1_isr, // 29: SOFTWARE1 + am_software2_isr, // 30: SOFTWARE2 + am_software3_isr // 31: SOFTWARE3 +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern uint32_t _etext; +extern uint32_t _sdata; +extern uint32_t _edata; +extern uint32_t _sbss; +extern uint32_t _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. +// +//***************************************************************************** +#if defined(__GNUC_STDC_INLINE__) +void +am_reset_isr(void) +{ + // + // Set the vector table pointer. + // + __asm(" ldr r0, =0xE000ED08\n" + " ldr r1, =g_am_pfnVectors\n" + " str r1, [r0]"); + + // + // Set the stack pointer. + // + __asm(" ldr sp, [r1]"); +#ifndef NOFPU + // + // Enable the FPU. + // + __asm("ldr r0, =0xE000ED88\n" + "ldr r1,[r0]\n" + "orr r1,#(0xF << 20)\n" + "str r1,[r0]\n" + "dsb\n" + "isb\n"); +#endif + // + // Copy the data segment initializers from flash to SRAM. + // + __asm(" ldr r0, =_init_data\n" + " ldr r1, =_sdata\n" + " ldr r2, =_edata\n" + "copy_loop:\n" + " ldr r3, [r0], #4\n" + " str r3, [r1], #4\n" + " cmp r1, r2\n" + " blt copy_loop\n"); + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_sbss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Call the application's entry point. + // + main(); + + // + // If main returns then execute a break point instruction + // + __asm(" bkpt "); +} +#else +#error GNU STDC inline not supported. +#endif + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +void +am_nmi_isr(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void +am_fault_isr(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void +am_default_isr(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + diff --git a/bsp/apollo2/libraries/startup/iar/startup_iar.c b/bsp/apollo2/libraries/startup/iar/startup_iar.c new file mode 100644 index 0000000000..3264300cb4 --- /dev/null +++ b/bsp/apollo2/libraries/startup/iar/startup_iar.c @@ -0,0 +1,312 @@ +//***************************************************************************** +// +//! @file startup_iar.c +//! +//! @brief Definitions for interrupt handlers, the vector table, and the stack. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2017, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include <stdint.h> + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language = extended + +//***************************************************************************** +// +// Weak function links. +// +//***************************************************************************** +#pragma weak am_mpufault_isr = am_fault_isr +#pragma weak am_busfault_isr = am_fault_isr +#pragma weak am_usagefault_isr = am_fault_isr +#pragma weak am_svcall_isr = am_default_isr +#pragma weak am_debugmon_isr = am_default_isr +#pragma weak am_pendsv_isr = am_default_isr +#pragma weak am_systick_isr = am_default_isr +#pragma weak am_brownout_isr = am_default_isr +#pragma weak am_watchdog_isr = am_default_isr +#pragma weak am_clkgen_isr = am_default_isr +#pragma weak am_vcomp_isr = am_default_isr +#pragma weak am_ioslave_ios_isr = am_default_isr +#pragma weak am_ioslave_acc_isr = am_default_isr +#pragma weak am_iomaster0_isr = am_default_isr +#pragma weak am_iomaster1_isr = am_default_isr +#pragma weak am_iomaster2_isr = am_default_isr +#pragma weak am_iomaster3_isr = am_default_isr +#pragma weak am_iomaster4_isr = am_default_isr +#pragma weak am_iomaster5_isr = am_default_isr +#pragma weak am_gpio_isr = am_default_isr +#pragma weak am_ctimer_isr = am_default_isr +#pragma weak am_uart_isr = am_default_isr +#pragma weak am_uart1_isr = am_default_isr +#pragma weak am_adc_isr = am_default_isr +#pragma weak am_pdm_isr = am_default_isr +#pragma weak am_stimer_isr = am_default_isr +#pragma weak am_stimer_cmpr0_isr = am_default_isr +#pragma weak am_stimer_cmpr1_isr = am_default_isr +#pragma weak am_stimer_cmpr2_isr = am_default_isr +#pragma weak am_stimer_cmpr3_isr = am_default_isr +#pragma weak am_stimer_cmpr4_isr = am_default_isr +#pragma weak am_stimer_cmpr5_isr = am_default_isr +#pragma weak am_stimer_cmpr6_isr = am_default_isr +#pragma weak am_stimer_cmpr7_isr = am_default_isr +#pragma weak am_flash_isr = am_default_isr +#pragma weak am_software0_isr = am_default_isr +#pragma weak am_software1_isr = am_default_isr +#pragma weak am_software2_isr = am_default_isr +#pragma weak am_software3_isr = am_default_isr + + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +extern __stackless void am_reset_isr(void); +extern __weak void am_nmi_isr(void); +extern __weak void am_fault_isr(void); +extern void am_mpufault_isr(void); +extern void am_busfault_isr(void); +extern void am_usagefault_isr(void); +extern void am_svcall_isr(void); +extern void am_debugmon_isr(void); +extern void am_pendsv_isr(void); +extern void am_systick_isr(void); +extern void am_brownout_isr(void); +extern void am_watchdog_isr(void); +extern void am_clkgen_isr(void); +extern void am_vcomp_isr(void); +extern void am_ioslave_ios_isr(void); +extern void am_ioslave_acc_isr(void); +extern void am_iomaster0_isr(void); +extern void am_iomaster1_isr(void); +extern void am_iomaster2_isr(void); +extern void am_iomaster3_isr(void); +extern void am_iomaster4_isr(void); +extern void am_iomaster5_isr(void); +extern void am_gpio_isr(void); +extern void am_ctimer_isr(void); +extern void am_uart_isr(void); +extern void am_uart1_isr(void); +extern void am_adc_isr(void); +extern void am_pdm_isr(void); +extern void am_stimer_isr(void); +extern void am_stimer_cmpr0_isr(void); +extern void am_stimer_cmpr1_isr(void); +extern void am_stimer_cmpr2_isr(void); +extern void am_stimer_cmpr3_isr(void); +extern void am_stimer_cmpr4_isr(void); +extern void am_stimer_cmpr5_isr(void); +extern void am_stimer_cmpr6_isr(void); +extern void am_stimer_cmpr7_isr(void); +extern void am_flash_isr(void); +extern void am_software0_isr(void); +extern void am_software1_isr(void); +extern void am_software2_isr(void); +extern void am_software3_isr(void); + +extern void am_default_isr(void); + +//***************************************************************************** +// +// The entry point for the application startup code. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[1024] @ ".noinit"; + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + uint32_t ui32Ptr; +} +uVectorEntry; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and +// am_usagefault_isr does not work if am_fault_isr is defined externally. +// Therefore, we'll explicitly use am_fault_isr in the table for those vectors. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) }, + // The initial stack pointer + am_reset_isr, // The reset handler + am_nmi_isr, // The NMI handler + am_fault_isr, // The hard fault handler + am_fault_isr, // The MPU fault handler + am_fault_isr, // The bus fault handler + am_fault_isr, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + am_svcall_isr, // SVCall handle + am_debugmon_isr, // Debug monitor handler + 0, // Reserved + am_pendsv_isr, // The PendSV handler + am_systick_isr, // The SysTick handler + + // + // Peripheral Interrupts + // + am_brownout_isr, // 0: Brownout + am_watchdog_isr, // 1: Watchdog + am_clkgen_isr, // 2: CLKGEN + am_vcomp_isr, // 3: Voltage Comparator + am_ioslave_ios_isr, // 4: I/O Slave general + am_ioslave_acc_isr, // 5: I/O Slave access + am_iomaster0_isr, // 6: I/O Master 0 + am_iomaster1_isr, // 7: I/O Master 1 + am_iomaster2_isr, // 8: I/O Master 2 + am_iomaster3_isr, // 9: I/O Master 3 + am_iomaster4_isr, // 10: I/O Master 4 + am_iomaster5_isr, // 11: I/O Master 5 + am_gpio_isr, // 12: GPIO + am_ctimer_isr, // 13: CTIMER + am_uart_isr, // 14: UART0 + am_uart1_isr, // 15: UART1 + am_adc_isr, // 16: ADC + am_pdm_isr, // 17: PDM + am_stimer_isr, // 18: STIMER + am_stimer_cmpr0_isr, // 19: STIMER COMPARE0 + am_stimer_cmpr1_isr, // 20: STIMER COMPARE1 + am_stimer_cmpr2_isr, // 21: STIMER COMPARE2 + am_stimer_cmpr3_isr, // 22: STIMER COMPARE3 + am_stimer_cmpr4_isr, // 23: STIMER COMPARE4 + am_stimer_cmpr5_isr, // 24: STIMER COMPARE5 + am_stimer_cmpr6_isr, // 25: STIMER COMPARE6 + am_stimer_cmpr7_isr, // 26: STIMER COMPARE7 + am_flash_isr, // 27: FLASH + am_software0_isr, // 28: SOFTWARE0 + am_software1_isr, // 29: SOFTWARE1 + am_software2_isr, // 30: SOFTWARE2 + am_software3_isr // 31: SOFTWARE3 +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. +// +//***************************************************************************** +void +am_reset_isr(void) +{ + // + // Call the application's entry point. + // + __iar_program_start(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +__weak void +am_nmi_isr(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +__weak void +am_fault_isr(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +am_default_isr(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} |