summaryrefslogtreecommitdiff
path: root/bsp/at91sam9260/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'bsp/at91sam9260/drivers')
-rw-r--r--bsp/at91sam9260/drivers/at91_i2c_gpio.c124
-rw-r--r--bsp/at91sam9260/drivers/at91_mci.c1268
-rw-r--r--bsp/at91sam9260/drivers/at91_mci.h168
-rw-r--r--bsp/at91sam9260/drivers/board.c244
-rw-r--r--bsp/at91sam9260/drivers/led.c84
-rw-r--r--bsp/at91sam9260/drivers/macb.c1240
-rw-r--r--bsp/at91sam9260/drivers/macb.h554
-rw-r--r--bsp/at91sam9260/drivers/mii.h20
-rw-r--r--bsp/at91sam9260/drivers/usart.c372
9 files changed, 2037 insertions, 2037 deletions
diff --git a/bsp/at91sam9260/drivers/at91_i2c_gpio.c b/bsp/at91sam9260/drivers/at91_i2c_gpio.c
index fb4c0ccfaf..d863ffed88 100644
--- a/bsp/at91sam9260/drivers/at91_i2c_gpio.c
+++ b/bsp/at91sam9260/drivers/at91_i2c_gpio.c
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
- * Date Author Notes
- * 2012-04-25 weety first version
+ * Date Author Notes
+ * 2012-04-25 weety first version
*/
#include <rtdevice.h>
@@ -15,101 +15,101 @@
static void at91_i2c_gpio_init()
{
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock
- at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23));
- at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23));
- at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23));
- at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24));
- at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24));
- at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24));
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock
+ at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23));
+ at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23));
+ at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23));
+ at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24));
+ at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24));
+ at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24));
- at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23));
- at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24));
+ at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23));
+ at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24));
- at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
- at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
+ at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
+ at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
}
static void at91_set_sda(void *data, rt_int32_t state)
{
- if (state)
- {
- at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
- }
- else
- {
- at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23));
- }
+ if (state)
+ {
+ at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
+ }
+ else
+ {
+ at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23));
+ }
}
static void at91_set_scl(void *data, rt_int32_t state)
{
- if (state)
- {
- at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
- }
- else
- {
- at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24));
- }
+ if (state)
+ {
+ at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
+ }
+ else
+ {
+ at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24));
+ }
}
static rt_int32_t at91_get_sda(void *data)
{
- return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23);
+ return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23);
}
static rt_int32_t at91_get_scl(void *data)
{
- return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24);
+ return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24);
}
static void at91_udelay (rt_uint32_t us)
{
- rt_int32_t i;
- for (; us > 0; us--)
- {
- i = 50000;
- while(i > 0)
- {
- i--;
- }
- }
+ rt_int32_t i;
+ for (; us > 0; us--)
+ {
+ i = 50000;
+ while(i > 0)
+ {
+ i--;
+ }
+ }
}
static const struct rt_i2c_bit_ops bit_ops = {
- RT_NULL,
- at91_set_sda,
- at91_set_scl,
- at91_get_sda,
- at91_get_scl,
-
- at91_udelay,
+ RT_NULL,
+ at91_set_sda,
+ at91_set_scl,
+ at91_get_sda,
+ at91_get_scl,
- 5,
- 100
+ at91_udelay,
+
+ 5,
+ 100
};
int at91_i2c_init(void)
{
- struct rt_i2c_bus_device *bus;
+ struct rt_i2c_bus_device *bus;
+
+ bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
+ if (bus == RT_NULL)
+ {
+ rt_kprintf("rt_malloc failed\n");
+ return -RT_ENOMEM;
+ }
- bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
- if (bus == RT_NULL)
- {
- rt_kprintf("rt_malloc failed\n");
- return -RT_ENOMEM;
- }
-
- rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
+ rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
- bus->priv = (void *)&bit_ops;
+ bus->priv = (void *)&bit_ops;
- at91_i2c_gpio_init();
+ at91_i2c_gpio_init();
- rt_i2c_bit_add_bus(bus, "i2c0");
+ rt_i2c_bit_add_bus(bus, "i2c0");
- return 0;
+ return 0;
}
INIT_DEVICE_EXPORT(at91_i2c_init);
diff --git a/bsp/at91sam9260/drivers/at91_mci.c b/bsp/at91sam9260/drivers/at91_mci.c
index dfa5d5172e..92f7abdfec 100644
--- a/bsp/at91sam9260/drivers/at91_mci.c
+++ b/bsp/at91sam9260/drivers/at91_mci.c
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
- * Date Author Notes
- * 2011-07-25 weety first version
+ * Date Author Notes
+ * 2011-07-25 weety first version
*/
#include <rtthread.h>
@@ -23,32 +23,32 @@
#define mci_dbg(fmt, ...)
#endif
-#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
+#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
-#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
- | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
- | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
+#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
+ | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
+ | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
-#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg))
-#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg))
+#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg))
+#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg))
-#define REQ_ST_INIT (1U << 0)
-#define REQ_ST_CMD (1U << 1)
-#define REQ_ST_STOP (1U << 2)
+#define REQ_ST_INIT (1U << 0)
+#define REQ_ST_CMD (1U << 1)
+#define REQ_ST_STOP (1U << 2)
struct at91_mci {
- struct rt_mmcsd_host *host;
- struct rt_mmcsd_req *req;
- struct rt_mmcsd_cmd *cmd;
- struct rt_timer timer;
- //struct rt_semaphore sem_ack;
- rt_uint32_t *buf;
- rt_uint32_t current_status;
+ struct rt_mmcsd_host *host;
+ struct rt_mmcsd_req *req;
+ struct rt_mmcsd_cmd *cmd;
+ struct rt_timer timer;
+ //struct rt_semaphore sem_ack;
+ rt_uint32_t *buf;
+ rt_uint32_t current_status;
};
/*
@@ -56,36 +56,36 @@ struct at91_mci {
*/
static void at91_reset_host()
{
- rt_uint32_t mr;
- rt_uint32_t sdcr;
- rt_uint32_t dtor;
- rt_uint32_t imr;
- rt_uint32_t level;
+ rt_uint32_t mr;
+ rt_uint32_t sdcr;
+ rt_uint32_t dtor;
+ rt_uint32_t imr;
+ rt_uint32_t level;
- level = rt_hw_interrupt_disable();
+ level = rt_hw_interrupt_disable();
- imr = at91_mci_read(AT91_MCI_IMR);
+ imr = at91_mci_read(AT91_MCI_IMR);
- at91_mci_write(AT91_MCI_IDR, 0xffffffff);
+ at91_mci_write(AT91_MCI_IDR, 0xffffffff);
- /* save current state */
- mr = at91_mci_read(AT91_MCI_MR) & 0x7fff;
- sdcr = at91_mci_read(AT91_MCI_SDCR);
- dtor = at91_mci_read(AT91_MCI_DTOR);
+ /* save current state */
+ mr = at91_mci_read(AT91_MCI_MR) & 0x7fff;
+ sdcr = at91_mci_read(AT91_MCI_SDCR);
+ dtor = at91_mci_read(AT91_MCI_DTOR);
- /* reset the controller */
- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
+ /* reset the controller */
+ at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
- /* restore state */
- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
- at91_mci_write(AT91_MCI_MR, mr);
- at91_mci_write(AT91_MCI_SDCR, sdcr);
- at91_mci_write(AT91_MCI_DTOR, dtor);
- at91_mci_write(AT91_MCI_IER, imr);
+ /* restore state */
+ at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
+ at91_mci_write(AT91_MCI_MR, mr);
+ at91_mci_write(AT91_MCI_SDCR, sdcr);
+ at91_mci_write(AT91_MCI_DTOR, dtor);
+ at91_mci_write(AT91_MCI_IER, imr);
- /* make sure sdio interrupts will fire */
- at91_mci_read(AT91_MCI_SR);
- rt_hw_interrupt_enable(level);
+ /* make sure sdio interrupts will fire */
+ at91_mci_read(AT91_MCI_SR);
+ rt_hw_interrupt_enable(level);
}
@@ -95,19 +95,19 @@ static void at91_reset_host()
*/
static void at91_mci_enable()
{
- rt_uint32_t mr;
+ rt_uint32_t mr;
- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
- at91_mci_write(AT91_MCI_IDR, 0xffffffff);
- at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
- mr = AT91_MCI_PDCMODE | 0x34a;
+ at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
+ at91_mci_write(AT91_MCI_IDR, 0xffffffff);
+ at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
+ mr = AT91_MCI_PDCMODE | 0x34a;
- mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
+ mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
- at91_mci_write(AT91_MCI_MR, mr);
+ at91_mci_write(AT91_MCI_MR, mr);
- /* use Slot A or B (only one at same time) */
- at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */
+ /* use Slot A or B (only one at same time) */
+ at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */
}
/*
@@ -115,39 +115,39 @@ static void at91_mci_enable()
*/
static void at91_mci_disable()
{
- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
+ at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
}
static void at91_timeout_timer(void *data)
{
- struct at91_mci *mci;
+ struct at91_mci *mci;
- mci = (struct at91_mci *)data;
+ mci = (struct at91_mci *)data;
- if (mci->req)
- {
- rt_kprintf("Timeout waiting end of packet\n");
+ if (mci->req)
+ {
+ rt_kprintf("Timeout waiting end of packet\n");
- if (mci->current_status == REQ_ST_CMD)
- {
- if (mci->req->cmd && mci->req->data)
- {
- mci->req->data->err = -RT_ETIMEOUT;
- }
- else
- {
- if (mci->req->cmd)
- mci->req->cmd->err = -RT_ETIMEOUT;
- }
- }
- else if (mci->current_status == REQ_ST_STOP)
- {
- mci->req->stop->err = -RT_ETIMEOUT;
- }
+ if (mci->current_status == REQ_ST_CMD)
+ {
+ if (mci->req->cmd && mci->req->data)
+ {
+ mci->req->data->err = -RT_ETIMEOUT;
+ }
+ else
+ {
+ if (mci->req->cmd)
+ mci->req->cmd->err = -RT_ETIMEOUT;
+ }
+ }
+ else if (mci->current_status == REQ_ST_STOP)
+ {
+ mci->req->stop->err = -RT_ETIMEOUT;
+ }
- at91_reset_host();
- mmcsd_req_complete(mci->host);
- }
+ at91_reset_host();
+ mmcsd_req_complete(mci->host);
+ }
}
/*
@@ -155,62 +155,62 @@ static void at91_timeout_timer(void *data)
*/
static void at91_mci_init_dma_read(struct at91_mci *mci)
{
- rt_uint8_t i;
- struct rt_mmcsd_cmd *cmd;
- struct rt_mmcsd_data *data;
- rt_uint32_t length;
+ rt_uint8_t i;
+ struct rt_mmcsd_cmd *cmd;
+ struct rt_mmcsd_data *data;
+ rt_uint32_t length;
- mci_dbg("pre dma read\n");
+ mci_dbg("pre dma read\n");
- cmd = mci->cmd;
- if (!cmd)
- {
- mci_dbg("no command\n");
- return;
- }
+ cmd = mci->cmd;
+ if (!cmd)
+ {
+ mci_dbg("no command\n");
+ return;
+ }
- data = cmd->data;
- if (!data)
- {
- mci_dbg("no data\n");
- return;
- }
+ data = cmd->data;
+ if (!data)
+ {
+ mci_dbg("no data\n");
+ return;
+ }
- for (i = 0; i < 1; i++)
- {
- /* Check to see if this needs filling */
- if (i == 0)
- {
- if (at91_mci_read(AT91_PDC_RCR) != 0)
- {
- mci_dbg("Transfer active in current\n");
- continue;
- }
- }
- else {
- if (at91_mci_read(AT91_PDC_RNCR) != 0)
- {
- mci_dbg("Transfer active in next\n");
- continue;
- }
- }
+ for (i = 0; i < 1; i++)
+ {
+ /* Check to see if this needs filling */
+ if (i == 0)
+ {
+ if (at91_mci_read(AT91_PDC_RCR) != 0)
+ {
+ mci_dbg("Transfer active in current\n");
+ continue;
+ }
+ }
+ else {
+ if (at91_mci_read(AT91_PDC_RNCR) != 0)
+ {
+ mci_dbg("Transfer active in next\n");
+ continue;
+ }
+ }
- length = data->blksize * data->blks;
- mci_dbg("dma address = %08X, length = %d\n", data->buf, length);
+ length = data->blksize * data->blks;
+ mci_dbg("dma address = %08X, length = %d\n", data->buf, length);
- if (i == 0)
- {
- at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf));
- at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4);
- }
- else
- {
- at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf));
- at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4);
- }
- }
+ if (i == 0)
+ {
+ at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf));
+ at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4);
+ }
+ else
+ {
+ at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf));
+ at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4);
+ }
+ }
- mci_dbg("pre dma read done\n");
+ mci_dbg("pre dma read done\n");
}
/*
@@ -218,185 +218,185 @@ static void at91_mci_init_dma_read(struct at91_mci *mci)
*/
static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd)
{
- rt_uint32_t cmdr, mr;
- rt_uint32_t block_length;
- struct rt_mmcsd_data *data = cmd->data;
- struct rt_mmcsd_host *host = mci->host;
+ rt_uint32_t cmdr, mr;
+ rt_uint32_t block_length;
+ struct rt_mmcsd_data *data = cmd->data;
+ struct rt_mmcsd_host *host = mci->host;
- rt_uint32_t blocks;
- rt_uint32_t ier = 0;
- rt_uint32_t length;
+ rt_uint32_t blocks;
+ rt_uint32_t ier = 0;
+ rt_uint32_t length;
- mci->cmd = cmd;
+ mci->cmd = cmd;
- /* Needed for leaving busy state before CMD1 */
- if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1))
- {
- mci_dbg("Clearing timeout\n");
- at91_mci_write(AT91_MCI_ARGR, 0);
- at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
- while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
- {
- /* spin */
- mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
- }
- }
+ /* Needed for leaving busy state before CMD1 */
+ if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1))
+ {
+ mci_dbg("Clearing timeout\n");
+ at91_mci_write(AT91_MCI_ARGR, 0);
+ at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
+ while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
+ {
+ /* spin */
+ mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
+ }
+ }
- cmdr = cmd->cmd_code;
+ cmdr = cmd->cmd_code;
- if (resp_type(cmd) == RESP_NONE)
- cmdr |= AT91_MCI_RSPTYP_NONE;
- else
- {
- /* if a response is expected then allow maximum response latancy */
- cmdr |= AT91_MCI_MAXLAT;
- /* set 136 bit response for R2, 48 bit response otherwise */
- if (resp_type(cmd) == RESP_R2)
- cmdr |= AT91_MCI_RSPTYP_136;
- else
- cmdr |= AT91_MCI_RSPTYP_48;
- }
+ if (resp_type(cmd) == RESP_NONE)
+ cmdr |= AT91_MCI_RSPTYP_NONE;
+ else
+ {
+ /* if a response is expected then allow maximum response latancy */
+ cmdr |= AT91_MCI_MAXLAT;
+ /* set 136 bit response for R2, 48 bit response otherwise */
+ if (resp_type(cmd) == RESP_R2)
+ cmdr |= AT91_MCI_RSPTYP_136;
+ else
+ cmdr |= AT91_MCI_RSPTYP_48;
+ }
- if (data)
- {
+ if (data)
+ {
- block_length = data->blksize;
- blocks = data->blks;
+ block_length = data->blksize;
+ blocks = data->blks;
- /* always set data start - also set direction flag for read */
- if (data->flags & DATA_DIR_READ)
- cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
- else if (data->flags & DATA_DIR_WRITE)
- cmdr |= AT91_MCI_TRCMD_START;
+ /* always set data start - also set direction flag for read */
+ if (data->flags & DATA_DIR_READ)
+ cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
+ else if (data->flags & DATA_DIR_WRITE)
+ cmdr |= AT91_MCI_TRCMD_START;
- if (data->flags & DATA_STREAM)
- cmdr |= AT91_MCI_TRTYP_STREAM;
- if (data->blks > 1)
- cmdr |= AT91_MCI_TRTYP_MULTIPLE;
- }
- else
- {
- block_length = 0;
- blocks = 0;
- }
+ if (data->flags & DATA_STREAM)
+ cmdr |= AT91_MCI_TRTYP_STREAM;
+ if (data->blks > 1)
+ cmdr |= AT91_MCI_TRTYP_MULTIPLE;
+ }
+ else
+ {
+ block_length = 0;
+ blocks = 0;
+ }
- /*if (cmd->cmd_code == GO_IDLE_STATE)
- {
- cmdr |= AT91_MCI_SPCMD_INIT;
- }*/
+ /*if (cmd->cmd_code == GO_IDLE_STATE)
+ {
+ cmdr |= AT91_MCI_SPCMD_INIT;
+ }*/
- if (cmd->cmd_code == STOP_TRANSMISSION)
- cmdr |= AT91_MCI_TRCMD_STOP;
+ if (cmd->cmd_code == STOP_TRANSMISSION)
+ cmdr |= AT91_MCI_TRCMD_STOP;
- if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN)
- cmdr |= AT91_MCI_OPDCMD;
+ if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN)
+ cmdr |= AT91_MCI_OPDCMD;
- /*
- * Set the arguments and send the command
- */
- mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
- cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
+ /*
+ * Set the arguments and send the command
+ */
+ mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
+ cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
- if (!data)
- {
- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
- at91_mci_write(AT91_PDC_RPR, 0);
- at91_mci_write(AT91_PDC_RCR, 0);
- at91_mci_write(AT91_PDC_RNPR, 0);
- at91_mci_write(AT91_PDC_RNCR, 0);
- at91_mci_write(AT91_PDC_TPR, 0);
- at91_mci_write(AT91_PDC_TCR, 0);
- at91_mci_write(AT91_PDC_TNPR, 0);
- at91_mci_write(AT91_PDC_TNCR, 0);
- ier = AT91_MCI_CMDRDY;
- }
- else
- {
- /* zero block length and PDC mode */
- mr = at91_mci_read(AT91_MCI_MR) & 0x5fff;
- mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0;
- mr |= (block_length << 16);
- mr |= AT91_MCI_PDCMODE;
- at91_mci_write(AT91_MCI_MR, mr);
+ if (!data)
+ {
+ at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
+ at91_mci_write(AT91_PDC_RPR, 0);
+ at91_mci_write(AT91_PDC_RCR, 0);
+ at91_mci_write(AT91_PDC_RNPR, 0);
+ at91_mci_write(AT91_PDC_RNCR, 0);
+ at91_mci_write(AT91_PDC_TPR, 0);
+ at91_mci_write(AT91_PDC_TCR, 0);
+ at91_mci_write(AT91_PDC_TNPR, 0);
+ at91_mci_write(AT91_PDC_TNCR, 0);
+ ier = AT91_MCI_CMDRDY;
+ }
+ else
+ {
+ /* zero block length and PDC mode */
+ mr = at91_mci_read(AT91_MCI_MR) & 0x5fff;
+ mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0;
+ mr |= (block_length << 16);
+ mr |= AT91_MCI_PDCMODE;
+ at91_mci_write(AT91_MCI_MR, mr);
- at91_mci_write(AT91_MCI_BLKR,
- AT91_MCI_BLKR_BCNT(blocks) |
- AT91_MCI_BLKR_BLKLEN(block_length));
+ at91_mci_write(AT91_MCI_BLKR,
+ AT91_MCI_BLKR_BCNT(blocks) |
+ AT91_MCI_BLKR_BLKLEN(block_length));
- /*
- * Disable the PDC controller
- */
- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
+ /*
+ * Disable the PDC controller
+ */
+ at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
- if (cmdr & AT91_MCI_TRCMD_START)
- {
- if (cmdr & AT91_MCI_TRDIR)
- {
- /*
- * Handle a read
- */
+ if (cmdr & AT91_MCI_TRCMD_START)
+ {
+ if (cmdr & AT91_MCI_TRDIR)
+ {
+ /*
+ * Handle a read
+ */
- mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
- at91_mci_init_dma_read(mci);
- ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
- }
- else
- {
- /*
- * Handle a write
- */
- length = block_length * blocks;
- /*
- * at91mci MCI1 rev2xx Data Write Operation and
- * number of bytes erratum
- */
- if (length < 12)
- {
- length = 12;
- mci->buf = rt_malloc(length);
- if (!mci->buf)
- {
- rt_kprintf("rt alloc tx buffer failed\n");
- cmd->err = -RT_ENOMEM;
- mmcsd_req_complete(mci->host);
- return;
- }
- rt_memset(mci->buf, 0, 12);
- rt_memcpy(mci->buf, data->buf, length);
- mmu_clean_dcache((rt_uint32_t)mci->buf, length);
- at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf));
- at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
- length : length / 4);
- }
- else
- {
- mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
- at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf));
- at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
- length : length / 4);
- }
- mci_dbg("Transmitting %d bytes\n", length);
- ier = AT91_MCI_CMDRDY;
- }
- }
- }
+ mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
+ at91_mci_init_dma_read(mci);
+ ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
+ }
+ else
+ {
+ /*
+ * Handle a write
+ */
+ length = block_length * blocks;
+ /*
+ * at91mci MCI1 rev2xx Data Write Operation and
+ * number of bytes erratum
+ */
+ if (length < 12)
+ {
+ length = 12;
+ mci->buf = rt_malloc(length);
+ if (!mci->buf)
+ {
+ rt_kprintf("rt alloc tx buffer failed\n");
+ cmd->err = -RT_ENOMEM;
+ mmcsd_req_complete(mci->host);
+ return;
+ }
+ rt_memset(mci->buf, 0, 12);
+ rt_memcpy(mci->buf, data->buf, length);
+ mmu_clean_dcache((rt_uint32_t)mci->buf, length);
+ at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf));
+ at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
+ length : length / 4);
+ }
+ else
+ {
+ mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
+ at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf));
+ at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
+ length : length / 4);
+ }
+ mci_dbg("Transmitting %d bytes\n", length);
+ ier = AT91_MCI_CMDRDY;
+ }
+ }
+ }
- /*
- * Send the command and then enable the PDC - not the other way round as
- * the data sheet says
- */
+ /*
+ * Send the command and then enable the PDC - not the other way round as
+ * the data sheet says
+ */
- at91_mci_write(AT91_MCI_ARGR, cmd->arg);
- at91_mci_write(AT91_MCI_CMDR, cmdr);
+ at91_mci_write(AT91_MCI_ARGR, cmd->arg);
+ at91_mci_write(AT91_MCI_CMDR, cmdr);
- if (cmdr & AT91_MCI_TRCMD_START)
- {
- if (cmdr & AT91_MCI_TRDIR)
- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
- }
+ if (cmdr & AT91_MCI_TRCMD_START)
+ {
+ if (cmdr & AT91_MCI_TRDIR)
+ at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
+ }
- /* Enable selected interrupts */
- at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier);
+ /* Enable selected interrupts */
+ at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier);
}
/*
@@ -404,25 +404,25 @@ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd
*/
static void at91_mci_process_next(struct at91_mci *mci)
{
- if (mci->current_status == REQ_ST_INIT)
- {
- mci->current_status = REQ_ST_CMD;
- at91_mci_send_command(mci, mci->req->cmd);
- }
- else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop)
- {
- mci->current_status = REQ_ST_STOP;
- at91_mci_send_command(mci, mci->req->stop);
- }
- else
- {
- rt_timer_stop(&mci->timer);
- /* the mci controller hangs after some transfers,
- * and the workaround is to reset it after each transfer.
- */
- at91_reset_host();
- mmcsd_req_complete(mci->host);
- }
+ if (mci->current_status == REQ_ST_INIT)
+ {
+ mci->current_status = REQ_ST_CMD;
+ at91_mci_send_command(mci, mci->req->cmd);
+ }
+ else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop)
+ {
+ mci->current_status = REQ_ST_STOP;
+ at91_mci_send_command(mci, mci->req->stop);
+ }
+ else
+ {
+ rt_timer_stop(&mci->timer);
+ /* the mci controller hangs after some transfers,
+ * and the workaround is to reset it after each transfer.
+ */
+ at91_reset_host();
+ mmcsd_req_complete(mci->host);
+ }
}
/*
@@ -430,15 +430,15 @@ static void at91_mci_process_next(struct at91_mci *mci)
*/
static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
- rt_uint32_t timeout = RT_TICK_PER_SECOND;
- struct at91_mci *mci = host->private_data;
- mci->req = req;
- mci->current_status = REQ_ST_INIT;
+ rt_uint32_t timeout = RT_TICK_PER_SECOND;
+ struct at91_mci *mci = host->private_data;
+ mci->req = req;
+ mci->current_status = REQ_ST_INIT;
- rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout);
- rt_timer_start(&mci->timer);
+ rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout);
+ rt_timer_start(&mci->timer);
- at91_mci_process_next(mci);
+ at91_mci_process_next(mci);
}
/*
@@ -446,29 +446,29 @@ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *re
*/
static void at91_mci_handle_transmitted(struct at91_mci *mci)
{
- struct rt_mmcsd_cmd *cmd;
- struct rt_mmcsd_data *data;
+ struct rt_mmcsd_cmd *cmd;
+ struct rt_mmcsd_data *data;
- mci_dbg("Handling the transmit\n");
+ mci_dbg("Handling the transmit\n");
- /* Disable the transfer */
- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
+ /* Disable the transfer */
+ at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
- /* Now wait for cmd ready */
- at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
+ /* Now wait for cmd ready */
+ at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
- cmd = mci->cmd;
- if (!cmd) return;
+ cmd = mci->cmd;
+ if (!cmd) return;
- data = cmd->data;
- if (!data) return;
+ data = cmd->data;
+ if (!data) return;
- if (data->blks > 1)
- {
- mci_dbg("multiple write : wait for BLKE...\n");
- at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE);
- } else
- at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
+ if (data->blks > 1)
+ {
+ mci_dbg("multiple write : wait for BLKE...\n");
+ at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE);
+ } else
+ at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
}
@@ -477,54 +477,54 @@ static void at91_mci_handle_transmitted(struct at91_mci *mci)
*/
static void at91_mci_post_dma_read(struct at91_mci *mci)
{
- struct rt_mmcsd_cmd *cmd;
- struct rt_mmcsd_data *data;
+ struct rt_mmcsd_cmd *cmd;
+ struct rt_mmcsd_data *data;
- mci_dbg("post dma read\n");
+ mci_dbg("post dma read\n");
- cmd = mci->cmd;
- if (!cmd)
- {
- mci_dbg("no command\n");
- return;
- }
+ cmd = mci->cmd;
+ if (!cmd)
+ {
+ mci_dbg("no command\n");
+ return;
+ }
- data = cmd->data;
- if (!data)
- {
- mci_dbg("no data\n");
- return;
- }
+ data = cmd->data;
+ if (!data)
+ {
+ mci_dbg("no data\n");
+ return;
+ }
- at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX);
- at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
+ at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX);
+ at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
- mci_dbg("post dma read done\n");
+ mci_dbg("post dma read done\n");
}
/*Handle after command sent ready*/
static int at91_mci_handle_cmdrdy(struct at91_mci *mci)
{
- if (!mci->cmd)
- return 1;
- else if (!mci->cmd->data)
- {
- if (mci->current_status == REQ_ST_STOP)
- {
- /*After multi block write, we must wait for NOTBUSY*/
- at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
- }
- else return 1;
- }
- else if (mci->cmd->data->flags & DATA_DIR_WRITE)
- {
- /*After sendding multi-block-write command, start DMA transfer*/
- at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
- }
+ if (!mci->cmd)
+ return 1;
+ else if (!mci->cmd->data)
+ {
+ if (mci->current_status == REQ_ST_STOP)
+ {
+ /*After multi block write, we must wait for NOTBUSY*/
+ at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
+ }
+ else return 1;
+ }
+ else if (mci->cmd->data->flags & DATA_DIR_WRITE)
+ {
+ /*After sendding multi-block-write command, start DMA transfer*/
+ at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
+ at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
+ }
- /* command not completed, have to wait */
- return 0;
+ /* command not completed, have to wait */
+ return 0;
}
/*
@@ -532,64 +532,64 @@ static int at91_mci_handle_cmdrdy(struct at91_mci *mci)
*/
static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status)
{
- struct rt_mmcsd_cmd *cmd = mci->cmd;
- struct rt_mmcsd_data *data = cmd->data;
+ struct rt_mmcsd_cmd *cmd = mci->cmd;
+ struct rt_mmcsd_data *data = cmd->data;
- at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
+ at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
- cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
- cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
- cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
- cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
+ cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
+ cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
+ cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
+ cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
- if (mci->buf)
- {
- //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks);
- rt_free(mci->buf);
- mci->buf = RT_NULL;
- }
+ if (mci->buf)
+ {
+ //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks);
+ rt_free(mci->buf);
+ mci->buf = RT_NULL;
+ }
- mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n",
- status, at91_mci_read(AT91_MCI_SR),
- cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+ mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n",
+ status, at91_mci_read(AT91_MCI_SR),
+ cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
- if (status & AT91_MCI_ERRORS)
- {
- if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4)))
- {
- cmd->err = 0;
- }
- else
- {
- if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE))
- {
- if (data)
- {
- if (status & AT91_MCI_DTOE)
- data->err = -RT_ETIMEOUT;
- else if (status & AT91_MCI_DCRCE)
- data->err = -RT_ERROR;
- }
- }
- else
- {
- if (status & AT91_MCI_RTOE)
- cmd->err = -RT_ETIMEOUT;
- else if (status & AT91_MCI_RCRCE)
- cmd->err = -RT_ERROR;
- else
- cmd->err = -RT_ERROR;
- }
+ if (status & AT91_MCI_ERRORS)
+ {
+ if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4)))
+ {
+ cmd->err = 0;
+ }
+ else
+ {
+ if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE))
+ {
+ if (data)
+ {
+ if (status & AT91_MCI_DTOE)
+ data->err = -RT_ETIMEOUT;
+ else if (status & AT91_MCI_DCRCE)
+ data->err = -RT_ERROR;
+ }
+ }
+ else
+ {
+ if (status & AT91_MCI_RTOE)
+ cmd->err = -RT_ETIMEOUT;
+ else if (status & AT91_MCI_RCRCE)
+ cmd->err = -RT_ERROR;
+ else
+ cmd->err = -RT_ERROR;
+ }
- rt_kprintf("error detected and set to %d/%d (cmd = %d)\n",
- cmd->err, data ? data->err : 0,
- cmd->cmd_code);
- }
- }
- else
- cmd->err = 0;
+ rt_kprintf("error detected and set to %d/%d (cmd = %d)\n",
+ cmd->err, data ? data->err : 0,
+ cmd->cmd_code);
+ }
+ }
+ else
+ cmd->err = 0;
- at91_mci_process_next(mci);
+ at91_mci_process_next(mci);
}
/*
@@ -597,120 +597,120 @@ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status)
*/
static void at91_mci_irq(int irq, void *param)
{
- struct at91_mci *mci = (struct at91_mci *)param;
- rt_int32_t completed = 0;
- rt_uint32_t int_status, int_mask;
+ struct at91_mci *mci = (struct at91_mci *)param;
+ rt_int32_t completed = 0;
+ rt_uint32_t int_status, int_mask;
- int_status = at91_mci_read(AT91_MCI_SR);
- int_mask = at91_mci_read(AT91_MCI_IMR);
+ int_status = at91_mci_read(AT91_MCI_SR);
+ int_mask = at91_mci_read(AT91_MCI_IMR);
- mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
- int_status & int_mask);
+ mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
+ int_status & int_mask);
- int_status = int_status & int_mask;
+ int_status = int_status & int_mask;
- if (int_status & AT91_MCI_ERRORS)
- {
- completed = 1;
+ if (int_status & AT91_MCI_ERRORS)
+ {
+ completed = 1;
- if (int_status & AT91_MCI_UNRE)
- mci_dbg("MMC: Underrun error\n");
- if (int_status & AT91_MCI_OVRE)
- mci_dbg("MMC: Overrun error\n");
- if (int_status & AT91_MCI_DTOE)
- mci_dbg("MMC: Data timeout\n");
- if (int_status & AT91_MCI_DCRCE)
- mci_dbg("MMC: CRC error in data\n");
- if (int_status & AT91_MCI_RTOE)
- mci_dbg("MMC: Response timeout\n");
- if (int_status & AT91_MCI_RENDE)
- mci_dbg("MMC: Response end bit error\n");
- if (int_status & AT91_MCI_RCRCE)
- mci_dbg("MMC: Response CRC error\n");
- if (int_status & AT91_MCI_RDIRE)
- mci_dbg("MMC: Response direction error\n");
- if (int_status & AT91_MCI_RINDE)
- mci_dbg("MMC: Response index error\n");
- }
- else
- {
- /* Only continue processing if no errors */
+ if (int_status & AT91_MCI_UNRE)
+ mci_dbg("MMC: Underrun error\n");
+ if (int_status & AT91_MCI_OVRE)
+ mci_dbg("MMC: Overrun error\n");
+ if (int_status & AT91_MCI_DTOE)
+ mci_dbg("MMC: Data timeout\n");
+ if (int_status & AT91_MCI_DCRCE)
+ mci_dbg("MMC: CRC error in data\n");
+ if (int_status & AT91_MCI_RTOE)
+ mci_dbg("MMC: Response timeout\n");
+ if (int_status & AT91_MCI_RENDE)
+ mci_dbg("MMC: Response end bit error\n");
+ if (int_status & AT91_MCI_RCRCE)
+ mci_dbg("MMC: Response CRC error\n");
+ if (int_status & AT91_MCI_RDIRE)
+ mci_dbg("MMC: Response direction error\n");
+ if (int_status & AT91_MCI_RINDE)
+ mci_dbg("MMC: Response index error\n");
+ }
+ else
+ {
+ /* Only continue processing if no errors */
- if (int_status & AT91_MCI_TXBUFE)
- {
- mci_dbg("TX buffer empty\n");
- at91_mci_handle_transmitted(mci);
- }
+ if (int_status & AT91_MCI_TXBUFE)
+ {
+ mci_dbg("TX buffer empty\n");
+ at91_mci_handle_transmitted(mci);
+ }
- if (int_status & AT91_MCI_ENDRX)
- {
- mci_dbg("ENDRX\n");
- at91_mci_post_dma_read(mci);
- }
+ if (int_status & AT91_MCI_ENDRX)
+ {
+ mci_dbg("ENDRX\n");
+ at91_mci_post_dma_read(mci);
+ }
- if (int_status & AT91_MCI_RXBUFF)
- {
- mci_dbg("RX buffer full\n");
- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
- at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
- completed = 1;
- }
+ if (int_status & AT91_MCI_RXBUFF)
+ {
+ mci_dbg("RX buffer full\n");
+ at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
+ at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
+ completed = 1;
+ }
- if (int_status & AT91_MCI_ENDTX)
- mci_dbg("Transmit has ended\n");
+ if (int_status & AT91_MCI_ENDTX)
+ mci_dbg("Transmit has ended\n");
- if (int_status & AT91_MCI_NOTBUSY)
- {
- mci_dbg("Card is ready\n");
- //at91_mci_update_bytes_xfered(host);
- completed = 1;
- }
+ if (int_status & AT91_MCI_NOTBUSY)
+ {
+ mci_dbg("Card is ready\n");
+ //at91_mci_update_bytes_xfered(host);
+ completed = 1;
+ }
- if (int_status & AT91_MCI_DTIP)
- mci_dbg("Data transfer in progress\n");
+ if (int_status & AT91_MCI_DTIP)
+ mci_dbg("Data transfer in progress\n");
- if (int_status & AT91_MCI_BLKE)
- {
- mci_dbg("Block transfer has ended\n");
- if (mci->req->data && mci->req->data->blks > 1)
- {
- /* multi block write : complete multi write
- * command and send stop */
- completed = 1;
- }
- else
- {
- at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
- }
- }
+ if (int_status & AT91_MCI_BLKE)
+ {
+ mci_dbg("Block transfer has ended\n");
+ if (mci->req->data && mci->req->data->blks > 1)
+ {
+ /* multi block write : complete multi write
+ * command and send stop */
+ completed = 1;
+ }
+ else
+ {
+ at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
+ }
+ }
- /*if (int_status & AT91_MCI_SDIOIRQA)
- rt_mmcsd_signal_sdio_irq(host->mmc);*/
+ /*if (int_status & AT91_MCI_SDIOIRQA)
+ rt_mmcsd_signal_sdio_irq(host->mmc);*/
- if (int_status & AT91_MCI_SDIOIRQB)
- sdio_irq_wakeup(mci->host);
+ if (int_status & AT91_MCI_SDIOIRQB)
+ sdio_irq_wakeup(mci->host);
- if (int_status & AT91_MCI_TXRDY)
- mci_dbg("Ready to transmit\n");
+ if (int_status & AT91_MCI_TXRDY)
+ mci_dbg("Ready to transmit\n");
- if (int_status & AT91_MCI_RXRDY)
- mci_dbg("Ready to receive\n");
+ if (int_status & AT91_MCI_RXRDY)
+ mci_dbg("Ready to receive\n");
- if (int_status & AT91_MCI_CMDRDY)
- {
- mci_dbg("Command ready\n");
- completed = at91_mci_handle_cmdrdy(mci);
- }
- }
+ if (int_status & AT91_MCI_CMDRDY)
+ {
+ mci_dbg("Command ready\n");
+ completed = at91_mci_handle_cmdrdy(mci);
+ }
+ }
- if (completed)
- {
- mci_dbg("Completed command\n");
- at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
- at91_mci_completed_command(mci, int_status);
- }
- else
- at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
+ if (completed)
+ {
+ mci_dbg("Completed command\n");
+ at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
+ at91_mci_completed_command(mci, int_status);
+ }
+ else
+ at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
}
@@ -720,173 +720,173 @@ static void at91_mci_irq(int irq, void *param)
*/
static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
- rt_uint32_t clkdiv;
- //struct at91_mci *mci = host->private_data;
- rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck"));
+ rt_uint32_t clkdiv;
+ //struct at91_mci *mci = host->private_data;
+ rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck"));
- if (io_cfg->clock == 0)
- {
- /* Disable the MCI controller */
- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
- clkdiv = 0;
- }
- else
- {
- /* Enable the MCI controller */
- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
+ if (io_cfg->clock == 0)
+ {
+ /* Disable the MCI controller */
+ at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
+ clkdiv = 0;
+ }
+ else
+ {
+ /* Enable the MCI controller */
+ at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
- if ((at91_master_clock % (io_cfg->clock * 2)) == 0)
- clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1;
- else
- clkdiv = (at91_master_clock / io_cfg->clock) / 2;
+ if ((at91_master_clock % (io_cfg->clock * 2)) == 0)
+ clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1;
+ else
+ clkdiv = (at91_master_clock / io_cfg->clock) / 2;
- mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv,
- at91_master_clock / (2 * (clkdiv + 1)));
- }
- if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
- {
- mci_dbg("MMC: Setting controller bus width to 4\n");
- at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
- }
- else
- {
- mci_dbg("MMC: Setting controller bus width to 1\n");
- at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
- }
+ mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv,
+ at91_master_clock / (2 * (clkdiv + 1)));
+ }
+ if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
+ {
+ mci_dbg("MMC: Setting controller bus width to 4\n");
+ at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
+ }
+ else
+ {
+ mci_dbg("MMC: Setting controller bus width to 1\n");
+ at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
+ }
- /* Set the clock divider */
- at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
+ /* Set the clock divider */
+ at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
- /* maybe switch power to the card */
- switch (io_cfg->power_mode)
- {
- case MMCSD_POWER_OFF:
- break;
- case MMCSD_POWER_UP:
- break;
- case MMCSD_POWER_ON:
- /*at91_mci_write(AT91_MCI_ARGR, 0);
- at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD);
- mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR));
- while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
- {
-
- }
- mci_dbg("at91 mci power on\n");*/
- break;
- default:
- rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode);
- break;
- }
+ /* maybe switch power to the card */
+ switch (io_cfg->power_mode)
+ {
+ case MMCSD_POWER_OFF:
+ break;
+ case MMCSD_POWER_UP:
+ break;
+ case MMCSD_POWER_ON:
+ /*at91_mci_write(AT91_MCI_ARGR, 0);
+ at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD);
+ mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR));
+ while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
+ {
+
+ }
+ mci_dbg("at91 mci power on\n");*/
+ break;
+ default:
+ rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode);
+ break;
+ }
}
static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable)
{
- at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB);
+ at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB);
}
static const struct rt_mmcsd_host_ops ops = {
- at91_mci_request,
- at91_mci_set_iocfg,
+ at91_mci_request,
+ at91_mci_set_iocfg,
RT_NULL,
- at91_mci_enable_sdio_irq,
+ at91_mci_enable_sdio_irq,
};
void at91_mci_detect(int irq, void *param)
{
- rt_kprintf("mmcsd gpio detected\n");
+ rt_kprintf("mmcsd gpio detected\n");
}
static void mci_gpio_init()
{
#ifdef USE_SLOT_B
- at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
- at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8));
- at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
- at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8));
- at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8));
+ at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
+ at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8));
+ at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
+ at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8));
+ at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8));
- at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7));
- at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7));
- at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7));
- at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7));
+ at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7));
+ at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7));
+ at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7));
+ at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7));
#else
- at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11));
- at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
- at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
+ at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11));
+ at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
+ at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
#endif
}
int at91_mci_init(void)
{
- struct rt_mmcsd_host *host;
- struct at91_mci *mci;
+ struct rt_mmcsd_host *host;
+ struct at91_mci *mci;
+
+ host = mmcsd_alloc_host();
+ if (!host)
+ {
+ return -RT_ERROR;
+ }
- host = mmcsd_alloc_host();
- if (!host)
- {
- return -RT_ERROR;
- }
+ mci = rt_malloc(sizeof(struct at91_mci));
+ if (!mci)
+ {
+ rt_kprintf("alloc mci failed\n");
+ goto err;
+ }
- mci = rt_malloc(sizeof(struct at91_mci));
- if (!mci)
- {
- rt_kprintf("alloc mci failed\n");
- goto err;
- }
+ rt_memset(mci, 0, sizeof(struct at91_mci));
- rt_memset(mci, 0, sizeof(struct at91_mci));
+ host->ops = &ops;
+ host->freq_min = 375000;
+ host->freq_max = 25000000;
+ host->valid_ocr = VDD_32_33 | VDD_33_34;
+ host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
+ MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
+ host->max_seg_size = 65535;
+ host->max_dma_segs = 2;
+ host->max_blk_size = 512;
+ host->max_blk_count = 4096;
- host->ops = &ops;
- host->freq_min = 375000;
- host->freq_max = 25000000;
- host->valid_ocr = VDD_32_33 | VDD_33_34;
- host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
- MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
- host->max_seg_size = 65535;
- host->max_dma_segs = 2;
- host->max_blk_size = 512;
- host->max_blk_count = 4096;
+ mci->host = host;
- mci->host = host;
+ mci_gpio_init();
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock
- mci_gpio_init();
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock
-
- at91_mci_disable();
- at91_mci_enable();
+ at91_mci_disable();
+ at91_mci_enable();
- /* instal interrupt */
- rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq,
- (void *)mci, "MMC");
- rt_hw_interrupt_umask(AT91SAM9260_ID_MCI);
- rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7),
- at91_mci_detect, RT_NULL, "MMC_DETECT");
- rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7));
+ /* instal interrupt */
+ rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq,
+ (void *)mci, "MMC");
+ rt_hw_interrupt_umask(AT91SAM9260_ID_MCI);
+ rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7),
+ at91_mci_detect, RT_NULL, "MMC_DETECT");
+ rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7));
- rt_timer_init(&mci->timer, "mci_timer",
- at91_timeout_timer,
- mci,
- RT_TICK_PER_SECOND,
- RT_TIMER_FLAG_PERIODIC);
+ rt_timer_init(&mci->timer, "mci_timer",
+ at91_timeout_timer,
+ mci,
+ RT_TICK_PER_SECOND,
+ RT_TIMER_FLAG_PERIODIC);
- //rt_timer_start(&mci->timer);
+ //rt_timer_start(&mci->timer);
- //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
+ //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
- host->private_data = mci;
+ host->private_data = mci;
- mmcsd_change(host);
+ mmcsd_change(host);
- return 0;
+ return 0;
err:
- mmcsd_free_host(host);
+ mmcsd_free_host(host);
- return -RT_ENOMEM;
+ return -RT_ENOMEM;
}
INIT_DEVICE_EXPORT(at91_mci_init);
@@ -896,15 +896,15 @@ FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init);
void mci_dump(void)
{
- rt_uint32_t i;
+ rt_uint32_t i;
- rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR));
- rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR));
- rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR));
+ rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR));
+ rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR));
+ rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR));
- for (i = 0; i <= 0x4c; i += 4) {
- rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i));
- }
+ for (i = 0; i <= 0x4c; i += 4) {
+ rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i));
+ }
}
FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci);
diff --git a/bsp/at91sam9260/drivers/at91_mci.h b/bsp/at91sam9260/drivers/at91_mci.h
index f2e4a0a56c..80eb07385d 100644
--- a/bsp/at91sam9260/drivers/at91_mci.h
+++ b/bsp/at91sam9260/drivers/at91_mci.h
@@ -11,99 +11,99 @@
#ifndef __AT91_MCI_H__
#define __AT91_MCI_H__
-#define AT91_MCI_CR 0x00 /* Control Register */
-#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
-#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
-#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
-#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
-#define AT91_MCI_SWRST (1 << 7) /* Software Reset */
+#define AT91_MCI_CR 0x00 /* Control Register */
+#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
+#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
+#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
+#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
+#define AT91_MCI_SWRST (1 << 7) /* Software Reset */
-#define AT91_MCI_MR 0x04 /* Mode Register */
-#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
-#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
-#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
-#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
-#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
-#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
-#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
-#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
+#define AT91_MCI_MR 0x04 /* Mode Register */
+#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
+#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
+#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
+#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
+#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
+#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
+#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
+#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
-#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
-#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
-#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
-#define AT91_MCI_DTOMUL_1 (0 << 4)
-#define AT91_MCI_DTOMUL_16 (1 << 4)
-#define AT91_MCI_DTOMUL_128 (2 << 4)
-#define AT91_MCI_DTOMUL_256 (3 << 4)
-#define AT91_MCI_DTOMUL_1K (4 << 4)
-#define AT91_MCI_DTOMUL_4K (5 << 4)
-#define AT91_MCI_DTOMUL_64K (6 << 4)
-#define AT91_MCI_DTOMUL_1M (7 << 4)
+#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
+#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
+#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
+#define AT91_MCI_DTOMUL_1 (0 << 4)
+#define AT91_MCI_DTOMUL_16 (1 << 4)
+#define AT91_MCI_DTOMUL_128 (2 << 4)
+#define AT91_MCI_DTOMUL_256 (3 << 4)
+#define AT91_MCI_DTOMUL_1K (4 << 4)
+#define AT91_MCI_DTOMUL_4K (5 << 4)
+#define AT91_MCI_DTOMUL_64K (6 << 4)
+#define AT91_MCI_DTOMUL_1M (7 << 4)
-#define AT91_MCI_SDCR 0x0c /* SD Card Register */
-#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
-#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
+#define AT91_MCI_SDCR 0x0c /* SD Card Register */
+#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
+#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
-#define AT91_MCI_ARGR 0x10 /* Argument Register */
+#define AT91_MCI_ARGR 0x10 /* Argument Register */
-#define AT91_MCI_CMDR 0x14 /* Command Register */
-#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
-#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
-#define AT91_MCI_RSPTYP_NONE (0 << 6)
-#define AT91_MCI_RSPTYP_48 (1 << 6)
-#define AT91_MCI_RSPTYP_136 (2 << 6)
-#define AT91_MCI_SPCMD (7 << 8) /* Special Command */
-#define AT91_MCI_SPCMD_NONE (0 << 8)
-#define AT91_MCI_SPCMD_INIT (1 << 8)
-#define AT91_MCI_SPCMD_SYNC (2 << 8)
-#define AT91_MCI_SPCMD_ICMD (4 << 8)
-#define AT91_MCI_SPCMD_IRESP (5 << 8)
-#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
-#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
-#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
-#define AT91_MCI_TRCMD_NONE (0 << 16)
-#define AT91_MCI_TRCMD_START (1 << 16)
-#define AT91_MCI_TRCMD_STOP (2 << 16)
-#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
-#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
-#define AT91_MCI_TRTYP_BLOCK (0 << 19)
-#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
-#define AT91_MCI_TRTYP_STREAM (2 << 19)
+#define AT91_MCI_CMDR 0x14 /* Command Register */
+#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
+#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
+#define AT91_MCI_RSPTYP_NONE (0 << 6)
+#define AT91_MCI_RSPTYP_48 (1 << 6)
+#define AT91_MCI_RSPTYP_136 (2 << 6)
+#define AT91_MCI_SPCMD (7 << 8) /* Special Command */
+#define AT91_MCI_SPCMD_NONE (0 << 8)
+#define AT91_MCI_SPCMD_INIT (1 << 8)
+#define AT91_MCI_SPCMD_SYNC (2 << 8)
+#define AT91_MCI_SPCMD_ICMD (4 << 8)
+#define AT91_MCI_SPCMD_IRESP (5 << 8)
+#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
+#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
+#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
+#define AT91_MCI_TRCMD_NONE (0 << 16)
+#define AT91_MCI_TRCMD_START (1 << 16)
+#define AT91_MCI_TRCMD_STOP (2 << 16)
+#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
+#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
+#define AT91_MCI_TRTYP_BLOCK (0 << 19)
+#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
+#define AT91_MCI_TRTYP_STREAM (2 << 19)
-#define AT91_MCI_BLKR 0x18 /* Block Register */
-#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
-#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */
+#define AT91_MCI_BLKR 0x18 /* Block Register */
+#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
+#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */
-#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
-#define AT91_MCR_RDR 0x30 /* Receive Data Register */
-#define AT91_MCR_TDR 0x34 /* Transmit Data Register */
+#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
+#define AT91_MCR_RDR 0x30 /* Receive Data Register */
+#define AT91_MCR_TDR 0x34 /* Transmit Data Register */
-#define AT91_MCI_SR 0x40 /* Status Register */
-#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */
-#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */
-#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */
-#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */
-#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */
-#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */
-#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */
-#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */
-#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */
-#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */
-#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */
-#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */
-#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */
-#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */
-#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */
-#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */
-#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */
-#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */
-#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */
-#define AT91_MCI_OVRE (1U << 30) /* Overrun */
-#define AT91_MCI_UNRE (1U << 31) /* Underrun */
+#define AT91_MCI_SR 0x40 /* Status Register */
+#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */
+#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */
+#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */
+#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */
+#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */
+#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */
+#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */
+#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */
+#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */
+#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */
+#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */
+#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */
+#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */
+#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */
+#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */
+#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */
+#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */
+#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */
+#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */
+#define AT91_MCI_OVRE (1U << 30) /* Overrun */
+#define AT91_MCI_UNRE (1U << 31) /* Underrun */
-#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
-#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
-#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
+#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
+#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
+#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
extern int at91_mci_init(void);
diff --git a/bsp/at91sam9260/drivers/board.c b/bsp/at91sam9260/drivers/board.c
index 78404a4ee0..8a063cfc86 100644
--- a/bsp/at91sam9260/drivers/board.c
+++ b/bsp/at91sam9260/drivers/board.c
@@ -40,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
extern void rt_dbgu_isr(void);
static struct mem_desc at91_mem_desc[] = {
- { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */
- { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */
- { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */
- { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
- { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */
+ { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */
+ { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */
+ { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */
+ { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
+ { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */
};
-#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
-#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
+#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
+#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
-static rt_uint32_t pit_cycle; /* write-once */
-static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
+static rt_uint32_t pit_cycle; /* write-once */
+static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
/**
* This function will handle rtos timer
*/
void rt_timer_handler(int vector, void *param)
{
- #ifdef RT_USING_DBGU
- if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1)
- {
- rt_dbgu_isr();
- }
- #endif
- if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)
- {
- unsigned nr_ticks;
+ #ifdef RT_USING_DBGU
+ if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1)
+ {
+ rt_dbgu_isr();
+ }
+ #endif
+ if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)
+ {
+ unsigned nr_ticks;
- /* Get number of ticks performed before irq, and ack it */
- nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
- rt_tick_increase();
- }
+ /* Get number of ticks performed before irq, and ack it */
+ nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+ rt_tick_increase();
+ }
}
static void at91sam926x_pit_reset(void)
{
- /* Disable timer and irqs */
- at91_sys_write(AT91_PIT_MR, 0);
+ /* Disable timer and irqs */
+ at91_sys_write(AT91_PIT_MR, 0);
- /* Clear any pending interrupts, wait for PIT to stop counting */
- while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
- ;
+ /* Clear any pending interrupts, wait for PIT to stop counting */
+ while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
+ ;
- /* Start PIT but don't enable IRQ */
- //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
- pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
- at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
- | AT91_PIT_PITIEN);
- rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
+ /* Start PIT but don't enable IRQ */
+ //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+ pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+ at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
+ | AT91_PIT_PITIEN);
+ rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
}
/*
@@ -97,19 +97,19 @@ static void at91sam926x_pit_reset(void)
*/
static void at91sam926x_pit_init(void)
{
- rt_uint32_t pit_rate;
- rt_uint32_t bits;
+ rt_uint32_t pit_rate;
+ rt_uint32_t bits;
- /*
- * Use our actual MCK to figure out how many MCK/16 ticks per
- * 1/HZ period (instead of a compile-time constant LATCH).
- */
- pit_rate = clk_get_rate(clk_get("mck")) / 16;
- rt_kprintf("pit_rate=%dHZ\n", pit_rate);
- pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
+ /*
+ * Use our actual MCK to figure out how many MCK/16 ticks per
+ * 1/HZ period (instead of a compile-time constant LATCH).
+ */
+ pit_rate = clk_get_rate(clk_get("mck")) / 16;
+ rt_kprintf("pit_rate=%dHZ\n", pit_rate);
+ pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
- /* Initialize and enable the timer */
- at91sam926x_pit_reset();
+ /* Initialize and enable the timer */
+ at91sam926x_pit_reset();
}
@@ -118,69 +118,69 @@ static void at91sam926x_pit_init(void)
*/
void rt_hw_timer_init()
{
- at91sam926x_pit_init();
+ at91sam926x_pit_init();
- /* install interrupt handler */
- rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler,
- RT_NULL, "system");
- rt_hw_interrupt_umask(AT91_ID_SYS);
+ /* install interrupt handler */
+ rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler,
+ RT_NULL, "system");
+ rt_hw_interrupt_umask(AT91_ID_SYS);
}
-
+
void at91_tc1_init()
{
- at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
- writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
- writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
- writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
- writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
+ at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
+ writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
+ writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
+ writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
+ writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
}
-#define RXRDY 0x01
-#define TXRDY (1 << 1)
-#define BPS 115200 /* serial baudrate */
+#define RXRDY 0x01
+#define TXRDY (1 << 1)
+#define BPS 115200 /* serial baudrate */
typedef struct uartport
{
- volatile rt_uint32_t CR;
- volatile rt_uint32_t MR;
- volatile rt_uint32_t IER;
- volatile rt_uint32_t IDR;
- volatile rt_uint32_t IMR;
- volatile rt_uint32_t CSR;
- volatile rt_uint32_t RHR;
- volatile rt_uint32_t THR;
- volatile rt_uint32_t BRGR;
- volatile rt_uint32_t RTOR;
- volatile rt_uint32_t TTGR;
- volatile rt_uint32_t reserved0[5];
- volatile rt_uint32_t FIDI;
- volatile rt_uint32_t NER;
- volatile rt_uint32_t reserved1;
- volatile rt_uint32_t IFR;
- volatile rt_uint32_t reserved2[44];
- volatile rt_uint32_t RPR;
- volatile rt_uint32_t RCR;
- volatile rt_uint32_t TPR;
- volatile rt_uint32_t TCR;
- volatile rt_uint32_t RNPR;
- volatile rt_uint32_t RNCR;
- volatile rt_uint32_t TNPR;
- volatile rt_uint32_t TNCR;
- volatile rt_uint32_t PTCR;
- volatile rt_uint32_t PTSR;
+ volatile rt_uint32_t CR;
+ volatile rt_uint32_t MR;
+ volatile rt_uint32_t IER;
+ volatile rt_uint32_t IDR;
+ volatile rt_uint32_t IMR;
+ volatile rt_uint32_t CSR;
+ volatile rt_uint32_t RHR;
+ volatile rt_uint32_t THR;
+ volatile rt_uint32_t BRGR;
+ volatile rt_uint32_t RTOR;
+ volatile rt_uint32_t TTGR;
+ volatile rt_uint32_t reserved0[5];
+ volatile rt_uint32_t FIDI;
+ volatile rt_uint32_t NER;
+ volatile rt_uint32_t reserved1;
+ volatile rt_uint32_t IFR;
+ volatile rt_uint32_t reserved2[44];
+ volatile rt_uint32_t RPR;
+ volatile rt_uint32_t RCR;
+ volatile rt_uint32_t TPR;
+ volatile rt_uint32_t TCR;
+ volatile rt_uint32_t RNPR;
+ volatile rt_uint32_t RNCR;
+ volatile rt_uint32_t TNPR;
+ volatile rt_uint32_t TNCR;
+ volatile rt_uint32_t PTCR;
+ volatile rt_uint32_t PTSR;
}uartport;
#define CIDR FIDI
#define EXID NER
#define FNR reserved1
-#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU)
+#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU)
static void at91_usart_putc(char c)
{
while (!(DBGU->CSR & TXRDY));
- DBGU->THR = c;
+ DBGU->THR = c;
}
/**
@@ -191,33 +191,33 @@ static void at91_usart_putc(char c)
*/
void rt_hw_console_output(const char* str)
{
- while (*str)
- {
- if (*str=='\n')
- {
- at91_usart_putc('\r');
- }
+ while (*str)
+ {
+ if (*str=='\n')
+ {
+ at91_usart_putc('\r');
+ }
- at91_usart_putc(*str++);
- }
+ at91_usart_putc(*str++);
+ }
}
static void rt_hw_console_init(void)
{
- int div;
- int mode = 0;
+ int div;
+ int mode = 0;
- DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX |
- AT91_US_RXDIS | AT91_US_TXDIS;
- mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
- AT91_US_CHMODE_NORMAL;
- mode |= AT91_US_CHRL_8;
- mode |= AT91_US_NBSTOP_1;
- mode |= AT91_US_PAR_NONE;
- DBGU->MR = mode;
- div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
- DBGU->BRGR = div;
- DBGU->CR = AT91_US_RXEN | AT91_US_TXEN;
+ DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX |
+ AT91_US_RXDIS | AT91_US_TXDIS;
+ mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
+ AT91_US_CHMODE_NORMAL;
+ mode |= AT91_US_CHRL_8;
+ mode |= AT91_US_NBSTOP_1;
+ mode |= AT91_US_PAR_NONE;
+ DBGU->MR = mode;
+ div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
+ DBGU->BRGR = div;
+ DBGU->CR = AT91_US_RXEN | AT91_US_TXEN;
}
@@ -226,31 +226,31 @@ static void rt_hw_console_init(void)
*/
void rt_hw_board_init()
{
- /* initialize the system clock */
- rt_hw_clock_init();
+ /* initialize the system clock */
+ rt_hw_clock_init();
- /* initialize console */
- rt_hw_console_init();
+ /* initialize console */
+ rt_hw_console_init();
- /* initialize mmu */
- rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
+ /* initialize mmu */
+ rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
- /* initialize hardware interrupt */
- rt_hw_interrupt_init();
+ /* initialize hardware interrupt */
+ rt_hw_interrupt_init();
- /* initialize early device */
+ /* initialize early device */
#ifdef RT_USING_COMPONENTS_INIT
- rt_components_board_init();
+ rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
- rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
- /* initialize timer0 */
- rt_hw_timer_init();
+ /* initialize timer0 */
+ rt_hw_timer_init();
/* initialize board */
#ifdef RT_USING_HEAP
- rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}
diff --git a/bsp/at91sam9260/drivers/led.c b/bsp/at91sam9260/drivers/led.c
index 8d56a99ffa..10277813d4 100644
--- a/bsp/at91sam9260/drivers/led.c
+++ b/bsp/at91sam9260/drivers/led.c
@@ -14,59 +14,59 @@
#if 1
// GB9260 board
-#define PIO_LED AT91_PIOB
-#define LED1 (1 << 25) // LED_SYS
-#define LED2 (0)
-#define LED3 (1 << 23) // LED_USR
-#define LED_ALL (LED1 | LED2 | LED3)
+#define PIO_LED AT91_PIOB
+#define LED1 (1 << 25) // LED_SYS
+#define LED2 (0)
+#define LED3 (1 << 23) // LED_USR
+#define LED_ALL (LED1 | LED2 | LED3)
#else
-#define PIO_LED AT91_PIOC
-#define LED1 (1 << 8)
-#define LED2 (1 << 11)
-#define LED3 (1 << 6)
-#define LED_ALL (LED1 | LED2 | LED3)
+#define PIO_LED AT91_PIOC
+#define LED1 (1 << 8)
+#define LED2 (1 << 11)
+#define LED3 (1 << 6)
+#define LED_ALL (LED1 | LED2 | LED3)
#endif
void led_init(void)
{
- at91_sys_write(PIO_LED+0x00, LED_ALL);
- at91_sys_write(PIO_LED+0x10, LED_ALL);
- at91_sys_write(PIO_LED+0x64, LED_ALL);
- at91_sys_write(PIO_LED+0x30, LED_ALL);
+ at91_sys_write(PIO_LED+0x00, LED_ALL);
+ at91_sys_write(PIO_LED+0x10, LED_ALL);
+ at91_sys_write(PIO_LED+0x64, LED_ALL);
+ at91_sys_write(PIO_LED+0x30, LED_ALL);
}
void led_on(int num)
{
- switch(num)
- {
- case 1:
- at91_sys_write(PIO_LED+0x34, LED1);
- break;
- case 2:
- at91_sys_write(PIO_LED+0x34, LED2);
- break;
- case 3:
- at91_sys_write(PIO_LED+0x34, LED3);
- break;
- default:
- break;
- }
+ switch(num)
+ {
+ case 1:
+ at91_sys_write(PIO_LED+0x34, LED1);
+ break;
+ case 2:
+ at91_sys_write(PIO_LED+0x34, LED2);
+ break;
+ case 3:
+ at91_sys_write(PIO_LED+0x34, LED3);
+ break;
+ default:
+ break;
+ }
}
void led_off(int num)
{
- switch(num)
- {
- case 1:
- at91_sys_write(PIO_LED+0x30, LED1);
- break;
- case 2:
- at91_sys_write(PIO_LED+0x30, LED2);
- break;
- case 3:
- at91_sys_write(PIO_LED+0x30, LED3);
- break;
- default:
- break;
- }
+ switch(num)
+ {
+ case 1:
+ at91_sys_write(PIO_LED+0x30, LED1);
+ break;
+ case 2:
+ at91_sys_write(PIO_LED+0x30, LED2);
+ break;
+ case 3:
+ at91_sys_write(PIO_LED+0x30, LED3);
+ break;
+ default:
+ break;
+ }
}
diff --git a/bsp/at91sam9260/drivers/macb.c b/bsp/at91sam9260/drivers/macb.c
index 78fdfab902..702d7e04a4 100644
--- a/bsp/at91sam9260/drivers/macb.c
+++ b/bsp/at91sam9260/drivers/macb.c
@@ -14,7 +14,7 @@
#include <at91sam926x.h>
#include "macb.h"
-#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
+#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
@@ -22,11 +22,11 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
/* Cache macros - Packet buffers would be from pbuf pool which is cached */
#define EMAC_VIRT_NOCACHE(addr) (addr)
#define EMAC_CACHE_INVALIDATE(addr, size) \
- mmu_invalidate_dcache((rt_uint32_t)addr, size)
+ mmu_invalidate_dcache((rt_uint32_t)addr, size)
#define EMAC_CACHE_WRITEBACK(addr, size) \
- mmu_clean_dcache((rt_uint32_t)addr, size)
+ mmu_clean_dcache((rt_uint32_t)addr, size)
#define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
- mmu_clean_invalidated_dcache((rt_uint32_t)addr, size)
+ mmu_clean_invalidated_dcache((rt_uint32_t)addr, size)
/* EMAC has BD's in cached memory - so need cache functions */
#define BD_CACHE_INVALIDATE(addr, size)
@@ -36,7 +36,7 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
/* EMAC internal utility function */
rt_inline unsigned long emac_virt_to_phys(unsigned long addr)
{
- return addr;
+ return addr;
}
@@ -45,112 +45,112 @@ rt_inline unsigned long emac_virt_to_phys(unsigned long addr)
#define MACB_TX_SRAM
#if defined(MACB_TX_SRAM)
-#define MACB_TX_RING_SIZE 2
-#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
-#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE)
+#define MACB_TX_RING_SIZE 2
+#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
+#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE)
#else
-#define MACB_TX_RING_SIZE 16
-#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
+#define MACB_TX_RING_SIZE 16
+#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
#endif
-#define MACB_RX_BUFFER_SIZE (4096*4)
-#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
+#define MACB_RX_BUFFER_SIZE (4096*4)
+#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
-#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE)
+#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE)
-#define TX_RING_GAP(macb) \
- (MACB_TX_RING_SIZE - (macb)->tx_pending)
+#define TX_RING_GAP(macb) \
+ (MACB_TX_RING_SIZE - (macb)->tx_pending)
-#define TX_BUFFS_AVAIL(macb) \
- (((macb)->tx_tail <= (macb)->tx_head) ? \
- (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \
- (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb))
+#define TX_BUFFS_AVAIL(macb) \
+ (((macb)->tx_tail <= (macb)->tx_head) ? \
+ (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \
+ (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb))
-#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1))
+#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1))
-#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1))
+#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1))
/* minimum number of free TX descriptors before waking up TX process */
-#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4)
+#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4)
-#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
- | MACB_BIT(ISR_ROVR))
+#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
+ | MACB_BIT(ISR_ROVR))
-#define MACB_TX_TIMEOUT 1000
-#define MACB_AUTONEG_TIMEOUT 5000000
-#define MACB_LINK_TIMEOUT 500000
+#define MACB_TX_TIMEOUT 1000
+#define MACB_AUTONEG_TIMEOUT 5000000
+#define MACB_LINK_TIMEOUT 500000
#define CONFIG_RMII
struct macb_dma_desc {
- rt_uint32_t addr;
- rt_uint32_t ctrl;
+ rt_uint32_t addr;
+ rt_uint32_t ctrl;
};
-#define RXADDR_USED 0x00000001
-#define RXADDR_WRAP 0x00000002
+#define RXADDR_USED 0x00000001
+#define RXADDR_WRAP 0x00000002
-#define RXBUF_FRMLEN_MASK 0x00000fff
-#define RXBUF_FRAME_START 0x00004000
-#define RXBUF_FRAME_END 0x00008000
-#define RXBUF_TYPEID_MATCH 0x00400000
-#define RXBUF_ADDR4_MATCH 0x00800000
-#define RXBUF_ADDR3_MATCH 0x01000000
-#define RXBUF_ADDR2_MATCH 0x02000000
-#define RXBUF_ADDR1_MATCH 0x04000000
-#define RXBUF_BROADCAST 0x80000000
+#define RXBUF_FRMLEN_MASK 0x00000fff
+#define RXBUF_FRAME_START 0x00004000
+#define RXBUF_FRAME_END 0x00008000
+#define RXBUF_TYPEID_MATCH 0x00400000
+#define RXBUF_ADDR4_MATCH 0x00800000
+#define RXBUF_ADDR3_MATCH 0x01000000
+#define RXBUF_ADDR2_MATCH 0x02000000
+#define RXBUF_ADDR1_MATCH 0x04000000
+#define RXBUF_BROADCAST 0x80000000
-#define TXBUF_FRMLEN_MASK 0x000007ff
-#define TXBUF_FRAME_END 0x00008000
-#define TXBUF_NOCRC 0x00010000
-#define TXBUF_EXHAUSTED 0x08000000
-#define TXBUF_UNDERRUN 0x10000000
-#define TXBUF_MAXRETRY 0x20000000
-#define TXBUF_WRAP 0x40000000
-#define TXBUF_USED 0x80000000
+#define TXBUF_FRMLEN_MASK 0x000007ff
+#define TXBUF_FRAME_END 0x00008000
+#define TXBUF_NOCRC 0x00010000
+#define TXBUF_EXHAUSTED 0x08000000
+#define TXBUF_UNDERRUN 0x10000000
+#define TXBUF_MAXRETRY 0x20000000
+#define TXBUF_WRAP 0x40000000
+#define TXBUF_USED 0x80000000
/* Duplex, half or full. */
-#define DUPLEX_HALF 0x00
-#define DUPLEX_FULL 0x01
+#define DUPLEX_HALF 0x00
+#define DUPLEX_FULL 0x01
#define MAX_ADDR_LEN 6
struct rt_macb_eth
{
- /* inherit from ethernet device */
- struct eth_device parent;
+ /* inherit from ethernet device */
+ struct eth_device parent;
- unsigned int regs;
+ unsigned int regs;
- unsigned int rx_tail;
- unsigned int tx_head;
- unsigned int tx_tail;
- unsigned int rx_pending;
- unsigned int tx_pending;
+ unsigned int rx_tail;
+ unsigned int tx_head;
+ unsigned int tx_tail;
+ unsigned int rx_pending;
+ unsigned int tx_pending;
- void *rx_buffer;
- void *tx_buffer;
- struct macb_dma_desc *rx_ring;
- struct macb_dma_desc *tx_ring;
+ void *rx_buffer;
+ void *tx_buffer;
+ struct macb_dma_desc *rx_ring;
+ struct macb_dma_desc *tx_ring;
- unsigned long rx_buffer_dma;
- unsigned long tx_buffer_dma;
- unsigned long rx_ring_dma;
- unsigned long tx_ring_dma;
+ unsigned long rx_buffer_dma;
+ unsigned long tx_buffer_dma;
+ unsigned long rx_ring_dma;
+ unsigned long tx_ring_dma;
- unsigned int tx_stop;
+ unsigned int tx_stop;
- /* interface address info. */
- rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
- unsigned short phy_addr;
+ /* interface address info. */
+ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
+ unsigned short phy_addr;
- struct rt_semaphore mdio_bus_lock;
- struct rt_semaphore tx_lock;
- struct rt_semaphore rx_lock;
- struct rt_semaphore tx_ack;
- rt_uint32_t speed;
- rt_uint32_t duplex;
- rt_uint32_t link;
- struct rt_timer timer;
+ struct rt_semaphore mdio_bus_lock;
+ struct rt_semaphore tx_lock;
+ struct rt_semaphore rx_lock;
+ struct rt_semaphore tx_ack;
+ rt_uint32_t speed;
+ rt_uint32_t duplex;
+ rt_uint32_t link;
+ struct rt_timer timer;
};
static struct rt_macb_eth macb_device;
@@ -165,253 +165,253 @@ static void udelay(rt_uint32_t us)
static void rt_macb_isr(int irq, void *param)
{
- struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
- rt_device_t dev = &(macb->parent.parent);
- rt_uint32_t status, rsr, tsr;
+ struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
+ rt_device_t dev = &(macb->parent.parent);
+ rt_uint32_t status, rsr, tsr;
- status = macb_readl(macb, ISR);
+ status = macb_readl(macb, ISR);
- while (status) {
+ while (status) {
- if (status & MACB_RX_INT_FLAGS)
- {
- rsr = macb_readl(macb, RSR);
- macb_writel(macb, RSR, rsr);
- /* a frame has been received */
- eth_device_ready(&(macb_device.parent));
-
- }
+ if (status & MACB_RX_INT_FLAGS)
+ {
+ rsr = macb_readl(macb, RSR);
+ macb_writel(macb, RSR, rsr);
+ /* a frame has been received */
+ eth_device_ready(&(macb_device.parent));
- if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
- MACB_BIT(ISR_RLE)))
- {
- macb_tx(macb);
- }
+ }
- /*
- * Link change detection isn't possible with RMII, so we'll
- * add that if/when we get our hands on a full-blown MII PHY.
- */
+ if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
+ MACB_BIT(ISR_RLE)))
+ {
+ macb_tx(macb);
+ }
- if (status & MACB_BIT(HRESP))
- {
- /*
- * TODO: Reset the hardware, and maybe move the printk
- * to a lower-priority context as well (work queue?)
- */
- rt_kprintf("%s: DMA bus error: HRESP not OK\n",
- dev->parent.name);
- }
+ /*
+ * Link change detection isn't possible with RMII, so we'll
+ * add that if/when we get our hands on a full-blown MII PHY.
+ */
- status = macb_readl(macb, ISR);
- }
+ if (status & MACB_BIT(HRESP))
+ {
+ /*
+ * TODO: Reset the hardware, and maybe move the printk
+ * to a lower-priority context as well (work queue?)
+ */
+ rt_kprintf("%s: DMA bus error: HRESP not OK\n",
+ dev->parent.name);
+ }
+
+ status = macb_readl(macb, ISR);
+ }
}
static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value)
{
- unsigned long netctl;
- unsigned long netstat;
- unsigned long frame;
+ unsigned long netctl;
+ unsigned long netstat;
+ unsigned long frame;
- rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
- netctl = macb_readl(macb, NCR);
- netctl |= MACB_BIT(MPE);
- macb_writel(macb, NCR, netctl);
+ rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
+ netctl = macb_readl(macb, NCR);
+ netctl |= MACB_BIT(MPE);
+ macb_writel(macb, NCR, netctl);
- frame = (MACB_BF(SOF, 1)
- | MACB_BF(RW, 1)
- | MACB_BF(PHYA, macb->phy_addr)
- | MACB_BF(REGA, reg)
- | MACB_BF(CODE, 2)
- | MACB_BF(DATA, value));
- macb_writel(macb, MAN, frame);
+ frame = (MACB_BF(SOF, 1)
+ | MACB_BF(RW, 1)
+ | MACB_BF(PHYA, macb->phy_addr)
+ | MACB_BF(REGA, reg)
+ | MACB_BF(CODE, 2)
+ | MACB_BF(DATA, value));
+ macb_writel(macb, MAN, frame);
- do {
- netstat = macb_readl(macb, NSR);
- } while (!(netstat & MACB_BIT(IDLE)));
+ do {
+ netstat = macb_readl(macb, NSR);
+ } while (!(netstat & MACB_BIT(IDLE)));
- netctl = macb_readl(macb, NCR);
- netctl &= ~MACB_BIT(MPE);
- macb_writel(macb, NCR, netctl);
- rt_sem_release(&macb->mdio_bus_lock);
+ netctl = macb_readl(macb, NCR);
+ netctl &= ~MACB_BIT(MPE);
+ macb_writel(macb, NCR, netctl);
+ rt_sem_release(&macb->mdio_bus_lock);
}
static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg)
{
- unsigned long netctl;
- unsigned long netstat;
- unsigned long frame;
+ unsigned long netctl;
+ unsigned long netstat;
+ unsigned long frame;
- rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
- netctl = macb_readl(macb, NCR);
- netctl |= MACB_BIT(MPE);
- macb_writel(macb, NCR, netctl);
+ rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
+ netctl = macb_readl(macb, NCR);
+ netctl |= MACB_BIT(MPE);
+ macb_writel(macb, NCR, netctl);
- frame = (MACB_BF(SOF, 1)
- | MACB_BF(RW, 2)
- | MACB_BF(PHYA, macb->phy_addr)
- | MACB_BF(REGA, reg)
- | MACB_BF(CODE, 2));
- macb_writel(macb, MAN, frame);
+ frame = (MACB_BF(SOF, 1)
+ | MACB_BF(RW, 2)
+ | MACB_BF(PHYA, macb->phy_addr)
+ | MACB_BF(REGA, reg)
+ | MACB_BF(CODE, 2));
+ macb_writel(macb, MAN, frame);
- do {
- netstat = macb_readl(macb, NSR);
- } while (!(netstat & MACB_BIT(IDLE)));
+ do {
+ netstat = macb_readl(macb, NSR);
+ } while (!(netstat & MACB_BIT(IDLE)));
- frame = macb_readl(macb, MAN);
+ frame = macb_readl(macb, MAN);
- netctl = macb_readl(macb, NCR);
- netctl &= ~MACB_BIT(MPE);
- macb_writel(macb, NCR, netctl);
- rt_sem_release(&macb->mdio_bus_lock);
+ netctl = macb_readl(macb, NCR);
+ netctl &= ~MACB_BIT(MPE);
+ macb_writel(macb, NCR, netctl);
+ rt_sem_release(&macb->mdio_bus_lock);
- return MACB_BFEXT(DATA, frame);
+ return MACB_BFEXT(DATA, frame);
}
static void macb_phy_reset(rt_device_t dev)
{
- int i;
- rt_uint16_t status, adv;
- struct rt_macb_eth *macb = dev->user_data;;
+ int i;
+ rt_uint16_t status, adv;
+ struct rt_macb_eth *macb = dev->user_data;;
- adv = ADVERTISE_CSMA | ADVERTISE_ALL;
- macb_mdio_write(macb, MII_ADVERTISE, adv);
- rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name);
- macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
- | BMCR_ANRESTART));
+ adv = ADVERTISE_CSMA | ADVERTISE_ALL;
+ macb_mdio_write(macb, MII_ADVERTISE, adv);
+ rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name);
+ macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
+ | BMCR_ANRESTART));
- for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++)
- {
- status = macb_mdio_read(macb, MII_BMSR);
- if (status & BMSR_ANEGCOMPLETE)
- break;
- udelay(100);
- }
+ for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++)
+ {
+ status = macb_mdio_read(macb, MII_BMSR);
+ if (status & BMSR_ANEGCOMPLETE)
+ break;
+ udelay(100);
+ }
- if (status & BMSR_ANEGCOMPLETE)
- rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name);
- else
- rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n",
- dev->parent.name, status);
+ if (status & BMSR_ANEGCOMPLETE)
+ rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name);
+ else
+ rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n",
+ dev->parent.name, status);
}
static int macb_phy_init(rt_device_t dev)
{
- struct rt_macb_eth *macb = dev->user_data;
- rt_uint32_t ncfgr;
- rt_uint16_t phy_id, status, adv, lpa;
- int media, speed, duplex;
- int i;
+ struct rt_macb_eth *macb = dev->user_data;
+ rt_uint32_t ncfgr;
+ rt_uint16_t phy_id, status, adv, lpa;
+ int media, speed, duplex;
+ int i;
- /* Check if the PHY is up to snuff... */
- phy_id = macb_mdio_read(macb, MII_PHYSID1);
- if (phy_id == 0xffff)
- {
- rt_kprintf("%s: No PHY present\n", dev->parent.name);
- return 0;
- }
+ /* Check if the PHY is up to snuff... */
+ phy_id = macb_mdio_read(macb, MII_PHYSID1);
+ if (phy_id == 0xffff)
+ {
+ rt_kprintf("%s: No PHY present\n", dev->parent.name);
+ return 0;
+ }
- status = macb_mdio_read(macb, MII_BMSR);
- if (!(status & BMSR_LSTATUS))
- {
- /* Try to re-negotiate if we don't have link already. */
- macb_phy_reset(dev);
+ status = macb_mdio_read(macb, MII_BMSR);
+ if (!(status & BMSR_LSTATUS))
+ {
+ /* Try to re-negotiate if we don't have link already. */
+ macb_phy_reset(dev);
- for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++)
- {
- status = macb_mdio_read(macb, MII_BMSR);
- if (status & BMSR_LSTATUS)
- break;
- udelay(100);
- }
- }
+ for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++)
+ {
+ status = macb_mdio_read(macb, MII_BMSR);
+ if (status & BMSR_LSTATUS)
+ break;
+ udelay(100);
+ }
+ }
- if (!(status & BMSR_LSTATUS))
- {
- rt_kprintf("%s: link down (status: 0x%04x)\n",
- dev->parent.name, status);
- return 0;
- }
- else
- {
- adv = macb_mdio_read(macb, MII_ADVERTISE);
- lpa = macb_mdio_read(macb, MII_LPA);
- media = mii_nway_result(lpa & adv);
- speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
- ? 1 : 0);
- duplex = (media & ADVERTISE_FULL) ? 1 : 0;
- rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
- dev->parent.name,
- speed ? "100" : "10",
- duplex ? "full" : "half",
- lpa);
+ if (!(status & BMSR_LSTATUS))
+ {
+ rt_kprintf("%s: link down (status: 0x%04x)\n",
+ dev->parent.name, status);
+ return 0;
+ }
+ else
+ {
+ adv = macb_mdio_read(macb, MII_ADVERTISE);
+ lpa = macb_mdio_read(macb, MII_LPA);
+ media = mii_nway_result(lpa & adv);
+ speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
+ ? 1 : 0);
+ duplex = (media & ADVERTISE_FULL) ? 1 : 0;
+ rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
+ dev->parent.name,
+ speed ? "100" : "10",
+ duplex ? "full" : "half",
+ lpa);
- ncfgr = macb_readl(macb, NCFGR);
- ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
- if (speed)
- ncfgr |= MACB_BIT(SPD);
- if (duplex)
- ncfgr |= MACB_BIT(FD);
- macb_writel(macb, NCFGR, ncfgr);
- return 1;
- }
+ ncfgr = macb_readl(macb, NCFGR);
+ ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
+ if (speed)
+ ncfgr |= MACB_BIT(SPD);
+ if (duplex)
+ ncfgr |= MACB_BIT(FD);
+ macb_writel(macb, NCFGR, ncfgr);
+ return 1;
+ }
}
void macb_update_link(void *param)
{
- struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
- rt_device_t dev = &macb->parent.parent;
- int status, status_change = 0;
- rt_uint32_t link;
- rt_uint32_t media;
- rt_uint16_t adv, lpa;
+ struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
+ rt_device_t dev = &macb->parent.parent;
+ int status, status_change = 0;
+ rt_uint32_t link;
+ rt_uint32_t media;
+ rt_uint16_t adv, lpa;
+
+ /* Do a fake read */
+ status = macb_mdio_read(macb, MII_BMSR);
+ if (status < 0)
+ return;
- /* Do a fake read */
- status = macb_mdio_read(macb, MII_BMSR);
- if (status < 0)
- return;
+ /* Read link and autonegotiation status */
+ status = macb_mdio_read(macb, MII_BMSR);
+ if (status < 0)
+ return;
- /* Read link and autonegotiation status */
- status = macb_mdio_read(macb, MII_BMSR);
- if (status < 0)
- return;
-
- if ((status & BMSR_LSTATUS) == 0)
- link = 0;
- else
- link = 1;
+ if ((status & BMSR_LSTATUS) == 0)
+ link = 0;
+ else
+ link = 1;
- if (link != macb->link)
- {
- macb->link = link;
- status_change = 1;
- }
+ if (link != macb->link)
+ {
+ macb->link = link;
+ status_change = 1;
+ }
- if (status_change)
- {
- if (macb->link)
- {
- adv = macb_mdio_read(macb, MII_ADVERTISE);
- lpa = macb_mdio_read(macb, MII_LPA);
- media = mii_nway_result(lpa & adv);
- macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
- ? 100 : 10);
- macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0;
- rt_kprintf("%s: link up (%dMbps/%s-duplex)\n",
- dev->parent.name, macb->speed,
- DUPLEX_FULL == macb->duplex ? "Full":"Half");
- eth_device_linkchange(&macb->parent, RT_TRUE);
- }
- else
- {
- rt_kprintf("%s: link down\n", dev->parent.name);
- eth_device_linkchange(&macb->parent, RT_FALSE);
- }
+ if (status_change)
+ {
+ if (macb->link)
+ {
+ adv = macb_mdio_read(macb, MII_ADVERTISE);
+ lpa = macb_mdio_read(macb, MII_LPA);
+ media = mii_nway_result(lpa & adv);
+ macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
+ ? 100 : 10);
+ macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0;
+ rt_kprintf("%s: link up (%dMbps/%s-duplex)\n",
+ dev->parent.name, macb->speed,
+ DUPLEX_FULL == macb->duplex ? "Full":"Half");
+ eth_device_linkchange(&macb->parent, RT_TRUE);
+ }
+ else
+ {
+ rt_kprintf("%s: link down\n", dev->parent.name);
+ eth_device_linkchange(&macb->parent, RT_FALSE);
+ }
- }
+ }
}
@@ -420,190 +420,190 @@ void macb_update_link(void *param)
static rt_err_t rt_macb_init(rt_device_t dev)
{
- struct rt_macb_eth *macb = dev->user_data;
- unsigned long paddr;
- rt_uint32_t hwaddr_bottom;
- rt_uint16_t hwaddr_top;
- int i;
+ struct rt_macb_eth *macb = dev->user_data;
+ unsigned long paddr;
+ rt_uint32_t hwaddr_bottom;
+ rt_uint16_t hwaddr_top;
+ int i;
+
+ /*
+ * macb_halt should have been called at some point before now,
+ * so we'll assume the controller is idle.
+ */
- /*
- * macb_halt should have been called at some point before now,
- * so we'll assume the controller is idle.
- */
+ /* initialize DMA descriptors */
+ paddr = macb->rx_buffer_dma;
+ for (i = 0; i < MACB_RX_RING_SIZE; i++)
+ {
+ if (i == (MACB_RX_RING_SIZE - 1))
+ paddr |= RXADDR_WRAP;
+ macb->rx_ring[i].addr = paddr;
+ macb->rx_ring[i].ctrl = 0;
+ paddr += 128;
+ }
+ paddr = macb->tx_buffer_dma;
+ for (i = 0; i < MACB_TX_RING_SIZE; i++)
+ {
+ macb->tx_ring[i].addr = paddr;
+ if (i == (MACB_TX_RING_SIZE - 1))
+ macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
+ else
+ macb->tx_ring[i].ctrl = TXBUF_USED;
+ paddr += 1536;
+ }
+ macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
- /* initialize DMA descriptors */
- paddr = macb->rx_buffer_dma;
- for (i = 0; i < MACB_RX_RING_SIZE; i++)
- {
- if (i == (MACB_RX_RING_SIZE - 1))
- paddr |= RXADDR_WRAP;
- macb->rx_ring[i].addr = paddr;
- macb->rx_ring[i].ctrl = 0;
- paddr += 128;
- }
- paddr = macb->tx_buffer_dma;
- for (i = 0; i < MACB_TX_RING_SIZE; i++)
- {
- macb->tx_ring[i].addr = paddr;
- if (i == (MACB_TX_RING_SIZE - 1))
- macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
- else
- macb->tx_ring[i].ctrl = TXBUF_USED;
- paddr += 1536;
- }
- macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
+ BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
+ BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
+ macb_writel(macb, RBQP, macb->rx_ring_dma);
+ macb_writel(macb, TBQP, macb->tx_ring_dma);
- BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
- BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
- macb_writel(macb, RBQP, macb->rx_ring_dma);
- macb_writel(macb, TBQP, macb->tx_ring_dma);
-
- /* set hardware address */
- hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr));
- macb_writel(macb, SA1B, hwaddr_bottom);
- hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4)));
- macb_writel(macb, SA1T, hwaddr_top);
+ /* set hardware address */
+ hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr));
+ macb_writel(macb, SA1B, hwaddr_bottom);
+ hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4)));
+ macb_writel(macb, SA1T, hwaddr_top);
-
- /* choose RMII or MII mode. This depends on the board */
+
+ /* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
- macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
+ macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
- macb_writel(macb, USRIO, MACB_BIT(CLKEN));
+ macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#endif /* CONFIG_RMII */
- if (!macb_phy_init(dev))
- return -RT_ERROR;
+ if (!macb_phy_init(dev))
+ return -RT_ERROR;
+
+ /* Enable TX and RX */
+ macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE));
+
+ /* Enable interrupts */
+ macb_writel(macb, IER, (MACB_BIT(RCOMP)
+ | MACB_BIT(RXUBR)
+ | MACB_BIT(ISR_TUND)
+ | MACB_BIT(ISR_RLE)
+ | MACB_BIT(TXERR)
+ | MACB_BIT(TCOMP)
+ | MACB_BIT(ISR_ROVR)
+ | MACB_BIT(HRESP)));
- /* Enable TX and RX */
- macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE));
-
- /* Enable interrupts */
- macb_writel(macb, IER, (MACB_BIT(RCOMP)
- | MACB_BIT(RXUBR)
- | MACB_BIT(ISR_TUND)
- | MACB_BIT(ISR_RLE)
- | MACB_BIT(TXERR)
- | MACB_BIT(TCOMP)
- | MACB_BIT(ISR_ROVR)
- | MACB_BIT(HRESP)));
-
- /* instal interrupt */
- rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr,
- (void *)macb, "emac");
- rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC);
+ /* instal interrupt */
+ rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr,
+ (void *)macb, "emac");
+ rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC);
- rt_timer_init(&macb->timer, "link_timer",
- macb_update_link,
- (void *)macb,
- RT_TICK_PER_SECOND,
- RT_TIMER_FLAG_PERIODIC);
+ rt_timer_init(&macb->timer, "link_timer",
+ macb_update_link,
+ (void *)macb,
+ RT_TICK_PER_SECOND,
+ RT_TIMER_FLAG_PERIODIC);
- rt_timer_start(&macb->timer);
-
- return RT_EOK;
+ rt_timer_start(&macb->timer);
+
+ return RT_EOK;
}
static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_macb_close(rt_device_t dev)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
- rt_set_errno(-RT_ENOSYS);
- return 0;
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
}
static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
- rt_set_errno(-RT_ENOSYS);
- return 0;
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
}
static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args)
{
- switch(cmd)
- {
- case NIOCTL_GADDR:
- /* get mac address */
- if(args) rt_memcpy(args, macb_device.dev_addr, 6);
- else return -RT_ERROR;
- break;
+ switch(cmd)
+ {
+ case NIOCTL_GADDR:
+ /* get mac address */
+ if(args) rt_memcpy(args, macb_device.dev_addr, 6);
+ else return -RT_ERROR;
+ break;
- default :
- break;
- }
+ default :
+ break;
+ }
- return RT_EOK;
+ return RT_EOK;
}
static void macb_tx(struct rt_macb_eth *macb)
{
- unsigned int tail;
- unsigned int head;
- rt_uint32_t status;
+ unsigned int tail;
+ unsigned int head;
+ rt_uint32_t status;
- status = macb_readl(macb, TSR);
- macb_writel(macb, TSR, status);
+ status = macb_readl(macb, TSR);
+ macb_writel(macb, TSR, status);
- /*rt_kprintf("macb_tx status = %02lx\n",
- (unsigned long)status);*/
+ /*rt_kprintf("macb_tx status = %02lx\n",
+ (unsigned long)status);*/
- if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE)))
- {
- int i;
- rt_kprintf("%s: TX %s, resetting buffers\n",
- macb->parent.parent.parent.name, status & MACB_BIT(UND) ?
- "underrun" : "retry limit exceeded");
+ if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE)))
+ {
+ int i;
+ rt_kprintf("%s: TX %s, resetting buffers\n",
+ macb->parent.parent.parent.name, status & MACB_BIT(UND) ?
+ "underrun" : "retry limit exceeded");
- /* Transfer ongoing, disable transmitter, to avoid confusion */
- if (status & MACB_BIT(TGO))
- macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
+ /* Transfer ongoing, disable transmitter, to avoid confusion */
+ if (status & MACB_BIT(TGO))
+ macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
- head = macb->tx_head;
+ head = macb->tx_head;
- /*Mark all the buffer as used to avoid sending a lost buffer*/
- for (i = 0; i < MACB_TX_RING_SIZE; i++)
- macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
+ /*Mark all the buffer as used to avoid sending a lost buffer*/
+ for (i = 0; i < MACB_TX_RING_SIZE; i++)
+ macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
- /* free transmit buffer in upper layer*/
+ /* free transmit buffer in upper layer*/
- macb->tx_head = macb->tx_tail = 0;
+ macb->tx_head = macb->tx_tail = 0;
- /* Enable the transmitter again */
- if (status & MACB_BIT(TGO))
- macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE));
- }
+ /* Enable the transmitter again */
+ if (status & MACB_BIT(TGO))
+ macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE));
+ }
- if (!(status & MACB_BIT(COMP)))
- /*
- * This may happen when a buffer becomes complete
- * between reading the ISR and scanning the
- * descriptors. Nothing to worry about.
- */
- return;
+ if (!(status & MACB_BIT(COMP)))
+ /*
+ * This may happen when a buffer becomes complete
+ * between reading the ISR and scanning the
+ * descriptors. Nothing to worry about.
+ */
+ return;
- head = macb->tx_head;
- for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail))
- {
- rt_uint32_t bufstat;
+ head = macb->tx_head;
+ for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail))
+ {
+ rt_uint32_t bufstat;
- bufstat = macb->tx_ring[tail].ctrl;
+ bufstat = macb->tx_ring[tail].ctrl;
- if (!(bufstat & MACB_BIT(TX_USED)))
- break;
- }
+ if (!(bufstat & MACB_BIT(TX_USED)))
+ break;
+ }
- macb->tx_tail = tail;
- if ((macb->tx_stop == 1) &&
- TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH)
- rt_sem_release(&macb->tx_ack);
+ macb->tx_tail = tail;
+ if ((macb->tx_stop == 1) &&
+ TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH)
+ rt_sem_release(&macb->tx_ack);
}
@@ -611,286 +611,286 @@ static void macb_tx(struct rt_macb_eth *macb)
/* transmit packet. */
rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p)
{
- unsigned long ctrl;
- struct pbuf* q;
- rt_uint8_t* bufptr;
- rt_uint32_t mapping;
- struct rt_macb_eth *macb = dev->user_data;
- unsigned int tx_head = macb->tx_head;
+ unsigned long ctrl;
+ struct pbuf* q;
+ rt_uint8_t* bufptr;
+ rt_uint32_t mapping;
+ struct rt_macb_eth *macb = dev->user_data;
+ unsigned int tx_head = macb->tx_head;
- rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER);
- if (TX_BUFFS_AVAIL(macb) < 1)
- {
- rt_sem_release(&macb->tx_lock);
- rt_kprintf("Tx Ring full!\n");
- rt_kprintf("tx_head = %u, tx_tail = %u\n",
- macb->tx_head, macb->tx_tail);
- return -RT_ERROR;
- }
+ rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER);
+ if (TX_BUFFS_AVAIL(macb) < 1)
+ {
+ rt_sem_release(&macb->tx_lock);
+ rt_kprintf("Tx Ring full!\n");
+ rt_kprintf("tx_head = %u, tx_tail = %u\n",
+ macb->tx_head, macb->tx_tail);
+ return -RT_ERROR;
+ }
- macb->tx_stop = 0;
+ macb->tx_stop = 0;
- ctrl = p->tot_len & TXBUF_FRMLEN_MASK;
- ctrl |= TXBUF_FRAME_END;
- if (tx_head == (MACB_TX_RING_SIZE - 1))
- {
- ctrl |= TXBUF_WRAP;
- }
+ ctrl = p->tot_len & TXBUF_FRMLEN_MASK;
+ ctrl |= TXBUF_FRAME_END;
+ if (tx_head == (MACB_TX_RING_SIZE - 1))
+ {
+ ctrl |= TXBUF_WRAP;
+ }
#if defined(MACB_TX_SRAM)
- bufptr = macb->tx_buffer + tx_head * 1536;
+ bufptr = macb->tx_buffer + tx_head * 1536;
#else
- mapping = (unsigned long)macb->tx_buffer + tx_head * 1536;
- bufptr = (rt_uint8_t *)mapping;
+ mapping = (unsigned long)macb->tx_buffer + tx_head * 1536;
+ bufptr = (rt_uint8_t *)mapping;
#endif
- for (q = p; q != NULL; q = q->next)
- {
- memcpy(bufptr, q->payload, q->len);
- bufptr += q->len;
- }
+ for (q = p; q != NULL; q = q->next)
+ {
+ memcpy(bufptr, q->payload, q->len);
+ bufptr += q->len;
+ }
#if !defined(MACB_TX_SRAM)
- EMAC_CACHE_WRITEBACK(mapping, p->tot_len);
+ EMAC_CACHE_WRITEBACK(mapping, p->tot_len);
#endif
- macb->tx_ring[tx_head].ctrl = ctrl;
- BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc));
- tx_head = NEXT_TX(tx_head);
- macb->tx_head = tx_head;
- macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
- macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
+ macb->tx_ring[tx_head].ctrl = ctrl;
+ BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc));
+ tx_head = NEXT_TX(tx_head);
+ macb->tx_head = tx_head;
+ macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
+ macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
- if (TX_BUFFS_AVAIL(macb) < 1)
- {
- macb->tx_stop = 1;
- rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER);
- }
- rt_sem_release(&macb->tx_lock);
+ if (TX_BUFFS_AVAIL(macb) < 1)
+ {
+ macb->tx_stop = 1;
+ rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER);
+ }
+ rt_sem_release(&macb->tx_lock);
- return RT_EOK;
+ return RT_EOK;
}
static void reclaim_rx_buffers(struct rt_macb_eth *macb,
- unsigned int new_tail)
+ unsigned int new_tail)
{
- unsigned int i;
+ unsigned int i;
- i = macb->rx_tail;
- while (i > new_tail)
- {
- macb->rx_ring[i].addr &= ~RXADDR_USED;
- i++;
- if (i > MACB_RX_RING_SIZE)
- i = 0;
- }
+ i = macb->rx_tail;
+ while (i > new_tail)
+ {
+ macb->rx_ring[i].addr &= ~RXADDR_USED;
+ i++;
+ if (i > MACB_RX_RING_SIZE)
+ i = 0;
+ }
- while (i < new_tail)
- {
- macb->rx_ring[i].addr &= ~RXADDR_USED;
- i++;
- }
+ while (i < new_tail)
+ {
+ macb->rx_ring[i].addr &= ~RXADDR_USED;
+ i++;
+ }
- macb->rx_tail = new_tail;
+ macb->rx_tail = new_tail;
}
/* reception packet. */
struct pbuf *rt_macb_rx(rt_device_t dev)
{
- struct rt_macb_eth *macb = dev->user_data;
- struct pbuf* p = RT_NULL;
- rt_uint32_t len;
- unsigned int rx_tail = macb->rx_tail;
- void *buffer;
- int wrapped = 0;
- rt_uint32_t status;
+ struct rt_macb_eth *macb = dev->user_data;
+ struct pbuf* p = RT_NULL;
+ rt_uint32_t len;
+ unsigned int rx_tail = macb->rx_tail;
+ void *buffer;
+ int wrapped = 0;
+ rt_uint32_t status;
+
+ rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER);
+ for (;;)
+ {
+ if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
+ break;
- rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER);
- for (;;)
- {
- if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
- break;
+ status = macb->rx_ring[rx_tail].ctrl;
+ if (status & RXBUF_FRAME_START)
+ {
+ if (rx_tail != macb->rx_tail)
+ reclaim_rx_buffers(macb, rx_tail);
+ wrapped = 0;
+ }
- status = macb->rx_ring[rx_tail].ctrl;
- if (status & RXBUF_FRAME_START)
- {
- if (rx_tail != macb->rx_tail)
- reclaim_rx_buffers(macb, rx_tail);
- wrapped = 0;
- }
+ if (status & RXBUF_FRAME_END)
+ {
+ buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail);
+ len = status & RXBUF_FRMLEN_MASK;
+ p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
+ if (!p)
+ {
+ rt_kprintf("alloc pbuf failed\n");
+ break;
+ }
+ if (wrapped)
+ {
+ unsigned int headlen, taillen;
- if (status & RXBUF_FRAME_END)
- {
- buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail);
- len = status & RXBUF_FRMLEN_MASK;
- p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
- if (!p)
- {
- rt_kprintf("alloc pbuf failed\n");
- break;
- }
- if (wrapped)
- {
- unsigned int headlen, taillen;
+ headlen = 128 * (MACB_RX_RING_SIZE
+ - macb->rx_tail);
+ taillen = len - headlen;
+ EMAC_CACHE_INVALIDATE(buffer, headlen);
+ EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen);
+ memcpy((void *)p->payload, buffer, headlen);
+ memcpy((void *)((unsigned int)p->payload + headlen),
+ macb->rx_buffer, taillen);
+ }
+ else
+ {
+ EMAC_CACHE_INVALIDATE(buffer, len);
+ memcpy((void *)p->payload, buffer, p->len);
+ }
- headlen = 128 * (MACB_RX_RING_SIZE
- - macb->rx_tail);
- taillen = len - headlen;
- EMAC_CACHE_INVALIDATE(buffer, headlen);
- EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen);
- memcpy((void *)p->payload, buffer, headlen);
- memcpy((void *)((unsigned int)p->payload + headlen),
- macb->rx_buffer, taillen);
- }
- else
- {
- EMAC_CACHE_INVALIDATE(buffer, len);
- memcpy((void *)p->payload, buffer, p->len);
- }
-
- if (++rx_tail >= MACB_RX_RING_SIZE)
- rx_tail = 0;
- reclaim_rx_buffers(macb, rx_tail);
- break;
- }
- else
- {
- if (++rx_tail >= MACB_RX_RING_SIZE)
- {
- wrapped = 1;
- rx_tail = 0;
- }
- }
- }
+ if (++rx_tail >= MACB_RX_RING_SIZE)
+ rx_tail = 0;
+ reclaim_rx_buffers(macb, rx_tail);
+ break;
+ }
+ else
+ {
+ if (++rx_tail >= MACB_RX_RING_SIZE)
+ {
+ wrapped = 1;
+ rx_tail = 0;
+ }
+ }
+ }
- rt_sem_release(&macb->rx_lock);
+ rt_sem_release(&macb->rx_lock);
- return p;
+ return p;
}
void macb_gpio_init()
{
- /* Pins used for MII and RMII */
- at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20));
- at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20));
+ /* Pins used for MII and RMII */
+ at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20));
+ at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20));
#ifndef GONFIG_RMII
- at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29));
- at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29));
+ at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29));
+ at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29));
#endif
}
rt_err_t macb_initialize()
{
- struct rt_macb_eth *macb = &macb_device;
- unsigned long macb_hz;
- rt_uint32_t ncfgr;
-
+ struct rt_macb_eth *macb = &macb_device;
+ unsigned long macb_hz;
+ rt_uint32_t ncfgr;
+
#if defined(MACB_TX_SRAM)
- macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE;
- macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE;
- macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES;
- macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES;
+ macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE;
+ macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE;
+ macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES;
+ macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES;
#else
- macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
- if (macb->tx_ring == RT_NULL)
- goto err1;
- EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
- macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring);
- macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring);
- macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE);
- if (macb->tx_buffer == RT_NULL)
- goto err2;
- macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer);
+ macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
+ if (macb->tx_ring == RT_NULL)
+ goto err1;
+ EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
+ macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring);
+ macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring);
+ macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE);
+ if (macb->tx_buffer == RT_NULL)
+ goto err2;
+ macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer);
#endif
- macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
- if (macb->rx_ring == RT_NULL)
- goto err3;
- EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
- macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring);
- macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring);
- macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE);
- if (macb->rx_buffer == RT_NULL)
- goto err4;
- macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer);
+ macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
+ if (macb->rx_ring == RT_NULL)
+ goto err3;
+ EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
+ macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring);
+ macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring);
+ macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE);
+ if (macb->rx_buffer == RT_NULL)
+ goto err4;
+ macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer);
+
+ macb->tx_pending = DEF_TX_RING_PENDING;
- macb->tx_pending = DEF_TX_RING_PENDING;
+ macb->regs = AT91SAM9260_BASE_EMAC;
+ macb->phy_addr = 0x00;
- macb->regs = AT91SAM9260_BASE_EMAC;
- macb->phy_addr = 0x00;
-
- /*
- * Do some basic initialization so that we at least can talk
- * to the PHY
- */
- macb_hz = clk_get_rate(clk_get("mck"));
- if (macb_hz < 20000000)
- ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
- else if (macb_hz < 40000000)
- ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
- else if (macb_hz < 80000000)
- ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
- else
- ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
+ /*
+ * Do some basic initialization so that we at least can talk
+ * to the PHY
+ */
+ macb_hz = clk_get_rate(clk_get("mck"));
+ if (macb_hz < 20000000)
+ ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
+ else if (macb_hz < 40000000)
+ ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
+ else if (macb_hz < 80000000)
+ ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
+ else
+ ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
- macb_writel(macb, NCFGR, ncfgr);
+ macb_writel(macb, NCFGR, ncfgr);
- macb->link = 0;
+ macb->link = 0;
- return RT_EOK;
+ return RT_EOK;
err4:
- rt_free(macb->rx_ring);
- macb->rx_ring = RT_NULL;
+ rt_free(macb->rx_ring);
+ macb->rx_ring = RT_NULL;
err3:
#if !defined(MACB_TX_SRAM)
- rt_free(macb->tx_buffer);
- macb->tx_buffer = RT_NULL;
+ rt_free(macb->tx_buffer);
+ macb->tx_buffer = RT_NULL;
err2:
- rt_free(macb->tx_ring);
- macb->tx_ring = RT_NULL;
+ rt_free(macb->tx_ring);
+ macb->tx_ring = RT_NULL;
err1:
#endif
- return -RT_ENOMEM;
+ return -RT_ENOMEM;
}
int rt_hw_macb_init(void)
{
- rt_err_t ret;
- at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock
- macb_gpio_init();
- rt_memset(&macb_device, 0, sizeof(macb_device));
- ret = macb_initialize();
- if (ret != RT_EOK)
- {
- rt_kprintf("AT91 EMAC initialized failed\n");
- return -1;
- }
- rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO);
- rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO);
- rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO);
+ rt_err_t ret;
+ at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock
+ macb_gpio_init();
+ rt_memset(&macb_device, 0, sizeof(macb_device));
+ ret = macb_initialize();
+ if (ret != RT_EOK)
+ {
+ rt_kprintf("AT91 EMAC initialized failed\n");
+ return -1;
+ }
+ rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO);
+ rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO);
+ rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO);
+
+ macb_device.dev_addr[0] = 0x00;
+ macb_device.dev_addr[1] = 0x60;
+ macb_device.dev_addr[2] = 0x6E;
+ macb_device.dev_addr[3] = 0x11;
+ macb_device.dev_addr[4] = 0x22;
+ macb_device.dev_addr[5] = 0x33;
- macb_device.dev_addr[0] = 0x00;
- macb_device.dev_addr[1] = 0x60;
- macb_device.dev_addr[2] = 0x6E;
- macb_device.dev_addr[3] = 0x11;
- macb_device.dev_addr[4] = 0x22;
- macb_device.dev_addr[5] = 0x33;
-
- macb_device.parent.parent.init = rt_macb_init;
- macb_device.parent.parent.open = rt_macb_open;
- macb_device.parent.parent.close = rt_macb_close;
- macb_device.parent.parent.read = rt_macb_read;
- macb_device.parent.parent.write = rt_macb_write;
- macb_device.parent.parent.control = rt_macb_control;
- macb_device.parent.parent.user_data = &macb_device;
+ macb_device.parent.parent.init = rt_macb_init;
+ macb_device.parent.parent.open = rt_macb_open;
+ macb_device.parent.parent.close = rt_macb_close;
+ macb_device.parent.parent.read = rt_macb_read;
+ macb_device.parent.parent.write = rt_macb_write;
+ macb_device.parent.parent.control = rt_macb_control;
+ macb_device.parent.parent.user_data = &macb_device;
- macb_device.parent.eth_rx = rt_macb_rx;
- macb_device.parent.eth_tx = rt_macb_tx;
+ macb_device.parent.eth_rx = rt_macb_rx;
+ macb_device.parent.eth_tx = rt_macb_tx;
- rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO);
+ rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO);
- eth_device_init(&(macb_device.parent), "e0");
+ eth_device_init(&(macb_device.parent), "e0");
- return 0;
+ return 0;
}
INIT_DEVICE_EXPORT(rt_hw_macb_init);
diff --git a/bsp/at91sam9260/drivers/macb.h b/bsp/at91sam9260/drivers/macb.h
index d6ecb2dd56..ed2ad390b7 100644
--- a/bsp/at91sam9260/drivers/macb.h
+++ b/bsp/at91sam9260/drivers/macb.h
@@ -12,319 +12,319 @@
#include <mii.h>
/* MACB register offsets */
-#define MACB_NCR 0x0000
-#define MACB_NCFGR 0x0004
-#define MACB_NSR 0x0008
-#define MACB_TSR 0x0014
-#define MACB_RBQP 0x0018
-#define MACB_TBQP 0x001c
-#define MACB_RSR 0x0020
-#define MACB_ISR 0x0024
-#define MACB_IER 0x0028
-#define MACB_IDR 0x002c
-#define MACB_IMR 0x0030
-#define MACB_MAN 0x0034
-#define MACB_PTR 0x0038
-#define MACB_PFR 0x003c
-#define MACB_FTO 0x0040
-#define MACB_SCF 0x0044
-#define MACB_MCF 0x0048
-#define MACB_FRO 0x004c
-#define MACB_FCSE 0x0050
-#define MACB_ALE 0x0054
-#define MACB_DTF 0x0058
-#define MACB_LCOL 0x005c
-#define MACB_EXCOL 0x0060
-#define MACB_TUND 0x0064
-#define MACB_CSE 0x0068
-#define MACB_RRE 0x006c
-#define MACB_ROVR 0x0070
-#define MACB_RSE 0x0074
-#define MACB_ELE 0x0078
-#define MACB_RJA 0x007c
-#define MACB_USF 0x0080
-#define MACB_STE 0x0084
-#define MACB_RLE 0x0088
-#define MACB_TPF 0x008c
-#define MACB_HRB 0x0090
-#define MACB_HRT 0x0094
-#define MACB_SA1B 0x0098
-#define MACB_SA1T 0x009c
-#define MACB_SA2B 0x00a0
-#define MACB_SA2T 0x00a4
-#define MACB_SA3B 0x00a8
-#define MACB_SA3T 0x00ac
-#define MACB_SA4B 0x00b0
-#define MACB_SA4T 0x00b4
-#define MACB_TID 0x00b8
-#define MACB_TPQ 0x00bc
-#define MACB_USRIO 0x00c0
-#define MACB_WOL 0x00c4
+#define MACB_NCR 0x0000
+#define MACB_NCFGR 0x0004
+#define MACB_NSR 0x0008
+#define MACB_TSR 0x0014
+#define MACB_RBQP 0x0018
+#define MACB_TBQP 0x001c
+#define MACB_RSR 0x0020
+#define MACB_ISR 0x0024
+#define MACB_IER 0x0028
+#define MACB_IDR 0x002c
+#define MACB_IMR 0x0030
+#define MACB_MAN 0x0034
+#define MACB_PTR 0x0038
+#define MACB_PFR 0x003c
+#define MACB_FTO 0x0040
+#define MACB_SCF 0x0044
+#define MACB_MCF 0x0048
+#define MACB_FRO 0x004c
+#define MACB_FCSE 0x0050
+#define MACB_ALE 0x0054
+#define MACB_DTF 0x0058
+#define MACB_LCOL 0x005c
+#define MACB_EXCOL 0x0060
+#define MACB_TUND 0x0064
+#define MACB_CSE 0x0068
+#define MACB_RRE 0x006c
+#define MACB_ROVR 0x0070
+#define MACB_RSE 0x0074
+#define MACB_ELE 0x0078
+#define MACB_RJA 0x007c
+#define MACB_USF 0x0080
+#define MACB_STE 0x0084
+#define MACB_RLE 0x0088
+#define MACB_TPF 0x008c
+#define MACB_HRB 0x0090
+#define MACB_HRT 0x0094
+#define MACB_SA1B 0x0098
+#define MACB_SA1T 0x009c
+#define MACB_SA2B 0x00a0
+#define MACB_SA2T 0x00a4
+#define MACB_SA3B 0x00a8
+#define MACB_SA3T 0x00ac
+#define MACB_SA4B 0x00b0
+#define MACB_SA4T 0x00b4
+#define MACB_TID 0x00b8
+#define MACB_TPQ 0x00bc
+#define MACB_USRIO 0x00c0
+#define MACB_WOL 0x00c4
/* Bitfields in NCR */
-#define MACB_LB_OFFSET 0
-#define MACB_LB_SIZE 1
-#define MACB_LLB_OFFSET 1
-#define MACB_LLB_SIZE 1
-#define MACB_RE_OFFSET 2
-#define MACB_RE_SIZE 1
-#define MACB_TE_OFFSET 3
-#define MACB_TE_SIZE 1
-#define MACB_MPE_OFFSET 4
-#define MACB_MPE_SIZE 1
-#define MACB_CLRSTAT_OFFSET 5
-#define MACB_CLRSTAT_SIZE 1
-#define MACB_INCSTAT_OFFSET 6
-#define MACB_INCSTAT_SIZE 1
-#define MACB_WESTAT_OFFSET 7
-#define MACB_WESTAT_SIZE 1
-#define MACB_BP_OFFSET 8
-#define MACB_BP_SIZE 1
-#define MACB_TSTART_OFFSET 9
-#define MACB_TSTART_SIZE 1
-#define MACB_THALT_OFFSET 10
-#define MACB_THALT_SIZE 1
-#define MACB_NCR_TPF_OFFSET 11
-#define MACB_NCR_TPF_SIZE 1
-#define MACB_TZQ_OFFSET 12
-#define MACB_TZQ_SIZE 1
+#define MACB_LB_OFFSET 0
+#define MACB_LB_SIZE 1
+#define MACB_LLB_OFFSET 1
+#define MACB_LLB_SIZE 1
+#define MACB_RE_OFFSET 2
+#define MACB_RE_SIZE 1
+#define MACB_TE_OFFSET 3
+#define MACB_TE_SIZE 1
+#define MACB_MPE_OFFSET 4
+#define MACB_MPE_SIZE 1
+#define MACB_CLRSTAT_OFFSET 5
+#define MACB_CLRSTAT_SIZE 1
+#define MACB_INCSTAT_OFFSET 6
+#define MACB_INCSTAT_SIZE 1
+#define MACB_WESTAT_OFFSET 7
+#define MACB_WESTAT_SIZE 1
+#define MACB_BP_OFFSET 8
+#define MACB_BP_SIZE 1
+#define MACB_TSTART_OFFSET 9
+#define MACB_TSTART_SIZE 1
+#define MACB_THALT_OFFSET 10
+#define MACB_THALT_SIZE 1
+#define MACB_NCR_TPF_OFFSET 11
+#define MACB_NCR_TPF_SIZE 1
+#define MACB_TZQ_OFFSET 12
+#define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */
-#define MACB_SPD_OFFSET 0
-#define MACB_SPD_SIZE 1
-#define MACB_FD_OFFSET 1
-#define MACB_FD_SIZE 1
-#define MACB_BIT_RATE_OFFSET 2
-#define MACB_BIT_RATE_SIZE 1
-#define MACB_JFRAME_OFFSET 3
-#define MACB_JFRAME_SIZE 1
-#define MACB_CAF_OFFSET 4
-#define MACB_CAF_SIZE 1
-#define MACB_NBC_OFFSET 5
-#define MACB_NBC_SIZE 1
-#define MACB_NCFGR_MTI_OFFSET 6
-#define MACB_NCFGR_MTI_SIZE 1
-#define MACB_UNI_OFFSET 7
-#define MACB_UNI_SIZE 1
-#define MACB_BIG_OFFSET 8
-#define MACB_BIG_SIZE 1
-#define MACB_EAE_OFFSET 9
-#define MACB_EAE_SIZE 1
-#define MACB_CLK_OFFSET 10
-#define MACB_CLK_SIZE 2
-#define MACB_RTY_OFFSET 12
-#define MACB_RTY_SIZE 1
-#define MACB_PAE_OFFSET 13
-#define MACB_PAE_SIZE 1
-#define MACB_RBOF_OFFSET 14
-#define MACB_RBOF_SIZE 2
-#define MACB_RLCE_OFFSET 16
-#define MACB_RLCE_SIZE 1
-#define MACB_DRFCS_OFFSET 17
-#define MACB_DRFCS_SIZE 1
-#define MACB_EFRHD_OFFSET 18
-#define MACB_EFRHD_SIZE 1
-#define MACB_IRXFCS_OFFSET 19
-#define MACB_IRXFCS_SIZE 1
+#define MACB_SPD_OFFSET 0
+#define MACB_SPD_SIZE 1
+#define MACB_FD_OFFSET 1
+#define MACB_FD_SIZE 1
+#define MACB_BIT_RATE_OFFSET 2
+#define MACB_BIT_RATE_SIZE 1
+#define MACB_JFRAME_OFFSET 3
+#define MACB_JFRAME_SIZE 1
+#define MACB_CAF_OFFSET 4
+#define MACB_CAF_SIZE 1
+#define MACB_NBC_OFFSET 5
+#define MACB_NBC_SIZE 1
+#define MACB_NCFGR_MTI_OFFSET 6
+#define MACB_NCFGR_MTI_SIZE 1
+#define MACB_UNI_OFFSET 7
+#define MACB_UNI_SIZE 1
+#define MACB_BIG_OFFSET 8
+#define MACB_BIG_SIZE 1
+#define MACB_EAE_OFFSET 9
+#define MACB_EAE_SIZE 1
+#define MACB_CLK_OFFSET 10
+#define MACB_CLK_SIZE 2
+#define MACB_RTY_OFFSET 12
+#define MACB_RTY_SIZE 1
+#define MACB_PAE_OFFSET 13
+#define MACB_PAE_SIZE 1
+#define MACB_RBOF_OFFSET 14
+#define MACB_RBOF_SIZE 2
+#define MACB_RLCE_OFFSET 16
+#define MACB_RLCE_SIZE 1
+#define MACB_DRFCS_OFFSET 17
+#define MACB_DRFCS_SIZE 1
+#define MACB_EFRHD_OFFSET 18
+#define MACB_EFRHD_SIZE 1
+#define MACB_IRXFCS_OFFSET 19
+#define MACB_IRXFCS_SIZE 1
/* Bitfields in NSR */
-#define MACB_NSR_LINK_OFFSET 0
-#define MACB_NSR_LINK_SIZE 1
-#define MACB_MDIO_OFFSET 1
-#define MACB_MDIO_SIZE 1
-#define MACB_IDLE_OFFSET 2
-#define MACB_IDLE_SIZE 1
+#define MACB_NSR_LINK_OFFSET 0
+#define MACB_NSR_LINK_SIZE 1
+#define MACB_MDIO_OFFSET 1
+#define MACB_MDIO_SIZE 1
+#define MACB_IDLE_OFFSET 2
+#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
-#define MACB_UBR_OFFSET 0
-#define MACB_UBR_SIZE 1
-#define MACB_COL_OFFSET 1
-#define MACB_COL_SIZE 1
-#define MACB_TSR_RLE_OFFSET 2
-#define MACB_TSR_RLE_SIZE 1
-#define MACB_TGO_OFFSET 3
-#define MACB_TGO_SIZE 1
-#define MACB_BEX_OFFSET 4
-#define MACB_BEX_SIZE 1
-#define MACB_COMP_OFFSET 5
-#define MACB_COMP_SIZE 1
-#define MACB_UND_OFFSET 6
-#define MACB_UND_SIZE 1
+#define MACB_UBR_OFFSET 0
+#define MACB_UBR_SIZE 1
+#define MACB_COL_OFFSET 1
+#define MACB_COL_SIZE 1
+#define MACB_TSR_RLE_OFFSET 2
+#define MACB_TSR_RLE_SIZE 1
+#define MACB_TGO_OFFSET 3
+#define MACB_TGO_SIZE 1
+#define MACB_BEX_OFFSET 4
+#define MACB_BEX_SIZE 1
+#define MACB_COMP_OFFSET 5
+#define MACB_COMP_SIZE 1
+#define MACB_UND_OFFSET 6
+#define MACB_UND_SIZE 1
/* Bitfields in RSR */
-#define MACB_BNA_OFFSET 0
-#define MACB_BNA_SIZE 1
-#define MACB_REC_OFFSET 1
-#define MACB_REC_SIZE 1
-#define MACB_OVR_OFFSET 2
-#define MACB_OVR_SIZE 1
+#define MACB_BNA_OFFSET 0
+#define MACB_BNA_SIZE 1
+#define MACB_REC_OFFSET 1
+#define MACB_REC_SIZE 1
+#define MACB_OVR_OFFSET 2
+#define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */
-#define MACB_MFD_OFFSET 0
-#define MACB_MFD_SIZE 1
-#define MACB_RCOMP_OFFSET 1
-#define MACB_RCOMP_SIZE 1
-#define MACB_RXUBR_OFFSET 2
-#define MACB_RXUBR_SIZE 1
-#define MACB_TXUBR_OFFSET 3
-#define MACB_TXUBR_SIZE 1
-#define MACB_ISR_TUND_OFFSET 4
-#define MACB_ISR_TUND_SIZE 1
-#define MACB_ISR_RLE_OFFSET 5
-#define MACB_ISR_RLE_SIZE 1
-#define MACB_TXERR_OFFSET 6
-#define MACB_TXERR_SIZE 1
-#define MACB_TCOMP_OFFSET 7
-#define MACB_TCOMP_SIZE 1
-#define MACB_ISR_LINK_OFFSET 9
-#define MACB_ISR_LINK_SIZE 1
-#define MACB_ISR_ROVR_OFFSET 10
-#define MACB_ISR_ROVR_SIZE 1
-#define MACB_HRESP_OFFSET 11
-#define MACB_HRESP_SIZE 1
-#define MACB_PFR_OFFSET 12
-#define MACB_PFR_SIZE 1
-#define MACB_PTZ_OFFSET 13
-#define MACB_PTZ_SIZE 1
+#define MACB_MFD_OFFSET 0
+#define MACB_MFD_SIZE 1
+#define MACB_RCOMP_OFFSET 1
+#define MACB_RCOMP_SIZE 1
+#define MACB_RXUBR_OFFSET 2
+#define MACB_RXUBR_SIZE 1
+#define MACB_TXUBR_OFFSET 3
+#define MACB_TXUBR_SIZE 1
+#define MACB_ISR_TUND_OFFSET 4
+#define MACB_ISR_TUND_SIZE 1
+#define MACB_ISR_RLE_OFFSET 5
+#define MACB_ISR_RLE_SIZE 1
+#define MACB_TXERR_OFFSET 6
+#define MACB_TXERR_SIZE 1
+#define MACB_TCOMP_OFFSET 7
+#define MACB_TCOMP_SIZE 1
+#define MACB_ISR_LINK_OFFSET 9
+#define MACB_ISR_LINK_SIZE 1
+#define MACB_ISR_ROVR_OFFSET 10
+#define MACB_ISR_ROVR_SIZE 1
+#define MACB_HRESP_OFFSET 11
+#define MACB_HRESP_SIZE 1
+#define MACB_PFR_OFFSET 12
+#define MACB_PFR_SIZE 1
+#define MACB_PTZ_OFFSET 13
+#define MACB_PTZ_SIZE 1
/* Bitfields in MAN */
-#define MACB_DATA_OFFSET 0
-#define MACB_DATA_SIZE 16
-#define MACB_CODE_OFFSET 16
-#define MACB_CODE_SIZE 2
-#define MACB_REGA_OFFSET 18
-#define MACB_REGA_SIZE 5
-#define MACB_PHYA_OFFSET 23
-#define MACB_PHYA_SIZE 5
-#define MACB_RW_OFFSET 28
-#define MACB_RW_SIZE 2
-#define MACB_SOF_OFFSET 30
-#define MACB_SOF_SIZE 2
+#define MACB_DATA_OFFSET 0
+#define MACB_DATA_SIZE 16
+#define MACB_CODE_OFFSET 16
+#define MACB_CODE_SIZE 2
+#define MACB_REGA_OFFSET 18
+#define MACB_REGA_SIZE 5
+#define MACB_PHYA_OFFSET 23
+#define MACB_PHYA_SIZE 5
+#define MACB_RW_OFFSET 28
+#define MACB_RW_SIZE 2
+#define MACB_SOF_OFFSET 30
+#define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */
-#define MACB_MII_OFFSET 0
-#define MACB_MII_SIZE 1
-#define MACB_EAM_OFFSET 1
-#define MACB_EAM_SIZE 1
-#define MACB_TX_PAUSE_OFFSET 2
-#define MACB_TX_PAUSE_SIZE 1
-#define MACB_TX_PAUSE_ZERO_OFFSET 3
-#define MACB_TX_PAUSE_ZERO_SIZE 1
+#define MACB_MII_OFFSET 0
+#define MACB_MII_SIZE 1
+#define MACB_EAM_OFFSET 1
+#define MACB_EAM_SIZE 1
+#define MACB_TX_PAUSE_OFFSET 2
+#define MACB_TX_PAUSE_SIZE 1
+#define MACB_TX_PAUSE_ZERO_OFFSET 3
+#define MACB_TX_PAUSE_ZERO_SIZE 1
/* Bitfields in USRIO (AT91) */
-#define MACB_RMII_OFFSET 0
-#define MACB_RMII_SIZE 1
-#define MACB_CLKEN_OFFSET 1
-#define MACB_CLKEN_SIZE 1
+#define MACB_RMII_OFFSET 0
+#define MACB_RMII_SIZE 1
+#define MACB_CLKEN_OFFSET 1
+#define MACB_CLKEN_SIZE 1
/* Bitfields in WOL */
-#define MACB_IP_OFFSET 0
-#define MACB_IP_SIZE 16
-#define MACB_MAG_OFFSET 16
-#define MACB_MAG_SIZE 1
-#define MACB_ARP_OFFSET 17
-#define MACB_ARP_SIZE 1
-#define MACB_SA1_OFFSET 18
-#define MACB_SA1_SIZE 1
-#define MACB_WOL_MTI_OFFSET 19
-#define MACB_WOL_MTI_SIZE 1
+#define MACB_IP_OFFSET 0
+#define MACB_IP_SIZE 16
+#define MACB_MAG_OFFSET 16
+#define MACB_MAG_SIZE 1
+#define MACB_ARP_OFFSET 17
+#define MACB_ARP_SIZE 1
+#define MACB_SA1_OFFSET 18
+#define MACB_SA1_SIZE 1
+#define MACB_WOL_MTI_OFFSET 19
+#define MACB_WOL_MTI_SIZE 1
/* Constants for CLK */
-#define MACB_CLK_DIV8 0
-#define MACB_CLK_DIV16 1
-#define MACB_CLK_DIV32 2
-#define MACB_CLK_DIV64 3
+#define MACB_CLK_DIV8 0
+#define MACB_CLK_DIV16 1
+#define MACB_CLK_DIV32 2
+#define MACB_CLK_DIV64 3
/* Constants for MAN register */
-#define MACB_MAN_SOF 1
-#define MACB_MAN_WRITE 1
-#define MACB_MAN_READ 2
-#define MACB_MAN_CODE 2
+#define MACB_MAN_SOF 1
+#define MACB_MAN_WRITE 1
+#define MACB_MAN_READ 2
+#define MACB_MAN_CODE 2
/* Bit manipulation macros */
-#define MACB_BIT(name) \
- (1 << MACB_##name##_OFFSET)
-#define MACB_BF(name,value) \
- (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
- << MACB_##name##_OFFSET)
+#define MACB_BIT(name) \
+ (1 << MACB_##name##_OFFSET)
+#define MACB_BF(name,value) \
+ (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
+ << MACB_##name##_OFFSET)
#define MACB_BFEXT(name,value)\
- (((value) >> MACB_##name##_OFFSET) \
- & ((1 << MACB_##name##_SIZE) - 1))
-#define MACB_BFINS(name,value,old) \
- (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
- << MACB_##name##_OFFSET)) \
- | MACB_BF(name,value))
+ (((value) >> MACB_##name##_OFFSET) \
+ & ((1 << MACB_##name##_SIZE) - 1))
+#define MACB_BFINS(name,value,old) \
+ (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
+ << MACB_##name##_OFFSET)) \
+ | MACB_BF(name,value))
/* Register access macros */
-#define macb_readl(port,reg) \
- readl((port)->regs + MACB_##reg)
-#define macb_writel(port,reg,value) \
- writel((value), (port)->regs + MACB_##reg)
+#define macb_readl(port,reg) \
+ readl((port)->regs + MACB_##reg)
+#define macb_writel(port,reg,value) \
+ writel((value), (port)->regs + MACB_##reg)
struct dma_desc {
- rt_uint32_t addr;
- rt_uint32_t ctrl;
+ rt_uint32_t addr;
+ rt_uint32_t ctrl;
};
/* DMA descriptor bitfields */
-#define MACB_RX_USED_OFFSET 0
-#define MACB_RX_USED_SIZE 1
-#define MACB_RX_WRAP_OFFSET 1
-#define MACB_RX_WRAP_SIZE 1
-#define MACB_RX_WADDR_OFFSET 2
-#define MACB_RX_WADDR_SIZE 30
+#define MACB_RX_USED_OFFSET 0
+#define MACB_RX_USED_SIZE 1
+#define MACB_RX_WRAP_OFFSET 1
+#define MACB_RX_WRAP_SIZE 1
+#define MACB_RX_WADDR_OFFSET 2
+#define MACB_RX_WADDR_SIZE 30
-#define MACB_RX_FRMLEN_OFFSET 0
-#define MACB_RX_FRMLEN_SIZE 12
-#define MACB_RX_OFFSET_OFFSET 12
-#define MACB_RX_OFFSET_SIZE 2
-#define MACB_RX_SOF_OFFSET 14
-#define MACB_RX_SOF_SIZE 1
-#define MACB_RX_EOF_OFFSET 15
-#define MACB_RX_EOF_SIZE 1
-#define MACB_RX_CFI_OFFSET 16
-#define MACB_RX_CFI_SIZE 1
-#define MACB_RX_VLAN_PRI_OFFSET 17
-#define MACB_RX_VLAN_PRI_SIZE 3
-#define MACB_RX_PRI_TAG_OFFSET 20
-#define MACB_RX_PRI_TAG_SIZE 1
-#define MACB_RX_VLAN_TAG_OFFSET 21
-#define MACB_RX_VLAN_TAG_SIZE 1
-#define MACB_RX_TYPEID_MATCH_OFFSET 22
-#define MACB_RX_TYPEID_MATCH_SIZE 1
-#define MACB_RX_SA4_MATCH_OFFSET 23
-#define MACB_RX_SA4_MATCH_SIZE 1
-#define MACB_RX_SA3_MATCH_OFFSET 24
-#define MACB_RX_SA3_MATCH_SIZE 1
-#define MACB_RX_SA2_MATCH_OFFSET 25
-#define MACB_RX_SA2_MATCH_SIZE 1
-#define MACB_RX_SA1_MATCH_OFFSET 26
-#define MACB_RX_SA1_MATCH_SIZE 1
-#define MACB_RX_EXT_MATCH_OFFSET 28
-#define MACB_RX_EXT_MATCH_SIZE 1
-#define MACB_RX_UHASH_MATCH_OFFSET 29
-#define MACB_RX_UHASH_MATCH_SIZE 1
-#define MACB_RX_MHASH_MATCH_OFFSET 30
-#define MACB_RX_MHASH_MATCH_SIZE 1
-#define MACB_RX_BROADCAST_OFFSET 31
-#define MACB_RX_BROADCAST_SIZE 1
+#define MACB_RX_FRMLEN_OFFSET 0
+#define MACB_RX_FRMLEN_SIZE 12
+#define MACB_RX_OFFSET_OFFSET 12
+#define MACB_RX_OFFSET_SIZE 2
+#define MACB_RX_SOF_OFFSET 14
+#define MACB_RX_SOF_SIZE 1
+#define MACB_RX_EOF_OFFSET 15
+#define MACB_RX_EOF_SIZE 1
+#define MACB_RX_CFI_OFFSET 16
+#define MACB_RX_CFI_SIZE 1
+#define MACB_RX_VLAN_PRI_OFFSET 17
+#define MACB_RX_VLAN_PRI_SIZE 3
+#define MACB_RX_PRI_TAG_OFFSET 20
+#define MACB_RX_PRI_TAG_SIZE 1
+#define MACB_RX_VLAN_TAG_OFFSET 21
+#define MACB_RX_VLAN_TAG_SIZE 1
+#define MACB_RX_TYPEID_MATCH_OFFSET 22
+#define MACB_RX_TYPEID_MATCH_SIZE 1
+#define MACB_RX_SA4_MATCH_OFFSET 23
+#define MACB_RX_SA4_MATCH_SIZE 1
+#define MACB_RX_SA3_MATCH_OFFSET 24
+#define MACB_RX_SA3_MATCH_SIZE 1
+#define MACB_RX_SA2_MATCH_OFFSET 25
+#define MACB_RX_SA2_MATCH_SIZE 1
+#define MACB_RX_SA1_MATCH_OFFSET 26
+#define MACB_RX_SA1_MATCH_SIZE 1
+#define MACB_RX_EXT_MATCH_OFFSET 28
+#define MACB_RX_EXT_MATCH_SIZE 1
+#define MACB_RX_UHASH_MATCH_OFFSET 29
+#define MACB_RX_UHASH_MATCH_SIZE 1
+#define MACB_RX_MHASH_MATCH_OFFSET 30
+#define MACB_RX_MHASH_MATCH_SIZE 1
+#define MACB_RX_BROADCAST_OFFSET 31
+#define MACB_RX_BROADCAST_SIZE 1
-#define MACB_TX_FRMLEN_OFFSET 0
-#define MACB_TX_FRMLEN_SIZE 11
-#define MACB_TX_LAST_OFFSET 15
-#define MACB_TX_LAST_SIZE 1
-#define MACB_TX_NOCRC_OFFSET 16
-#define MACB_TX_NOCRC_SIZE 1
-#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
-#define MACB_TX_BUF_EXHAUSTED_SIZE 1
-#define MACB_TX_UNDERRUN_OFFSET 28
-#define MACB_TX_UNDERRUN_SIZE 1
-#define MACB_TX_ERROR_OFFSET 29
-#define MACB_TX_ERROR_SIZE 1
-#define MACB_TX_WRAP_OFFSET 30
-#define MACB_TX_WRAP_SIZE 1
-#define MACB_TX_USED_OFFSET 31
-#define MACB_TX_USED_SIZE 1
+#define MACB_TX_FRMLEN_OFFSET 0
+#define MACB_TX_FRMLEN_SIZE 11
+#define MACB_TX_LAST_OFFSET 15
+#define MACB_TX_LAST_SIZE 1
+#define MACB_TX_NOCRC_OFFSET 16
+#define MACB_TX_NOCRC_SIZE 1
+#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
+#define MACB_TX_BUF_EXHAUSTED_SIZE 1
+#define MACB_TX_UNDERRUN_OFFSET 28
+#define MACB_TX_UNDERRUN_SIZE 1
+#define MACB_TX_ERROR_OFFSET 29
+#define MACB_TX_ERROR_SIZE 1
+#define MACB_TX_WRAP_OFFSET 30
+#define MACB_TX_WRAP_SIZE 1
+#define MACB_TX_USED_OFFSET 31
+#define MACB_TX_USED_SIZE 1
extern int rt_hw_macb_init();
diff --git a/bsp/at91sam9260/drivers/mii.h b/bsp/at91sam9260/drivers/mii.h
index 84f7cfe91c..03d914b7c3 100644
--- a/bsp/at91sam9260/drivers/mii.h
+++ b/bsp/at91sam9260/drivers/mii.h
@@ -22,7 +22,7 @@
#define MII_EXPANSION 0x06 /* Expansion register */
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
#define MII_STAT1000 0x0a /* 1000BASE-T status */
-#define MII_ESTATUS 0x0f /* Extended Status */
+#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
@@ -37,7 +37,7 @@
/* Basic mode control register. */
#define BMCR_RESV 0x003f /* Unused... */
-#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
+#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
@@ -56,7 +56,7 @@
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x00c0 /* Unused... */
-#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
+#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
@@ -85,7 +85,7 @@
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
- ADVERTISE_CSMA)
+ ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
@@ -107,8 +107,8 @@
#define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */
-#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
-#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
+#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
@@ -118,8 +118,8 @@
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */
-#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
-#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
+#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */
@@ -137,8 +137,8 @@
#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
/* Flow control flags */
-#define FLOW_CTRL_TX 0x01
-#define FLOW_CTRL_RX 0x02
+#define FLOW_CTRL_TX 0x01
+#define FLOW_CTRL_RX 0x02
/**
* mii_nway_result
diff --git a/bsp/at91sam9260/drivers/usart.c b/bsp/at91sam9260/drivers/usart.c
index dee5585f36..2d493a21bb 100644
--- a/bsp/at91sam9260/drivers/usart.c
+++ b/bsp/at91sam9260/drivers/usart.c
@@ -14,54 +14,54 @@
#include <at91sam926x.h>
#include <rtdevice.h>
-#define RXRDY 0x01
-#define TXRDY (1 << 1)
+#define RXRDY 0x01
+#define TXRDY (1 << 1)
typedef struct uartport
{
- volatile rt_uint32_t CR;
- volatile rt_uint32_t MR;
- volatile rt_uint32_t IER;
- volatile rt_uint32_t IDR;
- volatile rt_uint32_t IMR;
- volatile rt_uint32_t CSR;
- volatile rt_uint32_t RHR;
- volatile rt_uint32_t THR;
- volatile rt_uint32_t BRGR;
- volatile rt_uint32_t RTOR;
- volatile rt_uint32_t TTGR;
- volatile rt_uint32_t reserved0[5];
- volatile rt_uint32_t FIDI;
- volatile rt_uint32_t NER;
- volatile rt_uint32_t reserved1;
- volatile rt_uint32_t IFR;
- volatile rt_uint32_t reserved2[44];
- volatile rt_uint32_t RPR;
- volatile rt_uint32_t RCR;
- volatile rt_uint32_t TPR;
- volatile rt_uint32_t TCR;
- volatile rt_uint32_t RNPR;
- volatile rt_uint32_t RNCR;
- volatile rt_uint32_t TNPR;
- volatile rt_uint32_t TNCR;
- volatile rt_uint32_t PTCR;
- volatile rt_uint32_t PTSR;
+ volatile rt_uint32_t CR;
+ volatile rt_uint32_t MR;
+ volatile rt_uint32_t IER;
+ volatile rt_uint32_t IDR;
+ volatile rt_uint32_t IMR;
+ volatile rt_uint32_t CSR;
+ volatile rt_uint32_t RHR;
+ volatile rt_uint32_t THR;
+ volatile rt_uint32_t BRGR;
+ volatile rt_uint32_t RTOR;
+ volatile rt_uint32_t TTGR;
+ volatile rt_uint32_t reserved0[5];
+ volatile rt_uint32_t FIDI;
+ volatile rt_uint32_t NER;
+ volatile rt_uint32_t reserved1;
+ volatile rt_uint32_t IFR;
+ volatile rt_uint32_t reserved2[44];
+ volatile rt_uint32_t RPR;
+ volatile rt_uint32_t RCR;
+ volatile rt_uint32_t TPR;
+ volatile rt_uint32_t TCR;
+ volatile rt_uint32_t RNPR;
+ volatile rt_uint32_t RNCR;
+ volatile rt_uint32_t TNPR;
+ volatile rt_uint32_t TNCR;
+ volatile rt_uint32_t PTCR;
+ volatile rt_uint32_t PTSR;
}uartport;
#define CIDR FIDI
#define EXID NER
#define FNR reserved1
-#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU)
+#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU)
-#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0)
-#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1)
-#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2)
-#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3)
+#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0)
+#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1)
+#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2)
+#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3)
struct at91_uart {
- uartport *port;
- int irq;
+ uartport *port;
+ int irq;
};
@@ -71,18 +71,18 @@ struct at91_uart {
*/
void rt_at91_usart_handler(int vector, void *param)
{
- int status;
- struct at91_uart *uart;
- rt_device_t dev = (rt_device_t)param;
- uart = (struct at91_uart *)dev->user_data;
- status = uart->port->CSR;
- if (!(status & uart->port->IMR))
- {
- return;
- }
- rt_interrupt_enter();
- rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
- rt_interrupt_leave();
+ int status;
+ struct at91_uart *uart;
+ rt_device_t dev = (rt_device_t)param;
+ uart = (struct at91_uart *)dev->user_data;
+ status = uart->port->CSR;
+ if (!(status & uart->port->IMR))
+ {
+ return;
+ }
+ rt_interrupt_enter();
+ rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
+ rt_interrupt_leave();
}
/**
@@ -91,67 +91,67 @@ void rt_at91_usart_handler(int vector, void *param)
static rt_err_t at91_usart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
{
- int div;
- int mode = 0;
- struct at91_uart *uart;
+ int div;
+ int mode = 0;
+ struct at91_uart *uart;
- RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
- uart = (struct at91_uart *)serial->parent.user_data;
+ uart = (struct at91_uart *)serial->parent.user_data;
- uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX |
- AT91_US_RXDIS | AT91_US_TXDIS;
- mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
- AT91_US_CHMODE_NORMAL;
- switch (cfg->data_bits)
- {
- case DATA_BITS_8:
- mode |= AT91_US_CHRL_8;
- break;
- case DATA_BITS_7:
- mode |= AT91_US_CHRL_7;
- break;
- case DATA_BITS_6:
- mode |= AT91_US_CHRL_6;
- break;
- case DATA_BITS_5:
- mode |= AT91_US_CHRL_5;
- break;
- default:
- mode |= AT91_US_CHRL_8;
- break;
- }
+ uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX |
+ AT91_US_RXDIS | AT91_US_TXDIS;
+ mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
+ AT91_US_CHMODE_NORMAL;
+ switch (cfg->data_bits)
+ {
+ case DATA_BITS_8:
+ mode |= AT91_US_CHRL_8;
+ break;
+ case DATA_BITS_7:
+ mode |= AT91_US_CHRL_7;
+ break;
+ case DATA_BITS_6:
+ mode |= AT91_US_CHRL_6;
+ break;
+ case DATA_BITS_5:
+ mode |= AT91_US_CHRL_5;
+ break;
+ default:
+ mode |= AT91_US_CHRL_8;
+ break;
+ }
- switch (cfg->stop_bits)
- {
- case STOP_BITS_2:
- mode |= AT91_US_NBSTOP_2;
- break;
- case STOP_BITS_1:
- default:
- mode |= AT91_US_NBSTOP_1;
- break;
- }
+ switch (cfg->stop_bits)
+ {
+ case STOP_BITS_2:
+ mode |= AT91_US_NBSTOP_2;
+ break;
+ case STOP_BITS_1:
+ default:
+ mode |= AT91_US_NBSTOP_1;
+ break;
+ }
- switch (cfg->parity)
- {
- case PARITY_ODD:
- mode |= AT91_US_PAR_ODD;
- break;
- case PARITY_EVEN:
- mode |= AT91_US_PAR_EVEN;
- break;
- case PARITY_NONE:
- default:
- mode |= AT91_US_PAR_NONE;
- break;
- }
+ switch (cfg->parity)
+ {
+ case PARITY_ODD:
+ mode |= AT91_US_PAR_ODD;
+ break;
+ case PARITY_EVEN:
+ mode |= AT91_US_PAR_EVEN;
+ break;
+ case PARITY_NONE:
+ default:
+ mode |= AT91_US_PAR_NONE;
+ break;
+ }
- uart->port->MR = mode;
- div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
- uart->port->BRGR = div;
- uart->port->CR = AT91_US_RXEN | AT91_US_TXEN;
- uart->port->IER = 0x01;
+ uart->port->MR = mode;
+ div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
+ uart->port->BRGR = div;
+ uart->port->CR = AT91_US_RXEN | AT91_US_TXEN;
+ uart->port->IER = 0x01;
return RT_EOK;
}
@@ -168,11 +168,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial,
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
- rt_hw_interrupt_mask(uart->irq);
+ rt_hw_interrupt_mask(uart->irq);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
- rt_hw_interrupt_umask(uart->irq);
+ rt_hw_interrupt_umask(uart->irq);
break;
}
@@ -182,10 +182,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial,
static int at91_usart_putc(struct rt_serial_device *serial, char c)
{
rt_uint32_t level;
- struct at91_uart *uart = serial->parent.user_data;
+ struct at91_uart *uart = serial->parent.user_data;
while (!(uart->port->CSR & TXRDY));
- uart->port->THR = c;
+ uart->port->THR = c;
return 1;
}
@@ -193,16 +193,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c)
static int at91_usart_getc(struct rt_serial_device *serial)
{
int result;
- struct at91_uart *uart = serial->parent.user_data;
+ struct at91_uart *uart = serial->parent.user_data;
if (uart->port->CSR & RXRDY)
- {
- result = uart->port->RHR & 0xff;
- }
- else
- {
- result = -1;
- }
+ {
+ result = uart->port->RHR & 0xff;
+ }
+ else
+ {
+ result = -1;
+ }
return result;
}
@@ -218,8 +218,8 @@ static const struct rt_uart_ops at91_usart_ops =
#if defined(RT_USING_DBGU)
static struct rt_serial_device serial_dbgu;
struct at91_uart dbgu = {
- DBGU,
- AT91_ID_SYS
+ DBGU,
+ AT91_ID_SYS
};
#endif
@@ -227,82 +227,82 @@ struct at91_uart dbgu = {
#if defined(RT_USING_UART0)
static struct rt_serial_device serial0;
struct at91_uart uart0 = {
- UART0,
- AT91SAM9260_ID_US0
+ UART0,
+ AT91SAM9260_ID_US0
};
#endif
#if defined(RT_USING_UART1)
static struct rt_serial_device serial1;
struct at91_uart uart1 = {
- UART1,
- AT91SAM9260_ID_US1
+ UART1,
+ AT91SAM9260_ID_US1
};
#endif
#if defined(RT_USING_UART2)
static struct rt_serial_device serial2;
struct at91_uart uart2 = {
- UART2,
- AT91SAM9260_ID_US2
+ UART2,
+ AT91SAM9260_ID_US2
};
#endif
#if defined(RT_USING_UART3)
static struct rt_serial_device serial3;
struct at91_uart uart3 = {
- UART3,
- AT91SAM9260_ID_US3
+ UART3,
+ AT91SAM9260_ID_US3
};
#endif
void at91_usart_gpio_init(void)
{
- rt_uint32_t val;
+ rt_uint32_t val;
#ifdef RT_USING_DBGU
- at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15));
- //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
- at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15));
- at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15));
- at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15));
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+ at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15));
+ //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
+ at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15));
+ at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15));
+ at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15));
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
#ifdef RT_USING_UART0
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
- at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5));
- at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4));
- at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5));
- at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5));
- at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5));
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
+ at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5));
+ at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4));
+ at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5));
+ at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5));
+ at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5));
#endif
#ifdef RT_USING_UART1
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
- at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7));
- at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
- at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7));
- at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7));
- at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7));
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
+ at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7));
+ at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
+ at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7));
+ at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7));
+ at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7));
#endif
#ifdef RT_USING_UART2
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
- at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9));
- at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8));
- at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9));
- at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9));
- at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9));
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
+ at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9));
+ at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8));
+ at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9));
+ at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9));
+ at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9));
#endif
#ifdef RT_USING_UART3
- at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3);
- at91_sys_write(AT91_PIOB + PIO_IDR, (1<<10)|(1<<11));
- at91_sys_write(AT91_PIOB + PIO_PUER, (1<<10));
- at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<11));
- at91_sys_write(AT91_PIOB + PIO_ASR, (1<<10)|(1<<11));
- at91_sys_write(AT91_PIOB + PIO_PDR, (1<<10)|(1<<11));
+ at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3);
+ at91_sys_write(AT91_PIOB + PIO_IDR, (1<<10)|(1<<11));
+ at91_sys_write(AT91_PIOB + PIO_PUER, (1<<10));
+ at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<11));
+ at91_sys_write(AT91_PIOB + PIO_ASR, (1<<10)|(1<<11));
+ at91_sys_write(AT91_PIOB + PIO_PDR, (1<<10)|(1<<11));
#endif
}
@@ -314,17 +314,17 @@ void at91_usart_gpio_init(void)
*/
int rt_hw_uart_init(void)
{
- at91_usart_gpio_init();
+ at91_usart_gpio_init();
#if defined(RT_USING_DBGU)
- serial_dbgu.ops = &at91_usart_ops;
- serial_dbgu.config.baud_rate = BAUD_RATE_115200;
+ serial_dbgu.ops = &at91_usart_ops;
+ serial_dbgu.config.baud_rate = BAUD_RATE_115200;
serial_dbgu.config.bit_order = BIT_ORDER_LSB;
serial_dbgu.config.data_bits = DATA_BITS_8;
serial_dbgu.config.parity = PARITY_NONE;
serial_dbgu.config.stop_bits = STOP_BITS_1;
serial_dbgu.config.invert = NRZ_NORMAL;
- serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
+ serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial_dbgu, "dbgu",
@@ -333,83 +333,83 @@ int rt_hw_uart_init(void)
#endif
#if defined(RT_USING_UART0)
- serial0.ops = &at91_usart_ops;
- serial0.config.baud_rate = BAUD_RATE_115200;
+ serial0.ops = &at91_usart_ops;
+ serial0.config.baud_rate = BAUD_RATE_115200;
serial0.config.bit_order = BIT_ORDER_LSB;
serial0.config.data_bits = DATA_BITS_8;
serial0.config.parity = PARITY_NONE;
serial0.config.stop_bits = STOP_BITS_1;
serial0.config.invert = NRZ_NORMAL;
- serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
+ serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart0);
- rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler,
- (void *)&(serial0.parent), "UART0");
- rt_hw_interrupt_umask(uart0.irq);
+ rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler,
+ (void *)&(serial0.parent), "UART0");
+ rt_hw_interrupt_umask(uart0.irq);
#endif
#if defined(RT_USING_UART1)
- serial1.ops = &at91_usart_ops;
+ serial1.ops = &at91_usart_ops;
serial1.int_rx = &uart1_int_rx;
- serial1.config.baud_rate = BAUD_RATE_115200;
+ serial1.config.baud_rate = BAUD_RATE_115200;
serial1.config.bit_order = BIT_ORDER_LSB;
serial1.config.data_bits = DATA_BITS_8;
serial1.config.parity = PARITY_NONE;
serial1.config.stop_bits = STOP_BITS_1;
serial1.config.invert = NRZ_NORMAL;
- serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
+ serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart1);
- rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
- (void *)&(serial1.parent), "UART1");
- rt_hw_interrupt_umask(uart1.irq);
+ rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
+ (void *)&(serial1.parent), "UART1");
+ rt_hw_interrupt_umask(uart1.irq);
#endif
#if defined(RT_USING_UART2)
- serial2.ops = &at91_usart_ops;
- serial2.config.baud_rate = BAUD_RATE_115200;
+ serial2.ops = &at91_usart_ops;
+ serial2.config.baud_rate = BAUD_RATE_115200;
serial2.config.bit_order = BIT_ORDER_LSB;
serial2.config.data_bits = DATA_BITS_8;
serial2.config.parity = PARITY_NONE;
serial2.config.stop_bits = STOP_BITS_1;
serial2.config.invert = NRZ_NORMAL;
- serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
+ serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart2);
- rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
- (void *)&(serial2.parent), "UART2");
- rt_hw_interrupt_umask(uart2.irq);
+ rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
+ (void *)&(serial2.parent), "UART2");
+ rt_hw_interrupt_umask(uart2.irq);
#endif
#if defined(RT_USING_UART3)
- serial3.ops = &at91_usart_ops;
- serial3.config.baud_rate = BAUD_RATE_115200;
+ serial3.ops = &at91_usart_ops;
+ serial3.config.baud_rate = BAUD_RATE_115200;
serial3.config.bit_order = BIT_ORDER_LSB;
serial3.config.data_bits = DATA_BITS_8;
serial3.config.parity = PARITY_NONE;
serial3.config.stop_bits = STOP_BITS_1;
serial3.config.invert = NRZ_NORMAL;
- serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
+ serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart3);
- rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
- (void *)&(serial3.parent), "UART3");
- rt_hw_interrupt_umask(uart3.irq);
+ rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
+ (void *)&(serial3.parent), "UART3");
+ rt_hw_interrupt_umask(uart3.irq);
#endif
- return 0;
+ return 0;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);
@@ -417,7 +417,7 @@ INIT_BOARD_EXPORT(rt_hw_uart_init);
#ifdef RT_USING_DBGU
void rt_dbgu_isr(void)
{
- rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
+ rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
}
#endif
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-24 02:22:47 +0000