diff options
Diffstat (limited to 'bsp/beaglebone/applications/board.c')
| -rw-r--r-- | bsp/beaglebone/applications/board.c | 84 |
1 files changed, 42 insertions, 42 deletions
diff --git a/bsp/beaglebone/applications/board.c b/bsp/beaglebone/applications/board.c index 1ee0081b17..ff25dd7dd7 100644 --- a/bsp/beaglebone/applications/board.c +++ b/bsp/beaglebone/applications/board.c @@ -45,7 +45,7 @@ static rt_uint32_t DMTIMER = 0; static void rt_hw_timer_isr(int vector, void* param) { - rt_tick_increase(); + rt_tick_increase(); DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG; } @@ -67,73 +67,73 @@ static void timer_clk_init(void) while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8))) ; - /* Select the clock source for the Timer2 instance. */ - CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL); - /* 32k clock source */ - CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3; + /* Select the clock source for the Timer2 instance. */ + CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL); + /* 32k clock source */ + CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3; - while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) != - CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3); + while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) != + CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3); - /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */ - CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE; + /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */ + CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE; - /* Waiting for MODULEMODE field to reflect the written value. */ - while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) != - CM_PER_CLKCTRL_MODULEMODE_ENABLE); + /* Waiting for MODULEMODE field to reflect the written value. */ + while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) != + CM_PER_CLKCTRL_MODULEMODE_ENABLE); - /* - * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register - * for the module is fully functional. - */ - while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) != - CM_PER_CLKCTRL_IDLEST_FUNC); + /* + * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register + * for the module is fully functional. + */ + while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) != + CM_PER_CLKCTRL_IDLEST_FUNC); - /* Waiting for the L4LS clock */ - while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); - /* Waiting for the TIMER7 clock */ - while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK)); + /* Waiting for the L4LS clock */ + while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); + /* Waiting for the TIMER7 clock */ + while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK)); } int rt_hw_timer_init(void) { - rt_uint32_t counter; + rt_uint32_t counter; #ifdef RT_USING_VMM DMTIMER = vmm_find_iomap("TIMER7"); #endif - timer_clk_init(); + timer_clk_init(); - /* soft reset the timer */ - DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1; + /* soft reset the timer */ + DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1; while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1) ; - /* calculate count */ - counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND); + /* calculate count */ + counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND); - /* set initial count */ - DMTIMER_TCRR(TIMER_HW_BASE) = counter; - /* set reload count */ - DMTIMER_TLDR(TIMER_HW_BASE) = counter; + /* set initial count */ + DMTIMER_TCRR(TIMER_HW_BASE) = counter; + /* set reload count */ + DMTIMER_TLDR(TIMER_HW_BASE) = counter; - /* set mode: auto reload */ - DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR; + /* set mode: auto reload */ + DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR; - /* interrupt enable for match */ - DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG; + /* interrupt enable for match */ + DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG; DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG; - rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_control(TINT7, 0, 0); - rt_hw_interrupt_umask(TINT7); + rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_control(TINT7, 0, 0); + rt_hw_interrupt_umask(TINT7); while (DMTIMER_TWPS(TIMER_HW_BASE) != 0) ; - /* start timer */ - DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST; + /* start timer */ + DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST; while (DMTIMER_TWPS(TIMER_HW_BASE) != 0) ; @@ -148,7 +148,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init); void rt_hw_board_init(void) { rt_components_board_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); } void rt_hw_cpu_reset(void) |