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-rw-r--r--bsp/ls1bdev/drivers/board.c78
-rw-r--r--bsp/ls1bdev/drivers/board.h4
-rw-r--r--bsp/ls1bdev/drivers/display_controller.c332
-rw-r--r--bsp/ls1bdev/drivers/display_controller.h50
-rw-r--r--bsp/ls1bdev/drivers/uart.c342
-rw-r--r--bsp/ls1bdev/drivers/uart.h120
6 files changed, 463 insertions, 463 deletions
diff --git a/bsp/ls1bdev/drivers/board.c b/bsp/ls1bdev/drivers/board.c
index 92bb2d5146..63a827be09 100644
--- a/bsp/ls1bdev/drivers/board.c
+++ b/bsp/ls1bdev/drivers/board.c
@@ -19,7 +19,7 @@
/**
* @addtogroup Loongson LS1B
*/
-
+
/*@{*/
/**
@@ -27,14 +27,14 @@
*/
void rt_hw_timer_handler(void)
{
- unsigned int count;
+ unsigned int count;
- count = read_c0_compare();
- write_c0_compare(count);
- write_c0_count(0);
+ count = read_c0_compare();
+ write_c0_compare(count);
+ write_c0_count(0);
- /* increase a OS tick */
- rt_tick_increase();
+ /* increase a OS tick */
+ rt_tick_increase();
}
/**
@@ -42,8 +42,8 @@ void rt_hw_timer_handler(void)
*/
void rt_hw_timer_init(void)
{
- write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
- write_c0_count(0);
+ write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
+ write_c0_count(0);
}
/**
@@ -52,47 +52,47 @@ void rt_hw_timer_init(void)
void rt_hw_board_init(void)
{
#ifdef RT_USING_UART
- /* init hardware UART device */
- rt_hw_uart_init();
+ /* init hardware UART device */
+ rt_hw_uart_init();
#endif
#ifdef RT_USING_CONSOLE
- /* set console device */
- rt_console_set_device("uart0");
+ /* set console device */
+ rt_console_set_device("uart0");
#endif
- /* init operating system timer */
- rt_hw_timer_init();
+ /* init operating system timer */
+ rt_hw_timer_init();
- rt_kprintf("current sr: 0x%08x\n", read_c0_status());
+ rt_kprintf("current sr: 0x%08x\n", read_c0_status());
}
#define __raw_out_put(unr) \
- while (*ptr) \
- { \
- if (*ptr == '\n') \
- { \
- /* FIFO status, contain valid data */ \
- while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
- /* write data */ \
- UART_DAT(UART##unr##_BASE) = '\r'; \
- } \
- /* FIFO status, contain valid data */ \
- while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
- /* write data */ \
- UART_DAT(UART##unr##_BASE) = *ptr; \
- ptr ++; \
- }
+ while (*ptr) \
+ { \
+ if (*ptr == '\n') \
+ { \
+ /* FIFO status, contain valid data */ \
+ while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
+ /* write data */ \
+ UART_DAT(UART##unr##_BASE) = '\r'; \
+ } \
+ /* FIFO status, contain valid data */ \
+ while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
+ /* write data */ \
+ UART_DAT(UART##unr##_BASE) = *ptr; \
+ ptr ++; \
+ }
/* UART line status register value */
-#define UARTLSR_ERROR (1 << 7)
-#define UARTLSR_TE (1 << 6)
-#define UARTLSR_TFE (1 << 5)
-#define UARTLSR_BI (1 << 4)
-#define UARTLSR_FE (1 << 3)
-#define UARTLSR_PE (1 << 2)
-#define UARTLSR_OE (1 << 1)
-#define UARTLSR_DR (1 << 0)
+#define UARTLSR_ERROR (1 << 7)
+#define UARTLSR_TE (1 << 6)
+#define UARTLSR_TFE (1 << 5)
+#define UARTLSR_BI (1 << 4)
+#define UARTLSR_FE (1 << 3)
+#define UARTLSR_PE (1 << 2)
+#define UARTLSR_OE (1 << 1)
+#define UARTLSR_DR (1 << 0)
void rt_hw_console_output(const char *ptr)
{
#if defined(RT_USING_UART0)
diff --git a/bsp/ls1bdev/drivers/board.h b/bsp/ls1bdev/drivers/board.h
index 00929788f4..d1ee3dc9a9 100644
--- a/bsp/ls1bdev/drivers/board.h
+++ b/bsp/ls1bdev/drivers/board.h
@@ -15,7 +15,7 @@
void rt_hw_board_init(void);
/* 64M SDRAM */
-#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024)
-#define CPU_HZ (125 * 1000000)
+#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024)
+#define CPU_HZ (125 * 1000000)
#endif
diff --git a/bsp/ls1bdev/drivers/display_controller.c b/bsp/ls1bdev/drivers/display_controller.c
index cc0d58e59f..5dba114b69 100644
--- a/bsp/ls1bdev/drivers/display_controller.c
+++ b/bsp/ls1bdev/drivers/display_controller.c
@@ -13,24 +13,24 @@
struct vga_struct vga_mode[] =
{
- {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, },
- {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, },
- {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, },
- {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, },
- {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, },
- {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, },
- {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, },
- {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, },
- {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, },
- {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, },
- {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, },
- {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, },
- {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, },
- {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, },
- {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, },
- {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, },
- {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, },
- {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, },
+ {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, },
+ {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, },
+ {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, },
+ {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, },
+ {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, },
+ {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, },
+ {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, },
+ {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, },
+ {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, },
+ {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, },
+ {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, },
+ {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, },
+ {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, },
+ {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, },
+ {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, },
+ {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, },
+ {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, },
+ {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, },
};
ALIGN(16)
@@ -42,189 +42,189 @@ static struct rt_device_graphic_info _dc_info;
int caclulate_freq(long long XIN, long long PCLK)
{
- int i;
- long long clk, clk1;
- int start, end;
- int mi;
- int pll,ctrl,div,div1,frac;
+ int i;
+ long long clk, clk1;
+ int start, end;
+ int mi;
+ int pll,ctrl,div,div1,frac;
- pll = PLL_FREQ;
- ctrl = PLL_DIV_PARAM;
- rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
-// rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
- start = -1;
- end = 1;
+ pll = PLL_FREQ;
+ ctrl = PLL_DIV_PARAM;
+ rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
+// rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
+ start = -1;
+ end = 1;
- for (i=start; i<=end; i++)
- {
- clk = (12+i+(pll&0x3f))*33333333/2;
- div = clk/(long)PCLK/1000;
- clk1 = (12+i+1+(pll&0x3f))*33333333/2;
- div1 = clk1/(long)PCLK/1000;
- if (div!=div1)
- break;
- }
+ for (i=start; i<=end; i++)
+ {
+ clk = (12+i+(pll&0x3f))*33333333/2;
+ div = clk/(long)PCLK/1000;
+ clk1 = (12+i+1+(pll&0x3f))*33333333/2;
+ div1 = clk1/(long)PCLK/1000;
+ if (div!=div1)
+ break;
+ }
- if (div!=div1)
- {
- frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
- pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
- ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
- }
- else
- {
- clk = (12+start+(pll&0x3f))*33333333/2;
- clk1 = (12+end+(pll&0x3f))*33333333/2;
- if (abs((long)clk/div/1000-PCLK)<abs((long)clk1/(div+1)/1000-PCLK))
- {
- pll = (pll & ~0x3ff3f)|((pll&0x3f)+start);
- ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31);
- }
- else
- {
- pll = (pll & ~0x3ff3f)|((pll&0x3f)+end);
- ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31);
- }
- }
+ if (div!=div1)
+ {
+ frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
+ pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
+ ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
+ }
+ else
+ {
+ clk = (12+start+(pll&0x3f))*33333333/2;
+ clk1 = (12+end+(pll&0x3f))*33333333/2;
+ if (abs((long)clk/div/1000-PCLK)<abs((long)clk1/(div+1)/1000-PCLK))
+ {
+ pll = (pll & ~0x3ff3f)|((pll&0x3f)+start);
+ ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31);
+ }
+ else
+ {
+ pll = (pll & ~0x3ff3f)|((pll&0x3f)+end);
+ ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31);
+ }
+ }
- rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl);
- ctrl |= 0x2a00;
- PLL_DIV_PARAM = ctrl;
- PLL_FREQ = pll;
- rt_thread_delay(10);
-// initserial(0);
-// _probe_frequencies();
-// rt_kprintf("cpu freq is %d\n",tgt_pipefreq());
- return 0;
+ rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl);
+ ctrl |= 0x2a00;
+ PLL_DIV_PARAM = ctrl;
+ PLL_FREQ = pll;
+ rt_thread_delay(10);
+// initserial(0);
+// _probe_frequencies();
+// rt_kprintf("cpu freq is %d\n",tgt_pipefreq());
+ return 0;
}
static rt_err_t rt_dc_init(rt_device_t dev)
{
- int i, out, mode=-1;
- int val;
+ int i, out, mode=-1;
+ int val;
- for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
- {
- if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
- {
- mode=i;
+ for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
+ {
+ if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
+ {
+ mode=i;
#ifdef LS1FSOC
-// out = caclulatefreq(APB_CLK/1000,vga_mode[i].pclk);
-// rt_kprintf("out=%x\n",out);
- /*inner gpu dc logic fifo pll ctrl,must large then outclk*/
-// *(volatile int *)0xbfd00414 = out+1;
- /*output pix1 clock pll ctrl*/
-// *(volatile int *)0xbfd00410 = out;
- /*output pix2 clock pll ctrl */
-// *(volatile int *)0xbfd00424 = out;
+// out = caclulatefreq(APB_CLK/1000,vga_mode[i].pclk);
+// rt_kprintf("out=%x\n",out);
+ /*inner gpu dc logic fifo pll ctrl,must large then outclk*/
+// *(volatile int *)0xbfd00414 = out+1;
+ /*output pix1 clock pll ctrl*/
+// *(volatile int *)0xbfd00410 = out;
+ /*output pix2 clock pll ctrl */
+// *(volatile int *)0xbfd00424 = out;
#else
- caclulate_freq(APB_CLK/1000, vga_mode[i].pclk);
+ caclulate_freq(APB_CLK/1000, vga_mode[i].pclk);
#endif
- break;
- }
- }
+ break;
+ }
+ }
- if (mode<0)
- {
- rt_kprintf("\n\n\nunsupported framebuffer resolution\n\n\n");
- return;
- }
+ if (mode<0)
+ {
+ rt_kprintf("\n\n\nunsupported framebuffer resolution\n\n\n");
+ return;
+ }
- DC_FB_CONFIG = 0x0;
- DC_FB_CONFIG = 0x3; // // framebuffer configuration RGB565
- DC_FB_BUFFER_ADDR0 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
- DC_FB_BUFFER_ADDR1 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
- DC_DITHER_CONFIG = 0x0;
- DC_DITHER_TABLE_LOW = 0x0;
- DC_DITHER_TABLE_HIGH = 0x0;
- DC_PANEL_CONFIG = 0x80001311;
- DC_PANEL_TIMING = 0x0;
+ DC_FB_CONFIG = 0x0;
+ DC_FB_CONFIG = 0x3; // // framebuffer configuration RGB565
+ DC_FB_BUFFER_ADDR0 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
+ DC_FB_BUFFER_ADDR1 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
+ DC_DITHER_CONFIG = 0x0;
+ DC_DITHER_TABLE_LOW = 0x0;
+ DC_DITHER_TABLE_HIGH = 0x0;
+ DC_PANEL_CONFIG = 0x80001311;
+ DC_PANEL_TIMING = 0x0;
- DC_HDISPLAY = (vga_mode[mode].hfl<<16) | vga_mode[mode].hr;
- DC_HSYNC = 0x40000000 | (vga_mode[mode].hse<<16) | vga_mode[mode].hss;
- DC_VDISPLAY = (vga_mode[mode].vfl<<16) | vga_mode[mode].vr;
- DC_VSYNC = 0x40000000 | (vga_mode[mode].vse<<16) | vga_mode[mode].vss;
+ DC_HDISPLAY = (vga_mode[mode].hfl<<16) | vga_mode[mode].hr;
+ DC_HSYNC = 0x40000000 | (vga_mode[mode].hse<<16) | vga_mode[mode].hss;
+ DC_VDISPLAY = (vga_mode[mode].vfl<<16) | vga_mode[mode].vr;
+ DC_VSYNC = 0x40000000 | (vga_mode[mode].vse<<16) | vga_mode[mode].vss;
#if defined(CONFIG_VIDEO_32BPP)
- DC_FB_CONFIG = 0x00100104;
- DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
+ DC_FB_CONFIG = 0x00100104;
+ DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
#elif defined(CONFIG_VIDEO_16BPP)
- DC_FB_CONFIG = 0x00100103;
- DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
+ DC_FB_CONFIG = 0x00100103;
+ DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
#elif defined(CONFIG_VIDEO_15BPP)
- DC_FB_CONFIG = 0x00100102;
- DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
+ DC_FB_CONFIG = 0x00100102;
+ DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
#elif defined(CONFIG_VIDEO_12BPP)
- DC_FB_CONFIG = 0x00100101;
- DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
+ DC_FB_CONFIG = 0x00100101;
+ DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
#else //640x480-32Bits
- DC_FB_CONFIG = 0x00100104;
- DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
+ DC_FB_CONFIG = 0x00100104;
+ DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
#endif //32Bits
#ifdef LS1GSOC
- /*fix ls1g dc
- *first switch to tile mode
- *change origin register to 0
- *goback nomal mode
- */
- {
- val = DC_FB_CONFIG;
- DC_FB_CONFIG = val | 0x10;
- DC_FB_BUFFER_ORIGIN = 0;
- DC_FB_BUFFER_ORIGIN;
- rt_thread_delay(10);
- DC_FB_CONFIG;
- DC_FB_CONFIG = val;
- }
+ /*fix ls1g dc
+ *first switch to tile mode
+ *change origin register to 0
+ *goback nomal mode
+ */
+ {
+ val = DC_FB_CONFIG;
+ DC_FB_CONFIG = val | 0x10;
+ DC_FB_BUFFER_ORIGIN = 0;
+ DC_FB_BUFFER_ORIGIN;
+ rt_thread_delay(10);
+ DC_FB_CONFIG;
+ DC_FB_CONFIG = val;
+ }
#endif
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_dc_control(rt_device_t dev, int cmd, void *args)
{
- switch (cmd)
- {
- case RTGRAPHIC_CTRL_RECT_UPDATE:
- break;
- case RTGRAPHIC_CTRL_POWERON:
- break;
- case RTGRAPHIC_CTRL_POWEROFF:
- break;
- case RTGRAPHIC_CTRL_GET_INFO:
- rt_memcpy(args, &_dc_info, sizeof(_dc_info));
- break;
- case RTGRAPHIC_CTRL_SET_MODE:
- break;
- }
+ switch (cmd)
+ {
+ case RTGRAPHIC_CTRL_RECT_UPDATE:
+ break;
+ case RTGRAPHIC_CTRL_POWERON:
+ break;
+ case RTGRAPHIC_CTRL_POWEROFF:
+ break;
+ case RTGRAPHIC_CTRL_GET_INFO:
+ rt_memcpy(args, &_dc_info, sizeof(_dc_info));
+ break;
+ case RTGRAPHIC_CTRL_SET_MODE:
+ break;
+ }
- return RT_EOK;
+ return RT_EOK;
}
void rt_hw_dc_init(void)
{
- rt_device_t dc = rt_malloc(sizeof(struct rt_device));
- if (dc == RT_NULL)
- {
- rt_kprintf("dc == RT_NULL\n");
- return; /* no memory yet */
- }
+ rt_device_t dc = rt_malloc(sizeof(struct rt_device));
+ if (dc == RT_NULL)
+ {
+ rt_kprintf("dc == RT_NULL\n");
+ return; /* no memory yet */
+ }
- _dc_info.bits_per_pixel = 16;
- _dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
- _dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
- _dc_info.width = FB_XSIZE;
- _dc_info.height = FB_YSIZE;
+ _dc_info.bits_per_pixel = 16;
+ _dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
+ _dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
+ _dc_info.width = FB_XSIZE;
+ _dc_info.height = FB_YSIZE;
- /* init device structure */
- dc->type = RT_Device_Class_Graphic;
- dc->init = rt_dc_init;
- dc->open = RT_NULL;
- dc->close = RT_NULL;
- dc->control = rt_dc_control;
- dc->user_data = (void*)&_dc_info;
-
- /* register Display Controller device to RT-Thread */
- rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
+ /* init device structure */
+ dc->type = RT_Device_Class_Graphic;
+ dc->init = rt_dc_init;
+ dc->open = RT_NULL;
+ dc->close = RT_NULL;
+ dc->control = rt_dc_control;
+ dc->user_data = (void*)&_dc_info;
+
+ /* register Display Controller device to RT-Thread */
+ rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
}
diff --git a/bsp/ls1bdev/drivers/display_controller.h b/bsp/ls1bdev/drivers/display_controller.h
index 671acd45a5..1fa6243a72 100644
--- a/bsp/ls1bdev/drivers/display_controller.h
+++ b/bsp/ls1bdev/drivers/display_controller.h
@@ -7,48 +7,48 @@
* Date Author Notes
* 2011-08-08 lgnq first version for LS1B
*/
-
+
#ifndef __DISPLAY_CONTROLLER_H__
#define __DISPLAY_CONTROLLER_H__
#include <rtthread.h>
#include "ls1b.h"
-#define DC_BASE 0xBC301240 //Display Controller
+#define DC_BASE 0xBC301240 //Display Controller
/* Frame Buffer registers */
-#define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
-#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
-#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
-#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
-#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
-#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
-#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
-#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
-#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
-#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
-#define DC_HSYNC __REG32(DC_BASE + 0x1E0)
-#define DC_VDISPLAY __REG32(DC_BASE + 0x240)
-#define DC_VSYNC __REG32(DC_BASE + 0x260)
-#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340)
+#define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
+#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
+#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
+#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
+#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
+#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
+#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
+#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
+#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
+#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
+#define DC_HSYNC __REG32(DC_BASE + 0x1E0)
+#define DC_VDISPLAY __REG32(DC_BASE + 0x240)
+#define DC_VSYNC __REG32(DC_BASE + 0x260)
+#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340)
/* Display Controller driver for 1024x768 16bit */
-#define FB_XSIZE 1024
-#define FB_YSIZE 768
+#define FB_XSIZE 1024
+#define FB_YSIZE 768
#define CONFIG_VIDEO_16BPP
#define APB_CLK 33333333
-#define K1BASE 0xA0000000
-#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
-#define HW_FB_ADDR KSEG1(_rt_framebuffer)
-#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2)
+#define K1BASE 0xA0000000
+#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
+#define HW_FB_ADDR KSEG1(_rt_framebuffer)
+#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2)
struct vga_struct
{
- long pclk;
- int hr,hss,hse,hfl;
- int vr,vss,vse,vfl;
+ long pclk;
+ int hr,hss,hse,hfl;
+ int vr,vss,vse,vfl;
};
#endif
diff --git a/bsp/ls1bdev/drivers/uart.c b/bsp/ls1bdev/drivers/uart.c
index deedc981c4..066acd9bcb 100644
--- a/bsp/ls1bdev/drivers/uart.c
+++ b/bsp/ls1bdev/drivers/uart.c
@@ -23,253 +23,253 @@
struct rt_uart_ls1b
{
- struct rt_device parent;
+ struct rt_device parent;
- rt_uint32_t hw_base;
- rt_uint32_t irq;
+ rt_uint32_t hw_base;
+ rt_uint32_t irq;
- /* buffer for reception */
- rt_uint8_t read_index, save_index;
- rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+ /* buffer for reception */
+ rt_uint8_t read_index, save_index;
+ rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
static void rt_uart_irqhandler(int irqno, void *param)
{
- rt_ubase_t level;
- rt_uint8_t isr;
- struct rt_uart_ls1b *uart = &uart_device;
+ rt_ubase_t level;
+ rt_uint8_t isr;
+ struct rt_uart_ls1b *uart = &uart_device;
- /* read interrupt status and clear it */
- isr = UART_IIR(uart->hw_base);
- isr = (isr >> 1) & 0x3;
+ /* read interrupt status and clear it */
+ isr = UART_IIR(uart->hw_base);
+ isr = (isr >> 1) & 0x3;
- /* receive data available */
- if (isr & 0x02)
- {
- /* Receive Data Available */
- while (UART_LSR(uart->hw_base) & UARTLSR_DR)
- {
- uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
+ /* receive data available */
+ if (isr & 0x02)
+ {
+ /* Receive Data Available */
+ while (UART_LSR(uart->hw_base) & UARTLSR_DR)
+ {
+ uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
- level = rt_hw_interrupt_disable();
- uart->save_index ++;
- if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
- uart->save_index = 0;
- rt_hw_interrupt_enable(level);
- }
+ level = rt_hw_interrupt_disable();
+ uart->save_index ++;
+ if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
+ uart->save_index = 0;
+ rt_hw_interrupt_enable(level);
+ }
- /* invoke callback */
- if (uart->parent.rx_indicate != RT_NULL)
- {
- rt_size_t length;
- if (uart->read_index > uart->save_index)
- length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
- else
- length = uart->save_index - uart->read_index;
+ /* invoke callback */
+ if (uart->parent.rx_indicate != RT_NULL)
+ {
+ rt_size_t length;
+ if (uart->read_index > uart->save_index)
+ length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
+ else
+ length = uart->save_index - uart->read_index;
- uart->parent.rx_indicate(&uart->parent, length);
- }
- }
+ uart->parent.rx_indicate(&uart->parent, length);
+ }
+ }
- return;
+ return;
}
static rt_err_t rt_uart_init(rt_device_t dev)
{
- rt_uint32_t baud_div;
- struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+ rt_uint32_t baud_div;
+ struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
- RT_ASSERT(uart != RT_NULL);
+ RT_ASSERT(uart != RT_NULL);
#if 0
- /* init UART Hardware */
- UART_IER(uart->hw_base) = 0; /* clear interrupt */
- UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
+ /* init UART Hardware */
+ UART_IER(uart->hw_base) = 0; /* clear interrupt */
+ UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
- /* enable UART clock */
- /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
- UART_LCR(uart->hw_base) = 0x3;
+ /* enable UART clock */
+ /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+ UART_LCR(uart->hw_base) = 0x3;
- /* set baudrate */
- baud_div = DEV_CLK / 16 / UART_BAUDRATE;
- UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
+ /* set baudrate */
+ baud_div = DEV_CLK / 16 / UART_BAUDRATE;
+ UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
- UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
- UART_LSB(uart->hw_base) = baud_div & 0xff;
+ UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
+ UART_LSB(uart->hw_base) = baud_div & 0xff;
- UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
+ UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
- /* Enable UART unit, enable and clear FIFO */
- UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
+ /* Enable UART unit, enable and clear FIFO */
+ UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
#endif
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
- struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+ struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
- RT_ASSERT(uart != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* Enable the UART Interrupt */
- UART_IER(uart->hw_base) |= UARTIER_IRXE;
+ RT_ASSERT(uart != RT_NULL);
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /* Enable the UART Interrupt */
+ UART_IER(uart->hw_base) |= UARTIER_IRXE;
- /* install interrupt */
- rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
- rt_hw_interrupt_umask(uart->irq);
- }
- return RT_EOK;
+ /* install interrupt */
+ rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
+ rt_hw_interrupt_umask(uart->irq);
+ }
+ return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
- struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+ struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
- RT_ASSERT(uart != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* Disable the UART Interrupt */
- UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
- }
+ RT_ASSERT(uart != RT_NULL);
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /* Disable the UART Interrupt */
+ UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
+ }
- return RT_EOK;
+ return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
- rt_uint8_t *ptr;
- struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+ rt_uint8_t *ptr;
+ struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
- RT_ASSERT(uart != RT_NULL);
+ RT_ASSERT(uart != RT_NULL);
- /* point to buffer */
- ptr = (rt_uint8_t *)buffer;
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- while (size)
- {
- /* interrupt receive */
- rt_base_t level;
+ /* point to buffer */
+ ptr = (rt_uint8_t *)buffer;
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ while (size)
+ {
+ /* interrupt receive */
+ rt_base_t level;
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
- if (uart->read_index != uart->save_index)
- {
- *ptr = uart->rx_buffer[uart->read_index];
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+ if (uart->read_index != uart->save_index)
+ {
+ *ptr = uart->rx_buffer[uart->read_index];
- uart->read_index ++;
- if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
- uart->read_index = 0;
- }
- else
- {
- /* no data in rx buffer */
+ uart->read_index ++;
+ if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+ uart->read_index = 0;
+ }
+ else
+ {
+ /* no data in rx buffer */
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- break;
- }
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ break;
+ }
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
- ptr ++;
- size --;
- }
+ ptr ++;
+ size --;
+ }
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
- }
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+ }
- return 0;
+ return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
- char *ptr;
- struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+ char *ptr;
+ struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
- RT_ASSERT(uart != RT_NULL);
+ RT_ASSERT(uart != RT_NULL);
- ptr = (char *)buffer;
+ ptr = (char *)buffer;
- if (dev->flag & RT_DEVICE_FLAG_STREAM)
- {
- /* stream mode */
- while (size)
- {
- if (*ptr == '\n')
- {
- /* FIFO status, contain valid data */
- while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
- /* write data */
- UART_DAT(uart->hw_base) = '\r';
- }
+ if (dev->flag & RT_DEVICE_FLAG_STREAM)
+ {
+ /* stream mode */
+ while (size)
+ {
+ if (*ptr == '\n')
+ {
+ /* FIFO status, contain valid data */
+ while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
+ /* write data */
+ UART_DAT(uart->hw_base) = '\r';
+ }
- /* FIFO status, contain valid data */
- while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
- /* write data */
- UART_DAT(uart->hw_base) = *ptr;
+ /* FIFO status, contain valid data */
+ while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
+ /* write data */
+ UART_DAT(uart->hw_base) = *ptr;
- ptr ++;
- size --;
- }
- }
- else
- {
- while (size != 0)
- {
- /* FIFO status, contain valid data */
- while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
+ ptr ++;
+ size --;
+ }
+ }
+ else
+ {
+ while (size != 0)
+ {
+ /* FIFO status, contain valid data */
+ while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
- /* write data */
- UART_DAT(uart->hw_base) = *ptr;
+ /* write data */
+ UART_DAT(uart->hw_base) = *ptr;
- ptr++;
- size--;
- }
- }
+ ptr++;
+ size--;
+ }
+ }
- return (rt_size_t)ptr - (rt_size_t)buffer;
+ return (rt_size_t)ptr - (rt_size_t)buffer;
}
void rt_hw_uart_init(void)
{
- struct rt_uart_ls1b *uart;
+ struct rt_uart_ls1b *uart;
- /* get uart device */
- uart = &uart_device;
+ /* get uart device */
+ uart = &uart_device;
- /* device initialization */
- uart->parent.type = RT_Device_Class_Char;
- rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
- uart->read_index = uart->save_index = 0;
+ /* device initialization */
+ uart->parent.type = RT_Device_Class_Char;
+ rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+ uart->read_index = uart->save_index = 0;
#if defined(RT_USING_UART0)
- uart->hw_base = UART0_BASE;
- uart->irq = LS1B_UART0_IRQ;
+ uart->hw_base = UART0_BASE;
+ uart->irq = LS1B_UART0_IRQ;
#elif defined(RT_USING_UART1)
- uart->hw_base = UART1_BASE;
- uart->irq = LS1B_UART1_IRQ;
+ uart->hw_base = UART1_BASE;
+ uart->irq = LS1B_UART1_IRQ;
#elif defined(RT_USING_UART3)
- uart->hw_base = UART3_BASE;
- uart->irq = LS1B_UART3_IRQ;
+ uart->hw_base = UART3_BASE;
+ uart->irq = LS1B_UART3_IRQ;
#endif
- /* device interface */
- uart->parent.init = rt_uart_init;
- uart->parent.open = rt_uart_open;
- uart->parent.close = rt_uart_close;
- uart->parent.read = rt_uart_read;
- uart->parent.write = rt_uart_write;
- uart->parent.control = RT_NULL;
- uart->parent.user_data = RT_NULL;
+ /* device interface */
+ uart->parent.init = rt_uart_init;
+ uart->parent.open = rt_uart_open;
+ uart->parent.close = rt_uart_close;
+ uart->parent.read = rt_uart_read;
+ uart->parent.write = rt_uart_write;
+ uart->parent.control = RT_NULL;
+ uart->parent.user_data = RT_NULL;
- rt_device_register(&uart->parent, "uart0",
- RT_DEVICE_FLAG_RDWR |
- RT_DEVICE_FLAG_STREAM |
- RT_DEVICE_FLAG_INT_RX);
+ rt_device_register(&uart->parent, "uart0",
+ RT_DEVICE_FLAG_RDWR |
+ RT_DEVICE_FLAG_STREAM |
+ RT_DEVICE_FLAG_INT_RX);
}
#endif /* end of UART */
diff --git a/bsp/ls1bdev/drivers/uart.h b/bsp/ls1bdev/drivers/uart.h
index 402b3eac88..0347b3db4d 100644
--- a/bsp/ls1bdev/drivers/uart.h
+++ b/bsp/ls1bdev/drivers/uart.h
@@ -13,81 +13,81 @@
#include "ls1b.h"
-#define UART0_BASE 0xBFE40000
-#define UART0_1_BASE 0xBFE41000
-#define UART0_2_BASE 0xBFE42000
-#define UART0_3_BASE 0xBFE43000
-#define UART1_BASE 0xBFE44000
-#define UART1_1_BASE 0xBFE45000
-#define UART1_2_BASE 0xBFE46000
-#define UART1_3_BASE 0xBFE47000
-#define UART2_BASE 0xBFE48000
-#define UART3_BASE 0xBFE4C000
-#define UART4_BASE 0xBFE6C000
-#define UART5_BASE 0xBFE7C000
+#define UART0_BASE 0xBFE40000
+#define UART0_1_BASE 0xBFE41000
+#define UART0_2_BASE 0xBFE42000
+#define UART0_3_BASE 0xBFE43000
+#define UART1_BASE 0xBFE44000
+#define UART1_1_BASE 0xBFE45000
+#define UART1_2_BASE 0xBFE46000
+#define UART1_3_BASE 0xBFE47000
+#define UART2_BASE 0xBFE48000
+#define UART3_BASE 0xBFE4C000
+#define UART4_BASE 0xBFE6C000
+#define UART5_BASE 0xBFE7C000
/* UART registers */
-#define UART_DAT(base) __REG8(base + 0x00)
-#define UART_IER(base) __REG8(base + 0x01)
-#define UART_IIR(base) __REG8(base + 0x02)
-#define UART_FCR(base) __REG8(base + 0x02)
-#define UART_LCR(base) __REG8(base + 0x03)
-#define UART_MCR(base) __REG8(base + 0x04)
-#define UART_LSR(base) __REG8(base + 0x05)
-#define UART_MSR(base) __REG8(base + 0x06)
+#define UART_DAT(base) __REG8(base + 0x00)
+#define UART_IER(base) __REG8(base + 0x01)
+#define UART_IIR(base) __REG8(base + 0x02)
+#define UART_FCR(base) __REG8(base + 0x02)
+#define UART_LCR(base) __REG8(base + 0x03)
+#define UART_MCR(base) __REG8(base + 0x04)
+#define UART_LSR(base) __REG8(base + 0x05)
+#define UART_MSR(base) __REG8(base + 0x06)
-#define UART_LSB(base) __REG8(base + 0x00)
-#define UART_MSB(base) __REG8(base + 0x01)
+#define UART_LSB(base) __REG8(base + 0x00)
+#define UART_MSB(base) __REG8(base + 0x01)
/* UART0 registers */
-#define UART0_DAT __REG8(UART0_BASE + 0x00)
-#define UART0_IER __REG8(UART0_BASE + 0x01)
-#define UART0_IIR __REG8(UART0_BASE + 0x02)
-#define UART0_FCR __REG8(UART0_BASE + 0x02)
-#define UART0_LCR __REG8(UART0_BASE + 0x03)
-#define UART0_MCR __REG8(UART0_BASE + 0x04)
-#define UART0_LSR __REG8(UART0_BASE + 0x05)
-#define UART0_MSR __REG8(UART0_BASE + 0x06)
+#define UART0_DAT __REG8(UART0_BASE + 0x00)
+#define UART0_IER __REG8(UART0_BASE + 0x01)
+#define UART0_IIR __REG8(UART0_BASE + 0x02)
+#define UART0_FCR __REG8(UART0_BASE + 0x02)
+#define UART0_LCR __REG8(UART0_BASE + 0x03)
+#define UART0_MCR __REG8(UART0_BASE + 0x04)
+#define UART0_LSR __REG8(UART0_BASE + 0x05)
+#define UART0_MSR __REG8(UART0_BASE + 0x06)
-#define UART0_LSB __REG8(UART0_BASE + 0x00)
-#define UART0_MSB __REG8(UART0_BASE + 0x01)
+#define UART0_LSB __REG8(UART0_BASE + 0x00)
+#define UART0_MSB __REG8(UART0_BASE + 0x01)
/* UART1 registers */
-#define UART1_DAT __REG8(UART1_BASE + 0x00)
-#define UART1_IER __REG8(UART1_BASE + 0x01)
-#define UART1_IIR __REG8(UART1_BASE + 0x02)
-#define UART1_FCR __REG8(UART1_BASE + 0x02)
-#define UART1_LCR __REG8(UART1_BASE + 0x03)
-#define UART1_MCR __REG8(UART1_BASE + 0x04)
-#define UART1_LSR __REG8(UART1_BASE + 0x05)
-#define UART1_MSR __REG8(UART1_BASE + 0x06)
+#define UART1_DAT __REG8(UART1_BASE + 0x00)
+#define UART1_IER __REG8(UART1_BASE + 0x01)
+#define UART1_IIR __REG8(UART1_BASE + 0x02)
+#define UART1_FCR __REG8(UART1_BASE + 0x02)
+#define UART1_LCR __REG8(UART1_BASE + 0x03)
+#define UART1_MCR __REG8(UART1_BASE + 0x04)
+#define UART1_LSR __REG8(UART1_BASE + 0x05)
+#define UART1_MSR __REG8(UART1_BASE + 0x06)
-#define UART1_LSB __REG8(UART1_BASE + 0x00)
-#define UART1_MSB __REG8(UART1_BASE + 0x01)
+#define UART1_LSB __REG8(UART1_BASE + 0x00)
+#define UART1_MSB __REG8(UART1_BASE + 0x01)
/* UART interrupt enable register value */
-#define UARTIER_IME (1 << 3)
-#define UARTIER_ILE (1 << 2)
-#define UARTIER_ITXE (1 << 1)
-#define UARTIER_IRXE (1 << 0)
+#define UARTIER_IME (1 << 3)
+#define UARTIER_ILE (1 << 2)
+#define UARTIER_ITXE (1 << 1)
+#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
-#define UARTLCR_DLAB (1 << 7)
-#define UARTLCR_BCB (1 << 6)
-#define UARTLCR_SPB (1 << 5)
-#define UARTLCR_EPS (1 << 4)
-#define UARTLCR_PE (1 << 3)
-#define UARTLCR_SB (1 << 2)
+#define UARTLCR_DLAB (1 << 7)
+#define UARTLCR_BCB (1 << 6)
+#define UARTLCR_SPB (1 << 5)
+#define UARTLCR_EPS (1 << 4)
+#define UARTLCR_PE (1 << 3)
+#define UARTLCR_SB (1 << 2)
/* UART line status register value */
-#define UARTLSR_ERROR (1 << 7)
-#define UARTLSR_TE (1 << 6)
-#define UARTLSR_TFE (1 << 5)
-#define UARTLSR_BI (1 << 4)
-#define UARTLSR_FE (1 << 3)
-#define UARTLSR_PE (1 << 2)
-#define UARTLSR_OE (1 << 1)
-#define UARTLSR_DR (1 << 0)
+#define UARTLSR_ERROR (1 << 7)
+#define UARTLSR_TE (1 << 6)
+#define UARTLSR_TFE (1 << 5)
+#define UARTLSR_BI (1 << 4)
+#define UARTLSR_FE (1 << 3)
+#define UARTLSR_PE (1 << 2)
+#define UARTLSR_OE (1 << 1)
+#define UARTLSR_DR (1 << 0)
void rt_hw_uart_init(void);
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-23 23:13:25 +0000