diff options
Diffstat (limited to 'bsp/ls1cdev/drivers/net/synopGMAC_Dev.h')
| -rw-r--r-- | bsp/ls1cdev/drivers/net/synopGMAC_Dev.h | 1268 |
1 files changed, 634 insertions, 634 deletions
diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h index 74bc850d86..9c1d9869e4 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,9 +8,9 @@ * 2017-08-24 chinesebear first version */ - -#define UNUSED 1 - + +#define UNUSED 1 + #ifndef SYNOP_GMAC_DEV_H #define SYNOP_GMAC_DEV_H 1 @@ -31,41 +31,41 @@ #include "synopGMAC_plat.h" #include "synopGMAC_types.h" -//sw: typedef are included in synopGMAC_plat.h -// it is strange that we should add it here again!! +//sw: typedef are included in synopGMAC_plat.h +// it is strange that we should add it here again!! /*SynopGMAC can support up to 32 phys*/ #define GMAC_PHY_BASE 1 #ifdef GMAC_PHY_BASE #define DEFAULT_PHY_BASE GMAC_PHY_BASE #else -#define DEFAULT_PHY_BASE PHY16 //We use First Phy +#define DEFAULT_PHY_BASE PHY16 //We use First Phy #endif -#define MACBASE 0x0000 // The Mac Base address offset is 0x0000 -#define DMABASE 0x1000 // Dma base address starts with an offset 0x1000 +#define MACBASE 0x0000 // The Mac Base address offset is 0x0000 +#define DMABASE 0x1000 // Dma base address starts with an offset 0x1000 enum GMACPhyBase { - PHY0 = 0, //The device can support 32 phys, but we use first phy only - PHY1 = 1, - PHY16 = 16, - PHY31 = 31, + PHY0 = 0, //The device can support 32 phys, but we use first phy only + PHY1 = 1, + PHY16 = 16, + PHY31 = 31, }; -//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue -//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue -//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue -#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue -#define RECEIVE_DESC_SIZE 72 //96 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue +//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue +#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue +#define RECEIVE_DESC_SIZE 72 //96 //Rx Descriptors needed in the Descriptor pool/queue -#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type -#define ETHERNET_CRC 4 //Ethernet CRC -#define ETHERNET_EXTRA 2 //Only God knows about this????? -#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb -#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA -#define VLAN_TAG 4 //optional 802.1q VLAN Tag +#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type +#define ETHERNET_CRC 4 //Ethernet CRC +#define ETHERNET_EXTRA 2 //Only God knows about this????? +#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb +#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA +#define VLAN_TAG 4 //optional 802.1q VLAN Tag #define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size #define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size #define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size @@ -84,80 +84,80 @@ The descriptor is of 4 words, but our structrue contains 6 words where last two words are to hold the virtual address of the network buffer pointers for driver's use From the GMAC core release 3.50a onwards, the Enhanced Descriptor structure got changed. -The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal +The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal descriptor structure. Whenever IEEE 1588 Timestamping is enabled TX/RX DESC6 provides the lower 32 bits of Timestamp value and TX/RX DESC7 provides the upper 32 bits of Timestamp value In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DESC4 contains the extended status information */ -#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for - // descriptor whose index%MODULO_INTERRUPT is zero +#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for + // descriptor whose index%MODULO_INTERRUPT is zero #ifdef ENH_DESC_8W -typedef struct DmaDescStruct -{ - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ - /* This data below is used only by driver */ +typedef struct DmaDescStruct +{ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ u32 extstatus; /* Extended status of a Rx Descriptor */ u32 reserved1; /* Reserved word */ u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */ u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */ - u32 data1; /* This holds virtual address of buffer1, not used by DMA */ - u32 data2; /* This holds virtual address of buffer2, not used by DMA */ + u32 data1; /* This holds virtual address of buffer1, not used by DMA */ + u32 data2; /* This holds virtual address of buffer2, not used by DMA */ } DmaDesc; #else -typedef struct DmaDescStruct -{ - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ - /* This data below is used only by driver */ - u32 data1; /* This holds virtual address of buffer1, not used by DMA */ - u32 data2; /* This holds virtual address of buffer2, not used by DMA */ +typedef struct DmaDescStruct +{ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ + u32 data1; /* This holds virtual address of buffer1, not used by DMA */ + u32 data2; /* This holds virtual address of buffer2, not used by DMA */ - u32 dummy1; //sw: for addr align - u32 dummy2; // + u32 dummy1; //sw: for addr align + u32 dummy2; // } DmaDesc; #endif enum DescMode { - RINGMODE = 0x00000001, - CHAINMODE = 0x00000002, + RINGMODE = 0x00000001, + CHAINMODE = 0x00000002, }; enum BufferMode { - SINGLEBUF = 0x00000001, - DUALBUF = 0x00000002, + SINGLEBUF = 0x00000001, + DUALBUF = 0x00000002, }; /* synopGMAC device data */ -typedef struct synopGMACDeviceStruct +typedef struct synopGMACDeviceStruct { - u32 MacBase; /* base address of MAC registers */ - u32 DmaBase; /* base address of DMA registers */ - u32 PhyBase; /* PHY device address on MII interface */ - u32 Version; /* Gmac Revision version */ - + u32 MacBase; /* base address of MAC registers */ + u32 DmaBase; /* base address of DMA registers */ + u32 PhyBase; /* PHY device address on MII interface */ + u32 Version; /* Gmac Revision version */ + - dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ - dma_addr_t RxDescDma; /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ + dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ + dma_addr_t RxDescDma; /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ - u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ - u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ - + u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ + u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ + u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ - + u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ @@ -169,14 +169,14 @@ typedef struct synopGMACDeviceStruct DmaDesc * RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */ /*Phy related stuff*/ - u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ + u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ /* The status of the link */ - u32 LinkState0; /* Link status as reported by the Marvel Phy */ - u32 LinkState; /* Link status as reported by the Marvel Phy */ - u32 DuplexMode; /* Duplex mode of the Phy */ - u32 Speed; /* Speed of the Phy */ - u32 LoopBackMode; /* Loopback status of the Phy */ - + u32 LinkState0; /* Link status as reported by the Marvel Phy */ + u32 LinkState; /* Link status as reported by the Marvel Phy */ + u32 DuplexMode; /* Duplex mode of the Phy */ + u32 Speed; /* Speed of the Phy */ + u32 LoopBackMode; /* Loopback status of the Phy */ + // void * FirstTxDesc; // void * FirstRxDesc; // u32 skb_array[RECEIVE_DESC_SIZE]; @@ -184,36 +184,36 @@ typedef struct synopGMACDeviceStruct -/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" +/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter. * Since the Phy register map is standard, this map hardly changes to a different Ppy */ enum MiiRegisters { - PHY_CONTROL_REG = 0x0000, /*Control Register*/ - PHY_STATUS_REG = 0x0001, /*Status Register */ - PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ - PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ - PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ - PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ - PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ - PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ - PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ - PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ - PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ - PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ - PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ - PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ - PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ - PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ - PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ - PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ - PHY_LED_CONTROL = 0x0018, /*LED Control*/ - PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ - PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ - PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ - PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ + PHY_CONTROL_REG = 0x0000, /*Control Register*/ + PHY_STATUS_REG = 0x0001, /*Status Register */ + PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ + PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ + PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ + PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ + PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ + PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ + PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ + PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ + PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ + PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ + PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ + PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ + PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ + PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ + PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ + PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ + PHY_LED_CONTROL = 0x0018, /*LED Control*/ + PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ + PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ + PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ + PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ }; @@ -221,62 +221,62 @@ enum MiiRegisters */ enum Mii_GEN_CTRL -{ /* Description bits R/W default value */ - Mii_reset = 0x8000, - Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ - Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ - Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ +{ /* Description bits R/W default value */ + Mii_reset = 0x8000, + Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ + Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ + Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ + + Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ - Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ - - Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ - - Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ - Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ + Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ + + Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ + Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ }; enum Mii_Phy_Status { - Mii_phy_status_speed_10 = 0x0000, - Mii_phy_status_speed_100 = 0x4000, - Mii_phy_status_speed_1000 = 0x8000, - - Mii_phy_status_full_duplex = 0x2000, - Mii_phy_status_half_duplex = 0x0000, - - Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy -// Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY + Mii_phy_status_speed_10 = 0x0000, + Mii_phy_status_speed_100 = 0x4000, + Mii_phy_status_speed_1000 = 0x8000, + + Mii_phy_status_full_duplex = 0x2000, + Mii_phy_status_half_duplex = 0x0000, + + Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy +// Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY }; /* This is Status register layout. Status register is of 16 bit wide. */ enum Mii_GEN_STATUS { - Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ - Mii_Link = 0x0004, /* Link status 2 RW */ + Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ + Mii_Link = 0x0004, /* Link status 2 RW */ }; enum Mii_Link_Status { - LINKDOWN = 0, - LINKUP = 1, + LINKDOWN = 0, + LINKUP = 1, }; enum Mii_Duplex_Mode { - HALFDUPLEX = 1, - FULLDUPLEX = 2, + HALFDUPLEX = 1, + FULLDUPLEX = 2, }; enum Mii_Link_Speed { - SPEED10 = 1, - SPEED100 = 2, - SPEED1000 = 3, + SPEED10 = 1, + SPEED100 = 2, + SPEED1000 = 3, }; enum Mii_Loop_Back { - NOLOOPBACK = 0, - LOOPBACK = 1, + NOLOOPBACK = 0, + LOOPBACK = 1, }; @@ -286,107 +286,107 @@ enum Mii_Loop_Back * For Pci based system address is BARx + GmacRegisterBase * For any other system translation is done accordingly **********************************************************/ -enum GmacRegisters +enum GmacRegisters { - GmacConfig = 0x0000, /* Mac config Register */ - GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ - GmacHashHigh = 0x0008, /* Multi-cast hash table high */ - GmacHashLow = 0x000C, /* Multi-cast hash table low */ - GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ - GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ - GmacFlowControl = 0x0018, /* Flow control Register */ - GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ - - GmacVersion = 0x0020, /* GMAC Core Version Register */ - GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ - GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ - - GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ - GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ - - GmacAddr0High = 0x0040, /* Mac address0 high Register */ - GmacAddr0Low = 0x0044, /* Mac address0 low Register */ - GmacAddr1High = 0x0048, /* Mac address1 high Register */ - GmacAddr1Low = 0x004C, /* Mac address1 low Register */ - GmacAddr2High = 0x0050, /* Mac address2 high Register */ - GmacAddr2Low = 0x0054, /* Mac address2 low Register */ - GmacAddr3High = 0x0058, /* Mac address3 high Register */ - GmacAddr3Low = 0x005C, /* Mac address3 low Register */ - GmacAddr4High = 0x0060, /* Mac address4 high Register */ - GmacAddr4Low = 0x0064, /* Mac address4 low Register */ - GmacAddr5High = 0x0068, /* Mac address5 high Register */ - GmacAddr5Low = 0x006C, /* Mac address5 low Register */ - GmacAddr6High = 0x0070, /* Mac address6 high Register */ - GmacAddr6Low = 0x0074, /* Mac address6 low Register */ - GmacAddr7High = 0x0078, /* Mac address7 high Register */ - GmacAddr7Low = 0x007C, /* Mac address7 low Register */ - GmacAddr8High = 0x0080, /* Mac address8 high Register */ - GmacAddr8Low = 0x0084, /* Mac address8 low Register */ - GmacAddr9High = 0x0088, /* Mac address9 high Register */ - GmacAddr9Low = 0x008C, /* Mac address9 low Register */ + GmacConfig = 0x0000, /* Mac config Register */ + GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ + GmacHashHigh = 0x0008, /* Multi-cast hash table high */ + GmacHashLow = 0x000C, /* Multi-cast hash table low */ + GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ + GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ + GmacFlowControl = 0x0018, /* Flow control Register */ + GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ + + GmacVersion = 0x0020, /* GMAC Core Version Register */ + GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ + GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ + + GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ + GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ + + GmacAddr0High = 0x0040, /* Mac address0 high Register */ + GmacAddr0Low = 0x0044, /* Mac address0 low Register */ + GmacAddr1High = 0x0048, /* Mac address1 high Register */ + GmacAddr1Low = 0x004C, /* Mac address1 low Register */ + GmacAddr2High = 0x0050, /* Mac address2 high Register */ + GmacAddr2Low = 0x0054, /* Mac address2 low Register */ + GmacAddr3High = 0x0058, /* Mac address3 high Register */ + GmacAddr3Low = 0x005C, /* Mac address3 low Register */ + GmacAddr4High = 0x0060, /* Mac address4 high Register */ + GmacAddr4Low = 0x0064, /* Mac address4 low Register */ + GmacAddr5High = 0x0068, /* Mac address5 high Register */ + GmacAddr5Low = 0x006C, /* Mac address5 low Register */ + GmacAddr6High = 0x0070, /* Mac address6 high Register */ + GmacAddr6Low = 0x0074, /* Mac address6 low Register */ + GmacAddr7High = 0x0078, /* Mac address7 high Register */ + GmacAddr7Low = 0x007C, /* Mac address7 low Register */ + GmacAddr8High = 0x0080, /* Mac address8 high Register */ + GmacAddr8Low = 0x0084, /* Mac address8 low Register */ + GmacAddr9High = 0x0088, /* Mac address9 high Register */ + GmacAddr9Low = 0x008C, /* Mac address9 low Register */ GmacAddr10High = 0x0090, /* Mac address10 high Register */ - GmacAddr10Low = 0x0094, /* Mac address10 low Register */ - GmacAddr11High = 0x0098, /* Mac address11 high Register */ - GmacAddr11Low = 0x009C, /* Mac address11 low Register */ - GmacAddr12High = 0x00A0, /* Mac address12 high Register */ - GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ - GmacAddr13High = 0x00A8, /* Mac address13 high Register */ - GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ - GmacAddr14High = 0x00B0, /* Mac address14 high Register */ - GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ - GmacAddr15High = 0x00B8, /* Mac address15 high Register */ - GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ + GmacAddr10Low = 0x0094, /* Mac address10 low Register */ + GmacAddr11High = 0x0098, /* Mac address11 high Register */ + GmacAddr11Low = 0x009C, /* Mac address11 low Register */ + GmacAddr12High = 0x00A0, /* Mac address12 high Register */ + GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ + GmacAddr13High = 0x00A8, /* Mac address13 high Register */ + GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ + GmacAddr14High = 0x00B0, /* Mac address14 high Register */ + GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ + GmacAddr15High = 0x00B8, /* Mac address15 high Register */ + GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ GmacStatus = 0x00d8, /*MAC status*/ /*Time Stamp Register Map*/ - GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ + GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ - GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ - + GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ - - GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ //GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ - + GmacTSStatus = 0x0728, /* Time Stamp Status Register */ }; /********************************************************** * GMAC Network interface registers * This explains the Register's Layout - - * FES is Read only by default and is enabled only when Tx + + * FES is Read only by default and is enabled only when Tx * Config Parameter is enabled for RGMII/SGMII interface * during CoreKit Config. - + * DM is Read only with value 1'b1 in Full duplex only Config **********************************************************/ /* GmacConfig = 0x0000, Mac config Register Layout */ -enum GmacConfigReg -{ +enum GmacConfigReg +{ /* Bit description Bits R/W Reset value */ - GmacWatchdog = 0x00800000, + GmacWatchdog = 0x00800000, GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */ - GmacJabber = 0x00400000, + GmacJabber = 0x00400000, GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */ GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */ GmacFrameBurst = 0x00200000, GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ - + GmacJumboFrame = 0x00100000, GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ @@ -399,69 +399,69 @@ enum GmacConfigReg GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ - - GmacDisableCrs = 0x00010000, - GmacMiiGmii = 0x00008000, + + GmacDisableCrs = 0x00010000, + GmacMiiGmii = 0x00008000, GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ GmacSelectGmii = 0x00000000, /* GMII mode 0 */ - GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ - GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ + GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ + GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ - GmacRxOwn = 0x00002000, + GmacRxOwn = 0x00002000, GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ - - GmacLoopback = 0x00001000, + + GmacLoopback = 0x00001000, GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ - GmacDuplex = 0x00000800, + GmacDuplex = 0x00000800, GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */ GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */ - GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ + GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ - GmacRetry = 0x00000200, + GmacRetry = 0x00000200, GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ - GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ - GmacLinkDown = 0x00000100, /* Link Down 0 */ - - GmacPadCrcStrip = 0x00000080, + GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ + GmacLinkDown = 0x00000100, /* Link Down 0 */ + + GmacPadCrcStrip = 0x00000080, GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ - - GmacBackoffLimit = 0x00000060, + + GmacBackoffLimit = 0x00000060, GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ GmacBackoffLimit2 = 0x00000040, /* */ GmacBackoffLimit1 = 0x00000020, /* */ GmacBackoffLimit0 = 0x00000000, /* 00 */ - GmacDeferralCheck = 0x00000010, + GmacDeferralCheck = 0x00000010, GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ - - GmacTx = 0x00000008, + + GmacTx = 0x00000008, GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ - GmacRx = 0x00000004, + GmacRx = 0x00000004, GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */ GmacRxDisable = 0x00000000, /* Receiver disable 0 */ }; /* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/ -enum GmacFrameFilterReg +enum GmacFrameFilterReg { - GmacFilter = 0x80000000, + GmacFilter = 0x80000000, GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */ - GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ + GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ - GmacSrcAddrFilter = 0x00000200, + GmacSrcAddrFilter = 0x00000200, GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */ GmacSrcAddrFilterDisable = 0x00000000, /* 0 */ @@ -469,13 +469,13 @@ enum GmacFrameFilterReg GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */ GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */ - GmacPassControl = 0x000000C0, + GmacPassControl = 0x000000C0, GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */ GmacPassControl2 = 0x00000080, /* Forwards all control frames */ GmacPassControl1 = 0x00000040, /* Does not pass control frames */ GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */ - GmacBroadcast = 0x00000020, + GmacBroadcast = 0x00000020, GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */ GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */ @@ -500,17 +500,17 @@ enum GmacFrameFilterReg GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */ }; - + /*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */ -enum GmacGmiiAddrReg +enum GmacGmiiAddrReg { GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ GmiiDevShift = 11, GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ GmiiRegShift = 6, - - GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ + + GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ @@ -525,19 +525,19 @@ enum GmacGmiiAddrReg }; /* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */ -enum GmacGmiiDataReg +enum GmacGmiiDataReg { GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ }; /*GmacFlowControl = 0x0018, Flow control Register Layout */ -enum GmacFlowControlReg -{ +enum GmacFlowControlReg +{ GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ GmacPauseTimeShift = 16, - - GmacPauseLowThresh = 0x00000030, + + GmacPauseLowThresh = 0x00000030, GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */ @@ -547,11 +547,11 @@ enum GmacFlowControlReg GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */ GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */ - GmacRxFlowControl = 0x00000004, + GmacRxFlowControl = 0x00000004, GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */ GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */ - GmacTxFlowControl = 0x00000002, + GmacTxFlowControl = 0x00000002, GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */ GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */ @@ -559,29 +559,29 @@ enum GmacFlowControlReg GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ }; -/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ +/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ enum GmacInterruptStatusBitDefinition { - GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ - GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ - GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ - GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ - GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ - GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ - GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ - GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ - GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ + GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ + GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ + GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ + GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ + GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ + GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ + GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ + GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ + GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ }; -/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ +/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ enum GmacInterruptMaskBitDefinition { - GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ - GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ - GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ - GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ - GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ + GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ + GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ + GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ + GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ + GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ }; /********************************************************** @@ -590,7 +590,7 @@ enum GmacInterruptMaskBitDefinition * For any other system translation is done accordingly **********************************************************/ -enum DmaRegisters +enum DmaRegisters { DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ @@ -601,8 +601,8 @@ enum DmaRegisters DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ - DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ - DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ + DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ + DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ }; @@ -612,19 +612,19 @@ enum DmaRegisters **********************************************************/ /*DmaBusMode = 0x0000, CSR0 - Bus Mode */ -enum DmaBusModeReg +enum DmaBusModeReg { /* Bit description Bits R/W Reset value */ DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ - DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ - DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ - DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ - DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ - - DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ - - DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ + DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ + DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ + DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ + DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ + + DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ + + DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ @@ -645,20 +645,20 @@ enum DmaBusModeReg DmaDescriptorSkip1 = 0x00000004, /* */ DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ - DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ - DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ - + DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ + DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ + DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ DmaResetOff = 0x00000000, /* 0 */ }; /*DmaStatus = 0x0014, CSR5 - Dma status Register */ -enum DmaStatusReg -{ - /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ - GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ - GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ +enum DmaStatusReg +{ + /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ + GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ + GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ @@ -700,52 +700,52 @@ enum DmaStatusReg }; /*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */ -enum DmaControlReg -{ - DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ - +enum DmaControlReg +{ + DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ + DmaStoreAndForward = 0x02200000, /* (SF)Store and forward 21 RW 0 */ - DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ - - DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ - DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ - DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ - DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ - DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ - DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ - DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ - DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ - DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ - + DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ + + DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ + DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ + DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ + DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ + DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ + DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ + DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ + DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ + DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ + DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ - DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ - DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ - DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - - DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ - DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ - DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct4K = 0x00000300, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ - - DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ - DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ - DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ - DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ - DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ + DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ + DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + + DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ + DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ + DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct4K = 0x00000300, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ + + DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ + DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ + DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ + DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ + DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + + DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ + DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ - DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ - DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ - DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ @@ -755,7 +755,7 @@ enum DmaControlReg /*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */ enum DmaInterruptReg -{ +{ DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */ DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */ @@ -783,34 +783,34 @@ enum DmaInterruptReg #ifdef ENH_DESC /* **********Enhanced Descritpor structure to support 8K buffer per buffer **************************** - -DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address + +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a -32 bit Data bus is as shown below +32 bit Data bus is as shown below -Similarly +Similarly DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a 32 bit Data bus is as shown below -------------------------------------------------------------------------- - RDES0 |OWN (31)| Status | - -------------------------------------------------------------------------- - RDES1 | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1 | - -------------------------------------------------------------------------- - RDES2 | Buffer 1 Address | - -------------------------------------------------------------------------- - RDES3 | Buffer 2 Address / Next Descriptor Address | - -------------------------------------------------------------------------- + RDES0 |OWN (31)| Status | + -------------------------------------------------------------------------- + RDES1 | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + RDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- + RDES3 | Buffer 2 Address / Next Descriptor Address | + -------------------------------------------------------------------------- -------------------------------------------------------------------------- - TDES0 |OWN (31)| Ctrl | Res | Ctrl | Res | Status | - -------------------------------------------------------------------------- - TDES1 | Res | Byte Count Buffer 2 | Res | Byte Count Buffer 1 | - -------------------------------------------------------------------------- - TDES2 | Buffer 1 Address | - -------------------------------------------------------------------------- + TDES0 |OWN (31)| Ctrl | Res | Ctrl | Res | Status | + -------------------------------------------------------------------------- + TDES1 | Res | Byte Count Buffer 2 | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + TDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- TDES3 | Buffer 2 Address / Next Descriptor Address | - -------------------------------------------------------------------------- + -------------------------------------------------------------------------- */ @@ -819,15 +819,15 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ DescFrameLengthShift = 16, DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ - /* DE || OE || IPC || LC || RWT || RE || CE */ + /* DE || OE || IPC || LC || RWT || RE || CE */ DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ @@ -839,31 +839,31 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ -// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ +// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + + DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */ - DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ + DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ - DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ - - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - - DescRxTSavail = 0x00000080, /* Time stamp available 7 */ - DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescRxTSavail = 0x00000080, /* Time stamp available 7 */ + DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ @@ -874,25 +874,25 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ DescTxCollShift = 3, - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ - /* - This explains the RDES1/TDES1 bits layout - -------------------------------------------------------------------- - RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | - -------------------------------------------------------------------- + /* + This explains the RDES1/TDES1 bits layout + -------------------------------------------------------------------- + RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | + -------------------------------------------------------------------- - */ -// DmaDescriptorLength length word of DMA descriptor + */ +// DmaDescriptorLength length word of DMA descriptor - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ @@ -903,12 +903,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescSize1Shift = 0, - /* - This explains the RDES4 Extended Status bits layout - -------------------------------------------------------------------- - RDES4 | Extended Status | - -------------------------------------------------------------------- - */ + /* + This explains the RDES4 Extended Status bits layout + -------------------------------------------------------------------- + RDES4 | Extended Status | + -------------------------------------------------------------------- + */ DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */ DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */ DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */ @@ -923,12 +923,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ - + DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 is bypassed */ DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 - error or IP datagram version is not consistent + error or IP datagram version is not consistent with Ethernet type value */ DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 in IPdatagram processed by COE (Rx) */ @@ -943,38 +943,38 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ /* ********** Default Descritpor structure **************************** -DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a -32 bit Data bus is as shown below +32 bit Data bus is as shown below -Similarly +Similarly DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a 32 bit Data bus is as shown below -------------------------------------------------------------------- RDES0/TDES0 |OWN (31)| Status | - -------------------------------------------------------------------- + -------------------------------------------------------------------- RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | - -------------------------------------------------------------------- + -------------------------------------------------------------------- RDES2/TDES2 | Buffer 1 Address | - -------------------------------------------------------------------- + -------------------------------------------------------------------- RDES3/TDES3 | Buffer 2 Address / Next Descriptor Address | - -------------------------------------------------------------------- + -------------------------------------------------------------------- */ enum DmaDescriptorStatus /* status word of DMA descriptor */ { DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ DescFrameLengthShift = 16, DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ - /* DE || OE || IPC || LC || RWT || RE || CE */ + /* DE || OE || IPC || LC || RWT || RE || CE */ DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ @@ -986,16 +986,16 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ - DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ //Rx Descriptor Checksum Offload engine (type 2) encoding - //DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ + //DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ //DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - + + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ @@ -1005,21 +1005,21 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ DescTxCollShift = 3, - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ - - /* - This explains the RDES1/TDES1 bits layout - -------------------------------------------------------------------- - RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | - -------------------------------------------------------------------- - */ + /* + This explains the RDES1/TDES1 bits layout + -------------------------------------------------------------------- + RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | + -------------------------------------------------------------------- + + */ //DmaDescriptorLength length word of DMA descriptor DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */ @@ -1027,46 +1027,46 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxFirst = 0x20000000, /* (FS)Tx - First segment of the frame 29 */ DescTxDisableCrc = 0x04000000, /* (DC)Tx - Add CRC disabled (first segment only) 26 */ - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ RxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ RxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - - DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ + + DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ TxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ TxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - + DescSize2Mask = 0x003FF800, /* (TBS2) Buffer 2 size 21:11 */ DescSize2Shift = 11, DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */ DescSize1Shift = 0, - DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ }; #endif // Rx Descriptor COE type2 encoding enum RxDescCOEEncode { - RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ - RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ - RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ - RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ - RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ - RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ - RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ - RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ + RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ + RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ + RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ + RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ + RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ + RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ + RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ + RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ }; /********************************************************** * DMA engine interrupt handling functions **********************************************************/ - + enum synopGMACDmaIntEnum /* Intrerrupt types */ { synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ @@ -1089,7 +1089,7 @@ enum InitialRegisters | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, - + /* Full-duplex mode with perfect filter on */ GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff @@ -1097,13 +1097,13 @@ enum InitialRegisters | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode */ - // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast - // Hash filter. + // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast + // Hash filter. /* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */ GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff | GmacPromiscuousModeOff | GmacUcastHashFilterOff, - + /* Full-duplex mode */ GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, @@ -1112,17 +1112,17 @@ enum InitialRegisters /* Half-duplex mode with perfect filter on */ - // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, + // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, /*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/ GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode with perfect filter on */ GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode */ @@ -1144,13 +1144,13 @@ enum InitialRegisters DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip2 | DmaResetOff, // DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff, - + /* 1000 Mb/s mode */ DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , /* 100 Mb/s mode */ DmaControlInit100 = DmaStoreAndForward, - + /* 10 Mb/s mode */ DmaControlInit10 = DmaStoreAndForward, @@ -1178,191 +1178,191 @@ enum InitialRegisters enum MMC_ENABLE { - GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ - GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ - GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ - GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ - GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ + GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ + GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ + GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ + GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ + GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ }; enum MMC_TX { - GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ - GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ - GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ - - GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - - GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ - GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ - GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ - GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ - GmacMmcTxSingleColG = 0x014C, /*Successfully Tx Frames after singel collision in Half duplex mode */ - GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ - GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ - GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ - GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ - GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ - GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ - GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ - GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ - - GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ - GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ + GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ + GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ + GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ + + GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ + GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + + GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ + GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ + GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ + GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ + GmacMmcTxSingleColG = 0x014C, /*Successfully Tx Frames after singel collision in Half duplex mode */ + GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ + GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ + GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ + GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ + GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ + GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ + GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ + GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ + + GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ + GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ }; enum MMC_RX { - GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ - GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ - GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ - GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ - - GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ - GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ - GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ - GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ - GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ - GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ - - GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - - GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ - GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ - GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ - - GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ - GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ - GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ - - GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ + GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ + GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ + GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ + GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ + + GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ + GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ + GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ + GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ + GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ + GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ + + GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ + GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + + GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ + GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ + GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ + + GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ + GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ + GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ + + GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ }; enum MMC_IP_RELATED { - GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ - GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ - - GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ - GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ - GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ - GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ - GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ - - GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ - GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ - GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ - - GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ - GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ - - GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ - GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ + GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ + GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ + + GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ + GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ + GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ + GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ + + GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ + GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ + GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ + + GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ + GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ + + GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ + GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ - GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ - - GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ - GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ - GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ - GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ - GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ - - GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ - GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ - GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ - - GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ - GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ - - GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ - GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ - - GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ + GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ + + GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ + GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ + GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ + + GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ + GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ + + GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ + GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ + + GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ + GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ + + GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ }; enum MMC_CNTRL_REG_BIT_DESCRIPTIONS { - GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ - GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ - GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */ - GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ - + GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ + GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ + GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */ + GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ + }; enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ - GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ - GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ - GmacMmcRxPauseFrameInt = 0x00100000, /* set when GmacMmcRxPauseFrames counter reaches half of max value */ - GmacMmcRxOutOfRangeInt = 0x00080000, /* set when GmacMmcRxOutOfRangeType counter reaches half of max value */ - GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ - GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ - GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ - GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ - GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ - GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ - GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ - GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ - GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ - GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ - GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ - GmacMmcRxAlignErrorInt = 0x00000040, /* set when GmacMmcRxAlignError counter reaches half of max value */ - GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ - GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ - GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ - GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ - GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ - GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ + GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ + GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ + GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ + GmacMmcRxPauseFrameInt = 0x00100000, /* set when GmacMmcRxPauseFrames counter reaches half of max value */ + GmacMmcRxOutOfRangeInt = 0x00080000, /* set when GmacMmcRxOutOfRangeType counter reaches half of max value */ + GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ + GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ + GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ + GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ + GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ + GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ + GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ + GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ + GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ + GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ + GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ + GmacMmcRxAlignErrorInt = 0x00000040, /* set when GmacMmcRxAlignError counter reaches half of max value */ + GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ + GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ + GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ + GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ + GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ + GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ }; enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ - GmacMmcTxPauseFrameInt = 0x00800000, /* set when GmacMmcTxPauseFrames counter reaches half of max value */ - GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ - GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ - GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ - GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ - GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ - GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ - GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ - GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ - GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ - GmacMmcTxUnderFlowErrorInt = 0x00002000, /* set when GmacMmcTxUnderFlowError counter reaches half of max value */ - GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ - GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ - GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ - GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ - GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ - GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ - GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ - GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ - GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ - GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ - GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ - GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ - + GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ + GmacMmcTxPauseFrameInt = 0x00800000, /* set when GmacMmcTxPauseFrames counter reaches half of max value */ + GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ + GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ + GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ + GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ + GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ + GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ + GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ + GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ + GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ + GmacMmcTxUnderFlowErrorInt = 0x00002000, /* set when GmacMmcTxUnderFlowError counter reaches half of max value */ + GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ + GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ + GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ + GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ + GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ + GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ + GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ + GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ + GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ + GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ + GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ + GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ + }; /********************************************************** - * Power Management (PMT) Block + * Power Management (PMT) Block **********************************************************/ /** @@ -1372,36 +1372,36 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS * These enable are in PMT control and Status register and are programmed by apllication. * * When power down mode is enabled in PMT, all rx frames are dropped by the core. Core comes - * out of power down mode only when either Magic packe tor a Remote wake-up frame is received + * out of power down mode only when either Magic packe tor a Remote wake-up frame is received * and the corresponding detection is enabled. * - * Driver need not be modified to support this feature. Only Api to put the device in to power + * Driver need not be modified to support this feature. Only Api to put the device in to power * down mode is sufficient */ -#define WAKEUP_REG_LENGTH 8 /*This is the reg length for wake up register configuration*/ +#define WAKEUP_REG_LENGTH 8 /*This is the reg length for wake up register configuration*/ enum GmacPmtCtrlStatusBitDefinition { - GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ - GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ - GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ - GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ - GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ - GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ - GmacPmtPowerDown = 0x00000001, /* Power Down */ + GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ + GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ + GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ + GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ + GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ + GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ + GmacPmtPowerDown = 0x00000001, /* Power Down */ }; /********************************************************** - * IEEE 1588-2008 Precision Time Protocol (PTP) Support + * IEEE 1588-2008 Precision Time Protocol (PTP) Support **********************************************************/ enum PTPMessageType { - SYNC = 0x0, - Delay_Req = 0x1, + SYNC = 0x0, + Delay_Req = 0x1, Pdelay_Req = 0x2, Pdelay_Resp = 0x3, Follow_up = 0x8, @@ -1414,14 +1414,14 @@ enum PTPMessageType -typedef struct TimeStampStruct -{ +typedef struct TimeStampStruct +{ u32 TSversion; /* PTP Version 1 or PTP version2 */ - u32 TSmessagetype; /* Message type associated with this time stamp */ + u32 TSmessagetype; /* Message type associated with this time stamp */ - u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ - u32 TSupper32; /* Most significant 32 bit time stamp value */ - u32 TSlower32; /* Least Significat 32 bit time stamp value */ + u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ + u32 TSupper32; /* Most significant 32 bit time stamp value */ + u32 TSlower32; /* Least Significat 32 bit time stamp value */ } TimeStamp; @@ -1439,9 +1439,9 @@ typedef struct TimeStampStruct /* GmacTSControl = 0x0700, Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ enum GmacTSControlReg { - GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ - - GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ + GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ + + GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ /* TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken 00/01 X 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP @@ -1450,45 +1450,45 @@ enum GmacTSControlReg 10 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP 10 NA 1 SYNC, FOLLOW_UP 11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP - 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP + 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP */ - GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ - GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ - GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ - GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ + GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ + GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ + GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ + GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ - GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ - GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ - GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ - GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ - GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ - GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ + GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ + GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ + GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ + GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ + GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ + GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */ GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */ - GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ - GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ - GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ - - GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ + GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ + GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ + GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ - GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ - GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ - GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ - GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ + GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ + GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ + GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + + GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ }; -/* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ +/* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ enum GmacTSSubSecIncrReg { GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */ }; -/* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ +/* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ enum GmacTSSign { GmacTSSign = 0x80000000, /* PSNT 31 RW 0 */ @@ -1496,23 +1496,23 @@ enum GmacTSSign GmacTSNegative = 0x80000000, }; -/*GmacTargetTimeLow = 0x0718, 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ +/*GmacTargetTimeLow = 0x0718, 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ enum GmacTSLowReg { GmacTSDecThr = 0x3B9AC9FF, /*when TSCTRLSSR is set the max value for GmacTargetTimeLowReg and GmacTimeStampLow register is 0x3B9AC9FF at 1ns precision */ }; /* GmacTSHighWord = 0x0724, Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ -enum GmacTSHighWordReg +enum GmacTSHighWordReg { - GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */ + GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */ }; /*GmacTSStatus = 0x0728, Time Stamp Status Register */ enum GmacTSStatusReg { GmacTSTargTimeReached = 0x00000002, /* Time Stamp Target Time Reached 1 RO 0 */ GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */ -}; +}; /********************************************************** @@ -1527,9 +1527,9 @@ void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev); void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev); void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type); -void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" -void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" -void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" @@ -1540,7 +1540,7 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev); // void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" -void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" @@ -1549,11 +1549,11 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value); s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); -void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled -void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled +void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled +void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_val); // Update should happen making use of subsecond mask -void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, +void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val); // Reads the timestamp low,high and higher(Ver2) registers in the the struct pointer; readonly contents void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val); //Loads the timestamp target register with the values provided @@ -1571,7 +1571,7 @@ s32 synopGMAC_read_phy_reg(u32 RegBase,u32 PhyBase, u32 RegOffset, u16 * data); s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data); s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback); s32 synopGMAC_read_version (synopGMACdevice * gmacdev) ; -s32 synopGMAC_reset (synopGMACdevice * gmacdev ); +s32 synopGMAC_reset (synopGMACdevice * gmacdev ); s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ); s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value ); void synopGMAC_wd_enable(synopGMACdevice * gmacdev); @@ -1669,15 +1669,15 @@ bool synopGMAC_is_rx_desc_chained(DmaDesc * desc); bool synopGMAC_is_tx_desc_chained(DmaDesc * desc); void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2); #ifdef ENH_DESC_8W -s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, - u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); +s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, + u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); #else s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2 ); #endif s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2,u32 offload_needed,u32 * index,DmaDesc *Dpr); s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2); #ifdef ENH_DESC_8W -s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, +s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); #else s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2); @@ -1698,8 +1698,8 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev); void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev); void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev); /******Following APIs are valid only for Enhanced Descriptor from 3.50a release onwards*******/ -bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status); -bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status); +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status); +bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status); bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status); bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status); /*******************PMT APIs***************************************/ |