summaryrefslogtreecommitdiff
path: root/bsp/m16c62p/drivers/uart.c
diff options
context:
space:
mode:
Diffstat (limited to 'bsp/m16c62p/drivers/uart.c')
-rw-r--r--bsp/m16c62p/drivers/uart.c240
1 files changed, 120 insertions, 120 deletions
diff --git a/bsp/m16c62p/drivers/uart.c b/bsp/m16c62p/drivers/uart.c
index 62e2a6b885..67f56b98a3 100644
--- a/bsp/m16c62p/drivers/uart.c
+++ b/bsp/m16c62p/drivers/uart.c
@@ -19,44 +19,44 @@
struct rt_uart_m16c
{
- struct rt_device parent;
+ struct rt_device parent;
- /* buffer for reception */
- rt_uint8_t read_index, save_index;
- rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+ /* buffer for reception */
+ rt_uint8_t read_index, save_index;
+ rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
void u0rec_handler(void)
{
- rt_ubase_t level;
- rt_uint8_t c;
+ rt_ubase_t level;
+ rt_uint8_t c;
- struct rt_uart_m16c *uart = &uart_device;
+ struct rt_uart_m16c *uart = &uart_device;
- while (U0C1.BIT.RI == 0)
- ;
- c = U0RB.BYTE.U0RBL;
+ while (U0C1.BIT.RI == 0)
+ ;
+ c = U0RB.BYTE.U0RBL;
- /* Receive Data Available */
+ /* Receive Data Available */
uart->rx_buffer[uart->save_index] = c;
level = rt_hw_interrupt_disable();
- uart->save_index ++;
+ uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
- /* invoke callback */
- if (uart->parent.rx_indicate != RT_NULL)
- {
- rt_size_t length;
- if (uart->read_index > uart->save_index)
+ /* invoke callback */
+ if (uart->parent.rx_indicate != RT_NULL)
+ {
+ rt_size_t length;
+ if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
- }
+ }
}
static rt_err_t rt_uart_init (rt_device_t dev)
@@ -65,7 +65,7 @@ static rt_err_t rt_uart_init (rt_device_t dev)
/* set UART0 bit rate generator bit rate can be calculated by:
bit rate = ((BRG count source / 16)/baud rate) - 1
Baud rate is based on main crystal or PLL not CPU core clock */
- //pclk1 = 1; /// seleck F1SIO
+ //pclk1 = 1; /// seleck F1SIO
U0BRG = (unsigned char)(((CPU_CLK_FREQ/16)/BAUD_RATE)-1); //(N+1)
/* UART Transmit/Receive Control Register 2 */
@@ -139,144 +139,144 @@ static rt_err_t rt_uart_init (rt_device_t dev)
b6 UOLCH Data logic select bit
b7 UOERE Error signal output enable bit */
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
- RT_ASSERT(dev != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* Enable the UART Interrupt */
- }
+ RT_ASSERT(dev != RT_NULL);
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /* Enable the UART Interrupt */
+ }
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
- RT_ASSERT(dev != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* Disable the UART Interrupt */
- }
+ RT_ASSERT(dev != RT_NULL);
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /* Disable the UART Interrupt */
+ }
- return RT_EOK;
+ return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
- rt_uint8_t *ptr;
- struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev;
- RT_ASSERT(uart != RT_NULL);
+ rt_uint8_t *ptr;
+ struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev;
+ RT_ASSERT(uart != RT_NULL);
- /* point to buffer */
- ptr = (rt_uint8_t *)buffer;
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- while (size)
- {
- /* interrupt receive */
- rt_base_t level;
+ /* point to buffer */
+ ptr = (rt_uint8_t *)buffer;
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ while (size)
+ {
+ /* interrupt receive */
+ rt_base_t level;
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
- if (uart->read_index != uart->save_index)
- {
- *ptr = uart->rx_buffer[uart->read_index];
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+ if (uart->read_index != uart->save_index)
+ {
+ *ptr = uart->rx_buffer[uart->read_index];
- uart->read_index ++;
- if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
- uart->read_index = 0;
- }
- else
- {
- /* no data in rx buffer */
+ uart->read_index ++;
+ if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+ uart->read_index = 0;
+ }
+ else
+ {
+ /* no data in rx buffer */
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- break;
- }
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ break;
+ }
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
- ptr ++;
- size --;
- }
+ ptr ++;
+ size --;
+ }
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
- }
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+ }
- return 0;
+ return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
- char *ptr;
- ptr = (char *)buffer;
+ char *ptr;
+ ptr = (char *)buffer;
- if (dev->flag & RT_DEVICE_FLAG_STREAM)
- {
- /* stream mode */
- while (size)
- {
- if (*ptr == '\n')
- {
- while (U0C1.BIT.TI == 0)
- ;
- U0TB.BYTE.U0TBL = '\r';
- }
+ if (dev->flag & RT_DEVICE_FLAG_STREAM)
+ {
+ /* stream mode */
+ while (size)
+ {
+ if (*ptr == '\n')
+ {
+ while (U0C1.BIT.TI == 0)
+ ;
+ U0TB.BYTE.U0TBL = '\r';
+ }
- /* THRE status, contain valid data */
- while (U0C1.BIT.TI == 0)
- ;
- U0TB.BYTE.U0TBL = *ptr;
-
- ptr ++;
- size --;
- }
- }
- else
- {
- while (size != 0)
- {
- /* THRE status, contain valid data */
- while (U0C1.BIT.TI == 0)
- ;
- U0TB.BYTE.U0TBL = *ptr;
-
- ptr ++;
- size --;
- }
- }
+ /* THRE status, contain valid data */
+ while (U0C1.BIT.TI == 0)
+ ;
+ U0TB.BYTE.U0TBL = *ptr;
- return (rt_size_t)ptr - (rt_size_t)buffer;
+ ptr ++;
+ size --;
+ }
+ }
+ else
+ {
+ while (size != 0)
+ {
+ /* THRE status, contain valid data */
+ while (U0C1.BIT.TI == 0)
+ ;
+ U0TB.BYTE.U0TBL = *ptr;
+
+ ptr ++;
+ size --;
+ }
+ }
+
+ return (rt_size_t)ptr - (rt_size_t)buffer;
}
void rt_hw_uart_init(void)
{
- struct rt_uart_m16c *uart;
+ struct rt_uart_m16c *uart;
- /* get uart device */
- uart = &uart_device;
+ /* get uart device */
+ uart = &uart_device;
- /* device initialization */
- uart->parent.type = RT_Device_Class_Char;
- rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
- uart->read_index = uart->save_index = 0;
+ /* device initialization */
+ uart->parent.type = RT_Device_Class_Char;
+ rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+ uart->read_index = uart->save_index = 0;
- /* device interface */
- uart->parent.init = rt_uart_init;
- uart->parent.open = rt_uart_open;
- uart->parent.close = rt_uart_close;
- uart->parent.read = rt_uart_read;
- uart->parent.write = rt_uart_write;
- uart->parent.control = RT_NULL;
- uart->parent.user_data = RT_NULL;
+ /* device interface */
+ uart->parent.init = rt_uart_init;
+ uart->parent.open = rt_uart_open;
+ uart->parent.close = rt_uart_close;
+ uart->parent.read = rt_uart_read;
+ uart->parent.write = rt_uart_write;
+ uart->parent.control = RT_NULL;
+ uart->parent.user_data = RT_NULL;
- rt_device_register(&uart->parent,
- "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+ rt_device_register(&uart->parent,
+ "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
}
#endif /* end of UART */