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-rw-r--r--bsp/pic32ethernet/application.c2
-rw-r--r--bsp/pic32ethernet/board.c28
-rw-r--r--bsp/pic32ethernet/console.c4
-rw-r--r--bsp/pic32ethernet/rtconfig.h64
-rw-r--r--bsp/pic32ethernet/startup.c56
5 files changed, 77 insertions, 77 deletions
diff --git a/bsp/pic32ethernet/application.c b/bsp/pic32ethernet/application.c
index 2a14dd8f3f..ae2238f60b 100644
--- a/bsp/pic32ethernet/application.c
+++ b/bsp/pic32ethernet/application.c
@@ -29,7 +29,7 @@ void thread_led1_entry(void* parameter)
static void thread_led2_entry(void* parameter)
{
- // configure PORTD.RD2 = output
+ // configure PORTD.RD2 = output
mPORTDSetPinsDigitalOut(BIT_2);
while (1)
diff --git a/bsp/pic32ethernet/board.c b/bsp/pic32ethernet/board.c
index d7d5167998..5a738af8b1 100644
--- a/bsp/pic32ethernet/board.c
+++ b/bsp/pic32ethernet/board.c
@@ -32,12 +32,12 @@
#pragma config DEBUG = OFF // Debugger Disabled for Starter Kit
// The following is used by the main application
-#define SYS_FREQ (80000000UL)
+#define SYS_FREQ (80000000UL)
-#define PB_DIV (1 << ((OSCCON&_OSCCON_PBDIV0_MASK)>>_OSCCON_PBDIV0_POSITION) )
-#define PRESCALE 256
-#define TOGGLES_PER_SEC RT_TICK_PER_SECOND
-#define T1_TICK (SYS_FREQ/PB_DIV/PRESCALE/TOGGLES_PER_SEC)
+#define PB_DIV (1 << ((OSCCON&_OSCCON_PBDIV0_MASK)>>_OSCCON_PBDIV0_POSITION) )
+#define PRESCALE 256
+#define TOGGLES_PER_SEC RT_TICK_PER_SECOND
+#define T1_TICK (SYS_FREQ/PB_DIV/PRESCALE/TOGGLES_PER_SEC)
static void rt_hw_show_info(void)
{
@@ -64,18 +64,18 @@ static void rt_hw_timer_handler(void)
void rt_hw_board_init()
{
// Configure the device for maximum performance, but do not change the PBDIV clock divisor.
- // Given the options, this function will change the program Flash wait states,
- // RAM wait state and enable prefetch cache, but will not change the PBDIV.
+ // Given the options, this function will change the program Flash wait states,
+ // RAM wait state and enable prefetch cache, but will not change the PBDIV.
// The PBDIV value is already set via the pragma FPBDIV option above.
- SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
+ SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
- /* use DBPRINTF */
- /* rt_hw_console_init(); */
+ /* use DBPRINTF */
+ /* rt_hw_console_init(); */
- rt_hw_usart_init();
- rt_console_set_device("uart1");
+ rt_hw_usart_init();
+ rt_console_set_device("uart1");
- rt_hw_show_info();
+ rt_hw_show_info();
// enable multi-vector interrupts
INTEnableSystemMultiVectoredInt();
@@ -93,7 +93,7 @@ void rt_hw_board_init()
ConfigIntTimer1(T1_INT_ON | T1_INT_PRIOR_2);
/* Setup the software interrupt. */
- mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 );
+ mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 );
}
void __ISR(_TIMER_1_VECTOR, ipl2) Timer1Handler(void)
diff --git a/bsp/pic32ethernet/console.c b/bsp/pic32ethernet/console.c
index 587b90ef32..35c6725cf2 100644
--- a/bsp/pic32ethernet/console.c
+++ b/bsp/pic32ethernet/console.c
@@ -19,8 +19,8 @@
void rt_hw_console_init(void)
{
- //Initialize the DB_UTILS IO channel
-// DBINIT();
+ //Initialize the DB_UTILS IO channel
+// DBINIT();
}
/**
diff --git a/bsp/pic32ethernet/rtconfig.h b/bsp/pic32ethernet/rtconfig.h
index 5d329788bc..9783379c99 100644
--- a/bsp/pic32ethernet/rtconfig.h
+++ b/bsp/pic32ethernet/rtconfig.h
@@ -3,16 +3,16 @@
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
-#define RT_NAME_MAX 8
+#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE 4
+#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX 32
+#define RT_THREAD_PRIORITY_MAX 32
/* Tick per Second */
-#define RT_TICK_PER_SECOND 100
+#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
@@ -31,9 +31,9 @@
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 512
-#define RT_TIMER_TICK_PER_SECOND 10
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_TIMER_TICK_PER_SECOND 10
/* SECTION: IPC */
/* Using Semaphore*/
@@ -69,7 +69,7 @@
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLEBUF_SIZE 128
//#define RT_USING_NEWLIB
@@ -84,11 +84,11 @@
#define RT_USING_DFS_ELMFAT
/* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX 2
-/* the max number of opened files */
-#define DFS_FD_MAX 4
-/* the max number of cached sector */
-#define DFS_CACHE_MAX_NUM 4
+#define DFS_FILESYSTEMS_MAX 2
+/* the max number of opened files */
+#define DFS_FD_MAX 4
+/* the max number of cached sector */
+#define DFS_CACHE_MAX_NUM 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
//#define RT_USING_LWIP
@@ -102,37 +102,37 @@
#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM 5
+#define RT_LWIP_TCP_PCB_NUM 5
/* Using DHCP */
//#define RT_LWIP_DHCP
/* ip address of target*/
-#define RT_LWIP_IPADDR0 192
-#define RT_LWIP_IPADDR1 168
-#define RT_LWIP_IPADDR2 1
-#define RT_LWIP_IPADDR3 30
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
-#define RT_LWIP_GWADDR0 192
-#define RT_LWIP_GWADDR1 168
-#define RT_LWIP_GWADDR2 1
-#define RT_LWIP_GWADDR3 1
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
/* mask address of target*/
-#define RT_LWIP_MSKADDR0 255
-#define RT_LWIP_MSKADDR1 255
-#define RT_LWIP_MSKADDR2 255
-#define RT_LWIP_MSKADDR3 0
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY 12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
-#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
+#define RT_LWIP_TCPTHREAD_PRIORITY 12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
+#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
-#define RT_LWIP_ETHTHREAD_PRIORITY 15
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
-#define RT_LWIP_ETHTHREAD_STACKSIZE 512
+#define RT_LWIP_ETHTHREAD_PRIORITY 15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#endif
diff --git a/bsp/pic32ethernet/startup.c b/bsp/pic32ethernet/startup.c
index 33ea631e77..16285d8c56 100644
--- a/bsp/pic32ethernet/startup.c
+++ b/bsp/pic32ethernet/startup.c
@@ -25,61 +25,61 @@ extern void finsh_set_device(const char* device);
*/
void rtthread_startup(void)
{
- /* init board */
- rt_hw_board_init();
+ /* init board */
+ rt_hw_board_init();
- /* show version */
- rt_show_version();
+ /* show version */
+ rt_show_version();
- /* init tick */
- rt_system_tick_init();
+ /* init tick */
+ rt_system_tick_init();
- /* init kernel object */
- rt_system_object_init();
+ /* init kernel object */
+ rt_system_object_init();
- /* init timer system */
- rt_system_timer_init();
+ /* init timer system */
+ rt_system_timer_init();
#ifdef RT_USING_HEAP
/* init memory system */
rt_system_heap_init((void*)&_ramfunc_end, (void*)PIC32_SRAM_END);
#endif
- /* init scheduler system */
- rt_system_scheduler_init();
+ /* init scheduler system */
+ rt_system_scheduler_init();
- /* init application */
- rt_application_init();
+ /* init application */
+ rt_application_init();
#ifdef RT_USING_FINSH
- /* init finsh */
- finsh_system_init();
+ /* init finsh */
+ finsh_system_init();
#ifdef RT_USING_DEVICE
- finsh_set_device("uart1");
+ finsh_set_device("uart1");
#endif
#endif
/* init timer thread */
rt_system_timer_thread_init();
- /* init idle thread */
- rt_thread_idle_init();
+ /* init idle thread */
+ rt_thread_idle_init();
- /* start scheduler */
- rt_system_scheduler_start();
+ /* start scheduler */
+ rt_system_scheduler_start();
- /* never reach here */
- return ;
+ /* never reach here */
+ return ;
}
int main(void)
{
- /* disable interrupt first */
- rt_hw_interrupt_disable();
+ /* disable interrupt first */
+ rt_hw_interrupt_disable();
- /* startup RT-Thread RTOS */
- rtthread_startup();
+ /* startup RT-Thread RTOS */
+ rtthread_startup();
- return 0;
+ return 0;
}
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-24 08:13:12 +0000