diff options
Diffstat (limited to 'bsp/sam7x/drivers')
| -rw-r--r-- | bsp/sam7x/drivers/AT91SAM7X.h | 420 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/board.c | 154 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/board.h | 6 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/serial.c | 514 |
4 files changed, 547 insertions, 547 deletions
diff --git a/bsp/sam7x/drivers/AT91SAM7X.h b/bsp/sam7x/drivers/AT91SAM7X.h index 96430b2a17..2ee0c4fedc 100644 --- a/bsp/sam7x/drivers/AT91SAM7X.h +++ b/bsp/sam7x/drivers/AT91SAM7X.h @@ -19,229 +19,229 @@ extern "C" { #endif -#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ +#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ /* ========== Register definition for TC0 peripheral ========== */ -#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ -#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ -#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ -#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ -#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ -#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ -#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ -#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ -#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ +#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ +#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ +#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ +#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ +#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ +#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ +#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ +#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ +#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ /* ========== Register definition for TC1 peripheral ========== */ -#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ -#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ -#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ -#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ -#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ -#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ -#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ -#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ -#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ +#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ +#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ +#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ +#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ +#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ +#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ +#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ +#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ +#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ /* ========== Register definition for TC2 peripheral ========== */ -#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ -#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ -#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ -#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ -#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ -#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ -#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ -#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ -#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ +#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ +#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ +#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ +#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ +#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ +#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ +#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ +#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ +#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ /* ========== Register definition for PITC peripheral ========== */ -#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ -#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ -#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ -#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ +#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ +#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ +#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ +#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ /* ========== Register definition for UDP peripheral ========== */ -#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ -#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ -#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ -#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ -#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ -#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ -#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ -#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ -#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ -#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ -#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) -#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ -#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) -#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ +#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ +#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ +#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ +#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ +#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ +#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ +#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ +#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ +#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ +#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ +#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) +#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ +#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) +#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ /* ========== Register definition for US0 peripheral ========== */ -#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ -#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ -#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ -#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ -#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ -#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ -#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ -#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ -#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ -#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ -#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ -#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ -#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ -#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ +#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ +#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ +#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ +#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ +#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ +#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ +#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ +#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ +#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ +#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ +#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ +#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ +#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ +#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ /* ========== Register definition for AIC peripheral ========== */ -#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ -#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) -#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ -#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) -#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ -#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ -#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ -#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ -#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ -#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ -#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ -#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ -#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ -#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ -#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ -#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ -#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ -#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ -#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ -#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ +#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ +#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) +#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ +#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) +#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ +#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ +#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ +#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ +#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ +#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ +#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ +#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ +#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ +#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ +#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ +#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ +#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ +#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ +#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ +#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ /* ========== Register definition for DBGU peripheral ========== */ -#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ -#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ -#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ -#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ -#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ -#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ -#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ -#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ -#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ -#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ -#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ -#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ +#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ +#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ +#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ +#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ +#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ +#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ +#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ +#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ +#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ +#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ +#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ +#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ /* ========== Register definition for PIO peripheral ========== */ -#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ -#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ -#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ -#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ -#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ -#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ -#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ -#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ -#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ -#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ -#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ -#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ -#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ -#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ -#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ -#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ -#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ -#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ -#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ -#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ -#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ -#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ -#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ -#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ -#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ -#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ -#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ -#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ -#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ +#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ +#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ +#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ +#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ +#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ +#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ +#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ +#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ +#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ +#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ +#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ +#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ +#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ +#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ +#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ +#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ +#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ +#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ +#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ +#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ +#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ +#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ +#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ +#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ +#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ +#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ +#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ +#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ +#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ // ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register // ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register -#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register -#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register +#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register +#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register +#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register +#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register +#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register +#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register +#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register +#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register +#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register /* ========== Register definition for PMC peripheral ========== */ -#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ -#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ -#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ -#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ -#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ -#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ -#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ -#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ -#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ -#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ -#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ -#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ -#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ -#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ +#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ +#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ +#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ +#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ +#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ +#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ +#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ +#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ +#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ +#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ +#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ +#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ +#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ +#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ +#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ -// ========== Register definition for PDC_SPI1 peripheral ========== +// ========== Register definition for PDC_SPI1 peripheral ========== #define AT91C_SPI1_RNPR (AT91_REG(0xFFFE4110)) // (PDC_SPI1) Receive Next Pointer Register #define AT91C_SPI1_TPR (AT91_REG(0xFFFE4108)) // (PDC_SPI1) Transmit Pointer Register #define AT91C_SPI1_RPR (AT91_REG(0xFFFE4100)) // (PDC_SPI1) Receive Pointer Register @@ -252,7 +252,7 @@ extern "C" { #define AT91C_SPI1_TNCR (AT91_REG(0xFFFE411C)) // (PDC_SPI1) Transmit Next Counter Register #define AT91C_SPI1_TNPR (AT91_REG(0xFFFE4118)) // (PDC_SPI1) Transmit Next Pointer Register #define AT91C_SPI1_PTCR (AT91_REG(0xFFFE4120)) // (PDC_SPI1) PDC Transfer Control Register -// ========== Register definition for SPI1 peripheral ========== +// ========== Register definition for SPI1 peripheral ========== #define AT91C_SPI1_CSR (AT91_REG(0xFFFE4030)) // (SPI1) Chip Select Register #define AT91C_SPI1_IDR (AT91_REG(0xFFFE4018)) // (SPI1) Interrupt Disable Register #define AT91C_SPI1_SR (AT91_REG(0xFFFE4010)) // (SPI1) Status Register @@ -262,7 +262,7 @@ extern "C" { #define AT91C_SPI1_IER (AT91_REG(0xFFFE4014)) // (SPI1) Interrupt Enable Register #define AT91C_SPI1_TDR (AT91_REG(0xFFFE400C)) // (SPI1) Transmit Data Register #define AT91C_SPI1_MR (AT91_REG(0xFFFE4004)) // (SPI1) Mode Register -// ========== Register definition for PDC_SPI0 peripheral ========== +// ========== Register definition for PDC_SPI0 peripheral ========== #define AT91C_SPI0_PTCR (AT91_REG(0xFFFE0120)) // (PDC_SPI0) PDC Transfer Control Register #define AT91C_SPI0_TNPR (AT91_REG(0xFFFE0118)) // (PDC_SPI0) Transmit Next Pointer Register #define AT91C_SPI0_RNPR (AT91_REG(0xFFFE0110)) // (PDC_SPI0) Receive Next Pointer Register @@ -273,7 +273,7 @@ extern "C" { #define AT91C_SPI0_RNCR (AT91_REG(0xFFFE0114)) // (PDC_SPI0) Receive Next Counter Register #define AT91C_SPI0_TCR (AT91_REG(0xFFFE010C)) // (PDC_SPI0) Transmit Counter Register #define AT91C_SPI0_RCR (AT91_REG(0xFFFE0104)) // (PDC_SPI0) Receive Counter Register -// ========== Register definition for SPI0 peripheral ========== +// ========== Register definition for SPI0 peripheral ========== #define AT91C_SPI0_CSR (AT91_REG(0xFFFE0030)) // (SPI0) Chip Select Register #define AT91C_SPI0_IDR (AT91_REG(0xFFFE0018)) // (SPI0) Interrupt Disable Register #define AT91C_SPI0_SR (AT91_REG(0xFFFE0010)) // (SPI0) Status Register @@ -321,19 +321,19 @@ extern "C" { #define AT91C_ID_IRQ1 (31) /* Advanced Interrupt Controller (IRQ1) */ #define AT91C_ALL_INT (0xC00FFFFF) /* ALL VALID INTERRUPTS */ -#define MCK 48054857 +#define MCK 48054857 /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #ifdef __cplusplus } diff --git a/bsp/sam7x/drivers/board.c b/bsp/sam7x/drivers/board.c index 1e13656f66..571e7e724c 100644 --- a/bsp/sam7x/drivers/board.c +++ b/bsp/sam7x/drivers/board.c @@ -35,40 +35,40 @@ static void rt_hw_board_led_init(void); */ void rt_hw_timer_handler(int vector, void* param) { - if (AT91C_BASE_PITC->PITC_PISR & 0x01) - { - /* increase a tick */ - rt_tick_increase(); + if (AT91C_BASE_PITC->PITC_PISR & 0x01) + { + /* increase a tick */ + rt_tick_increase(); - /* ack interrupt */ - AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR; - } - else - { - /* end of interrupt */ - AT91C_BASE_AIC->AIC_EOICR = 0; - } + /* ack interrupt */ + AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR; + } + else + { + /* end of interrupt */ + AT91C_BASE_AIC->AIC_EOICR = 0; + } } - /* PIO Flash PA PB PIN */ -#define LED1 (1 << 19) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */ -#define LED2 (1 << 20) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */ -#define LED3 (1 << 21) /* PA2 & PWM2 SCK0 44 */ -#define LED4 (1 << 22) /* PA3 & TWD NPCS3 43 */ -#define LED_MASK (LED1|LED2|LED3|LED4) + /* PIO Flash PA PB PIN */ +#define LED1 (1 << 19) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */ +#define LED2 (1 << 20) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */ +#define LED3 (1 << 21) /* PA2 & PWM2 SCK0 44 */ +#define LED4 (1 << 22) /* PA3 & TWD NPCS3 43 */ +#define LED_MASK (LED1|LED2|LED3|LED4) int leds[] = {LED1, LED2, LED3, LED4}; -/** +/** * This function will init led on the board */ static void rt_hw_board_led_init() { - /* enable the clock of the PIO A, PIO B */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA | 1 << AT91C_ID_PIOB; + /* enable the clock of the PIO A, PIO B */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA | 1 << AT91C_ID_PIOB; - /* configure PIO as output for led */ - AT91C_BASE_PIOB->PIO_PER = LED_MASK; - AT91C_BASE_PIOB->PIO_OER = LED_MASK; + /* configure PIO as output for led */ + AT91C_BASE_PIOB->PIO_PER = LED_MASK; + AT91C_BASE_PIOB->PIO_OER = LED_MASK; } /** @@ -78,10 +78,10 @@ static void rt_hw_board_led_init() */ void rt_hw_board_led_on(int n) { - if (n >= 0 && n < 4) - { - AT91C_BASE_PIOB->PIO_CODR = leds[n]; - } + if (n >= 0 && n < 4) + { + AT91C_BASE_PIOB->PIO_CODR = leds[n]; + } } /** @@ -91,10 +91,10 @@ void rt_hw_board_led_on(int n) */ void rt_hw_board_led_off(int n) { - if (n >= 0 && n < 4) - { - AT91C_BASE_PIOB->PIO_SODR = leds[n]; - } + if (n >= 0 && n < 4) + { + AT91C_BASE_PIOB->PIO_SODR = leds[n]; + } } /* @@ -108,47 +108,47 @@ void rt_hw_board_led_off(int n) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str == '\n') - { - while (!(AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY)); - AT91C_BASE_US0->US_THR = '\r'; - } - - /* Wait for Empty Tx Buffer */ - while (!(AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - AT91C_BASE_US0->US_THR = *str; - - str ++; - } + while (*str) + { + if (*str == '\n') + { + while (!(AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY)); + AT91C_BASE_US0->US_THR = '\r'; + } + + /* Wait for Empty Tx Buffer */ + while (!(AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY)); + /* Transmit Character */ + AT91C_BASE_US0->US_THR = *str; + + str ++; + } } static void rt_hw_console_init() { - /* Enable Clock for USART0 */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0; - /* Enable RxD0 and TxD0 Pin */ - //AT91C_BASE_PIOA->PIO_PDR = (1 << 5) | (1 << 6); - AT91C_BASE_PIOA->PIO_PDR = 1 | (1 << 1);//fix bug 2010-3-9 + /* Enable Clock for USART0 */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0; + /* Enable RxD0 and TxD0 Pin */ + //AT91C_BASE_PIOA->PIO_PDR = (1 << 5) | (1 << 6); + AT91C_BASE_PIOA->PIO_PDR = 1 | (1 << 1);//fix bug 2010-3-9 - AT91C_BASE_US0->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ + AT91C_BASE_US0->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ - AT91C_BASE_US0->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ - AT91C_US_CLKS_CLOCK | /* Clock = MCK */ - AT91C_US_CHRL_8_BITS | /* 8-bit Data */ - AT91C_US_PAR_NONE | /* No Parity */ - AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + AT91C_BASE_US0->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - /* set baud rate divisor */ - AT91C_BASE_US0->US_BRGR = BRD; + /* set baud rate divisor */ + AT91C_BASE_US0->US_BRGR = BRD; - AT91C_BASE_US0->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ + AT91C_BASE_US0->US_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ } /** @@ -156,20 +156,20 @@ static void rt_hw_console_init() */ void rt_hw_board_init(void) { - extern void rt_serial_init(void); - - /* init hardware console */ - rt_hw_console_init(); + extern void rt_serial_init(void); + + /* init hardware console */ + rt_hw_console_init(); - /* init led */ - rt_hw_board_led_init(); + /* init led */ + rt_hw_board_led_init(); - /* init PITC */ - AT91C_BASE_PITC->PITC_PIMR = (1 << 25) | (1 << 24) | PIV; + /* init PITC */ + AT91C_BASE_PITC->PITC_PIMR = (1 << 25) | (1 << 24) | PIV; - /* install timer handler */ - rt_hw_interrupt_install(AT91C_ID_SYS, rt_hw_timer_handler, RT_NULL, "tick"); - AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SYS] = 0; - rt_hw_interrupt_umask(AT91C_ID_SYS); + /* install timer handler */ + rt_hw_interrupt_install(AT91C_ID_SYS, rt_hw_timer_handler, RT_NULL, "tick"); + AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SYS] = 0; + rt_hw_interrupt_umask(AT91C_ID_SYS); } /*@}*/ diff --git a/bsp/sam7x/drivers/board.h b/bsp/sam7x/drivers/board.h index 97a1e449fc..fbabb628ba 100644 --- a/bsp/sam7x/drivers/board.h +++ b/bsp/sam7x/drivers/board.h @@ -19,9 +19,9 @@ #include <rtthread.h> -#define MCK 48054857 -#define BR 115200 /* Baud Rate */ -#define BRD (MCK/16/BR) /* Baud Rate Divisor */ +#define MCK 48054857 +#define BR 115200 /* Baud Rate */ +#define BRD (MCK/16/BR) /* Baud Rate Divisor */ void rt_hw_board_led_on(int n); void rt_hw_board_led_off(int n); diff --git a/bsp/sam7x/drivers/serial.c b/bsp/sam7x/drivers/serial.c index 48fe49fed8..0f6d04a648 100644 --- a/bsp/sam7x/drivers/serial.c +++ b/bsp/sam7x/drivers/serial.c @@ -28,46 +28,46 @@ typedef volatile rt_uint32_t REG32; struct rt_at91serial_hw { - REG32 US_CR; // Control Register - REG32 US_MR; // Mode Register - REG32 US_IER; // Interrupt Enable Register - REG32 US_IDR; // Interrupt Disable Register - REG32 US_IMR; // Interrupt Mask Register - REG32 US_CSR; // Channel Status Register - REG32 US_RHR; // Receiver Holding Register - REG32 US_THR; // Transmitter Holding Register - REG32 US_BRGR; // Baud Rate Generator Register - REG32 US_RTOR; // Receiver Time-out Register - REG32 US_TTGR; // Transmitter Time-guard Register - REG32 Reserved0[5]; // - REG32 US_FIDI; // FI_DI_Ratio Register - REG32 US_NER; // Nb Errors Register - REG32 Reserved1[1]; // - REG32 US_IF; // IRDA_FILTER Register - REG32 Reserved2[44]; // - REG32 US_RPR; // Receive Pointer Register - REG32 US_RCR; // Receive Counter Register - REG32 US_TPR; // Transmit Pointer Register - REG32 US_TCR; // Transmit Counter Register - REG32 US_RNPR; // Receive Next Pointer Register - REG32 US_RNCR; // Receive Next Counter Register - REG32 US_TNPR; // Transmit Next Pointer Register - REG32 US_TNCR; // Transmit Next Counter Register - REG32 US_PTCR; // PDC Transfer Control Register - REG32 US_PTSR; // PDC Transfer Status Register + REG32 US_CR; // Control Register + REG32 US_MR; // Mode Register + REG32 US_IER; // Interrupt Enable Register + REG32 US_IDR; // Interrupt Disable Register + REG32 US_IMR; // Interrupt Mask Register + REG32 US_CSR; // Channel Status Register + REG32 US_RHR; // Receiver Holding Register + REG32 US_THR; // Transmitter Holding Register + REG32 US_BRGR; // Baud Rate Generator Register + REG32 US_RTOR; // Receiver Time-out Register + REG32 US_TTGR; // Transmitter Time-guard Register + REG32 Reserved0[5]; // + REG32 US_FIDI; // FI_DI_Ratio Register + REG32 US_NER; // Nb Errors Register + REG32 Reserved1[1]; // + REG32 US_IF; // IRDA_FILTER Register + REG32 Reserved2[44]; // + REG32 US_RPR; // Receive Pointer Register + REG32 US_RCR; // Receive Counter Register + REG32 US_TPR; // Transmit Pointer Register + REG32 US_TCR; // Transmit Counter Register + REG32 US_RNPR; // Receive Next Pointer Register + REG32 US_RNCR; // Receive Next Counter Register + REG32 US_TNPR; // Transmit Next Pointer Register + REG32 US_TNCR; // Transmit Next Counter Register + REG32 US_PTCR; // PDC Transfer Control Register + REG32 US_PTSR; // PDC Transfer Status Register }; struct rt_at91serial { - struct rt_device parent; + struct rt_device parent; - struct rt_at91serial_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; + struct rt_at91serial_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 struct rt_at91serial serial1; @@ -78,312 +78,312 @@ struct rt_at91serial serial2; static void rt_hw_serial_isr(int irqno, void* param) { - rt_base_t level; - struct rt_device* device; - struct rt_at91serial* serial = (struct rt_at91serial*)param; + rt_base_t level; + struct rt_device* device; + struct rt_at91serial* serial = (struct rt_at91serial*)param; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - /* get generic device object */ - device = (rt_device_t)serial; + /* get generic device object */ + device = (rt_device_t)serial; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); - /* ack interrupt */ - AT91C_AIC_EOICR = 1; + /* ack interrupt */ + AT91C_AIC_EOICR = 1; } static rt_err_t rt_serial_init (rt_device_t dev) { - rt_uint32_t bd; - struct rt_at91serial* serial = (struct rt_at91serial*) dev; + rt_uint32_t bd; + struct rt_at91serial* serial = (struct rt_at91serial*) dev; - RT_ASSERT(serial != RT_NULL); - /* must be US0 or US1 */ - RT_ASSERT((serial->peripheral_id == AT91C_ID_US0) || - (serial->peripheral_id == AT91C_ID_US1)); + RT_ASSERT(serial != RT_NULL); + /* must be US0 or US1 */ + RT_ASSERT((serial->peripheral_id == AT91C_ID_US0) || + (serial->peripheral_id == AT91C_ID_US1)); - /* Enable Clock for USART */ - AT91C_PMC_PCER = 1 << serial->peripheral_id; + /* Enable Clock for USART */ + AT91C_PMC_PCER = 1 << serial->peripheral_id; - /* Enable RxD0 and TxDO Pin */ - if (serial->peripheral_id == AT91C_ID_US0) - { - /* set pinmux */ - //AT91C_PIO_PDR = (1 << 5) | (1 << 6); - AT91C_PIO_PDR = 1 | (1 << 1); //fix bug 2010-3-9 - } - else if (serial->peripheral_id == AT91C_ID_US1) - { - /* set pinmux */ - //AT91C_PIO_PDR = (1 << 21) | (1 << 22); - AT91C_PIO_PDR = (1 << 5) | (1 << 6); //fix bug 2010-3-9 - } + /* Enable RxD0 and TxDO Pin */ + if (serial->peripheral_id == AT91C_ID_US0) + { + /* set pinmux */ + //AT91C_PIO_PDR = (1 << 5) | (1 << 6); + AT91C_PIO_PDR = 1 | (1 << 1); //fix bug 2010-3-9 + } + else if (serial->peripheral_id == AT91C_ID_US1) + { + /* set pinmux */ + //AT91C_PIO_PDR = (1 << 21) | (1 << 22); + AT91C_PIO_PDR = (1 << 5) | (1 << 6); //fix bug 2010-3-9 + } - serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ + serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ - serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ - AT91C_US_CLKS_CLOCK | /* Clock = MCK */ - AT91C_US_CHRL_8_BITS | /* 8-bit Data */ - AT91C_US_PAR_NONE | /* No Parity */ - AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - /* set baud rate divisor */ - bd = ((MCK*10)/(serial->baudrate * 16)); - if ((bd % 10) >= 5) bd = (bd / 10) + 1; - else bd /= 10; + /* set baud rate divisor */ + bd = ((MCK*10)/(serial->baudrate * 16)); + if ((bd % 10) >= 5) bd = (bd / 10) + 1; + else bd /= 10; - serial->hw_base->US_BRGR = bd; - serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ + serial->hw_base->US_BRGR = bd; + serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ // US_IMR is a READ-ONLY register! - //serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ + //serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, serial, "uart"); - // SAM7X Datasheet 30.5.3: - // It is notrecommended to use the USART interrupt line in edge sensitive mode - //AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); - AT91C_AIC_SMR(serial->peripheral_id) = 5; - rt_hw_interrupt_umask(serial->peripheral_id); - } + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, serial, "uart"); + // SAM7X Datasheet 30.5.3: + // It is notrecommended to use the USART interrupt line in edge sensitive mode + //AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); + AT91C_AIC_SMR(serial->peripheral_id) = 5; + rt_hw_interrupt_umask(serial->peripheral_id); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ - //serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ + //serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ + } - serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ + serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; - size --; - } + ptr ++; + size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { + /* Wait for Full Rx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); - /* Read Character */ - *ptr = serial->hw_base->US_RHR; - ptr ++; - size --; - } + /* Read Character */ + *ptr = serial->hw_base->US_RHR; + ptr ++; + size --; + } - return (rt_size_t)ptr - (rt_size_t)buffer; - } + return (rt_size_t)ptr - (rt_size_t)buffer; + } - return 0; + return 0; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - serial->hw_base->US_THR = '\r'; - } + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ + if (*ptr == '\n') + { + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + serial->hw_base->US_THR = '\r'; + } - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; - size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; + size --; + } + } + else + { + while (size) + { + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; - size --; - } - } - } + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; + size --; + } + } + } - return (rt_size_t)ptr - (rt_size_t)buffer; + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } rt_err_t rt_hw_serial_init() { - rt_device_t device; + rt_device_t device; #ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; + device = (rt_device_t) &serial1; - /* init serial device private data */ - serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; - serial1.peripheral_id = AT91C_ID_US0; - serial1.baudrate = 115200; + /* init serial device private data */ + serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; + serial1.peripheral_id = AT91C_ID_US0; + serial1.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - device = (rt_device_t) &serial2; + device = (rt_device_t) &serial2; - serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; - serial2.peripheral_id = AT91C_ID_US1; - serial2.baudrate = 115200; + serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; + serial2.peripheral_id = AT91C_ID_US1; + serial2.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart2 on device subsystem */ - rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart2 on device subsystem */ + rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif - return RT_EOK; + return RT_EOK; } /*@}*/ |