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-rw-r--r--libcpu/arm/dm36x/cpuport.c172
-rw-r--r--libcpu/arm/dm36x/mmu.c232
-rw-r--r--libcpu/arm/dm36x/mmu.h22
-rw-r--r--libcpu/arm/dm36x/stack.c2
4 files changed, 214 insertions, 214 deletions
diff --git a/libcpu/arm/dm36x/cpuport.c b/libcpu/arm/dm36x/cpuport.c
index f6e8a20056..fc80248528 100644
--- a/libcpu/arm/dm36x/cpuport.c
+++ b/libcpu/arm/dm36x/cpuport.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -11,8 +11,8 @@
#include <rthw.h>
#include <rtthread.h>
-#define ICACHE_MASK (rt_uint32_t)(1 << 12)
-#define DCACHE_MASK (rt_uint32_t)(1 << 2)
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
extern void machine_reset(void);
extern void machine_shutdown(void);
@@ -20,70 +20,70 @@ extern void machine_shutdown(void);
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
- rt_uint32_t i;
+ rt_uint32_t i;
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- return i;
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "orr r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
+ __asm__ __volatile__( \
+ "mrc p15,0,r0,c1,c0,0\n\t" \
+ "orr r0,r0,%0\n\t" \
+ "mcr p15,0,r0,c1,c0,0" \
+ : \
+ :"r" (bit) \
+ :"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "bic r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
+ __asm__ __volatile__( \
+ "mrc p15,0,r0,c1,c0,0\n\t" \
+ "bic r0,r0,%0\n\t" \
+ "mcr p15,0,r0,c1,c0,0" \
+ : \
+ :"r" (bit) \
+ :"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
- rt_uint32_t i;
+ rt_uint32_t i;
- __asm
- {
- mrc p15, 0, i, c1, c0, 0
- }
+ __asm
+ {
+ mrc p15, 0, i, c1, c0, 0
+ }
- return i;
+ return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
- rt_uint32_t value;
+ rt_uint32_t value;
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
+ __asm
+ {
+ mrc p15, 0, value, c1, c0, 0
+ orr value, value, bit
+ mcr p15, 0, value, c1, c0, 0
+ }
}
rt_inline void cache_disable(rt_uint32_t bit)
{
- rt_uint32_t value;
+ rt_uint32_t value;
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
+ __asm
+ {
+ mrc p15, 0, value, c1, c0, 0
+ bic value, value, bit
+ mcr p15, 0, value, c1, c0, 0
+ }
}
#endif
@@ -93,7 +93,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
*/
void rt_hw_cpu_icache_enable()
{
- cache_enable(ICACHE_MASK);
+ cache_enable(ICACHE_MASK);
}
/**
@@ -102,7 +102,7 @@ void rt_hw_cpu_icache_enable()
*/
void rt_hw_cpu_icache_disable()
{
- cache_disable(ICACHE_MASK);
+ cache_disable(ICACHE_MASK);
}
/**
@@ -111,7 +111,7 @@ void rt_hw_cpu_icache_disable()
*/
rt_base_t rt_hw_cpu_icache_status()
{
- return (cp15_rd() & ICACHE_MASK);
+ return (cp15_rd() & ICACHE_MASK);
}
/**
@@ -120,7 +120,7 @@ rt_base_t rt_hw_cpu_icache_status()
*/
void rt_hw_cpu_dcache_enable()
{
- cache_enable(DCACHE_MASK);
+ cache_enable(DCACHE_MASK);
}
/**
@@ -129,7 +129,7 @@ void rt_hw_cpu_dcache_enable()
*/
void rt_hw_cpu_dcache_disable()
{
- cache_disable(DCACHE_MASK);
+ cache_disable(DCACHE_MASK);
}
/**
@@ -138,7 +138,7 @@ void rt_hw_cpu_dcache_disable()
*/
rt_base_t rt_hw_cpu_dcache_status()
{
- return (cp15_rd() & DCACHE_MASK);
+ return (cp15_rd() & DCACHE_MASK);
}
/**
@@ -147,13 +147,13 @@ rt_base_t rt_hw_cpu_dcache_status()
*/
void rt_hw_cpu_reset()
{
-
- rt_kprintf("Restarting system...\n");
- machine_reset();
- while(1); /* loop forever and wait for reset to happen */
+ rt_kprintf("Restarting system...\n");
+ machine_reset();
- /* NEVER REACHED */
+ while(1); /* loop forever and wait for reset to happen */
+
+ /* NEVER REACHED */
}
/**
@@ -162,67 +162,67 @@ void rt_hw_cpu_reset()
*/
void rt_hw_cpu_shutdown()
{
- rt_uint32_t level;
- rt_kprintf("shutdown...\n");
+ rt_uint32_t level;
+ rt_kprintf("shutdown...\n");
- level = rt_hw_interrupt_disable();
- machine_shutdown();
- while (level)
- {
- RT_ASSERT(0);
- }
+ level = rt_hw_interrupt_disable();
+ machine_shutdown();
+ while (level)
+ {
+ RT_ASSERT(0);
+ }
}
#ifdef RT_USING_CPU_FFS
/**
- * This function finds the first bit set (beginning with the least significant bit)
+ * This function finds the first bit set (beginning with the least significant bit)
* in value and return the index of that bit.
*
- * Bits are numbered starting at 1 (the least significant bit). A return value of
+ * Bits are numbered starting at 1 (the least significant bit). A return value of
* zero from any of these functions means that the argument was zero.
- *
- * @return return the index of the first bit set. If value is 0, then this function
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
* shall return 0.
*/
#if defined(__CC_ARM)
int __rt_ffs(int value)
{
- register rt_uint32_t x;
+ register rt_uint32_t x;
+
+ if (value == 0)
+ return value;
- if (value == 0)
- return value;
-
- __asm
- {
- rsb x, value, #0
- and x, x, value
- clz x, x
- rsb x, x, #32
- }
+ __asm
+ {
+ rsb x, value, #0
+ and x, x, value
+ clz x, x
+ rsb x, x, #32
+ }
- return x;
+ return x;
}
#elif defined(__IAR_SYSTEMS_ICC__)
int __rt_ffs(int value)
{
- if (value == 0)
- return value;
+ if (value == 0)
+ return value;
- __ASM("RSB r4, r0, #0");
- __ASM("AND r4, r4, r0");
- __ASM("CLZ r4, r4");
- __ASM("RSB r0, r4, #32");
+ __ASM("RSB r4, r0, #0");
+ __ASM("AND r4, r4, r0");
+ __ASM("CLZ r4, r4");
+ __ASM("RSB r0, r4, #32");
}
#elif defined(__GNUC__)
int __rt_ffs(int value)
{
- if (value == 0)
- return value;
+ if (value == 0)
+ return value;
- value &= (-value);
- asm ("clz %0, %1": "=r"(value) :"r"(value));
+ value &= (-value);
+ asm ("clz %0, %1": "=r"(value) :"r"(value));
- return (32 - value);
+ return (32 - value);
}
#endif
diff --git a/libcpu/arm/dm36x/mmu.c b/libcpu/arm/dm36x/mmu.c
index abb2c1cd9e..bec2e6a71c 100644
--- a/libcpu/arm/dm36x/mmu.c
+++ b/libcpu/arm/dm36x/mmu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -12,22 +12,22 @@
#ifdef __CC_ARM
void mmu_setttbase(rt_uint32_t i)
{
- register rt_uint32_t value;
+ register rt_uint32_t value;
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
- value = 0;
+ value = 0;
__asm volatile
{
mcr p15, 0, value, c8, c7, 0
- }
+ }
- value = 0x55555555;
- __asm volatile
- {
+ value = 0x55555555;
+ __asm volatile
+ {
mcr p15, 0, value, c3, c0, 0
mcr p15, 0, i, c2, c0, 0
}
@@ -153,44 +153,44 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
while(ptr < buffer + size)
{
- __asm volatile
- {
- MCR p15, 0, ptr, c7, c14, 1
- }
+ __asm volatile
+ {
+ MCR p15, 0, ptr, c7, c14, 1
+ }
ptr += CACHE_LINE_SIZE;
}
}
void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
{
- unsigned int ptr;
+ unsigned int ptr;
- ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+ ptr = buffer & ~(CACHE_LINE_SIZE - 1);
- while (ptr < buffer + size)
- {
- __asm volatile
- {
- MCR p15, 0, ptr, c7, c10, 1
- }
- ptr += CACHE_LINE_SIZE;
- }
+ while (ptr < buffer + size)
+ {
+ __asm volatile
+ {
+ MCR p15, 0, ptr, c7, c10, 1
+ }
+ ptr += CACHE_LINE_SIZE;
+ }
}
void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
{
- unsigned int ptr;
+ unsigned int ptr;
- ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+ ptr = buffer & ~(CACHE_LINE_SIZE - 1);
- while (ptr < buffer + size)
- {
- __asm volatile
- {
- MCR p15, 0, ptr, c7, c6, 1
- }
- ptr += CACHE_LINE_SIZE;
- }
+ while (ptr < buffer + size)
+ {
+ __asm volatile
+ {
+ MCR p15, 0, ptr, c7, c6, 1
+ }
+ ptr += CACHE_LINE_SIZE;
+ }
}
void mmu_invalidate_tlb()
@@ -231,137 +231,137 @@ void mmu_invalidate_dcache_all()
#elif defined(__GNUC__)
void mmu_setttbase(register rt_uint32_t i)
{
- register rt_uint32_t value;
+ register rt_uint32_t value;
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
- value = 0;
- asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+ value = 0;
+ asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
- value = 0x55555555;
- asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
- asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+ value = 0x55555555;
+ asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+ asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
}
void mmu_set_domain(register rt_uint32_t i)
{
- asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
+ asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
}
void mmu_enable()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i |= 0x1;
- i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
- /* S R bit=1 0 for system protection */
- i |= (1 << 8);
- i &= ~(1 << 9);
+ i |= 0x1;
+ i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
+ /* S R bit=1 0 for system protection */
+ i |= (1 << 8);
+ i &= ~(1 << 9);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~0x1;
+ i &= ~0x1;
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_enable_icache()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i |= (1 << 12);
+ i |= (1 << 12);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_enable_dcache()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i |= (1 << 2);
+ i |= (1 << 2);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable_icache()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(1 << 12);
+ i &= ~(1 << 12);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable_dcache()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(1 << 2);
+ i &= ~(1 << 2);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_enable_alignfault()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i |= (1 << 1);
+ i |= (1 << 1);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable_alignfault()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(1 << 1);
+ i &= ~(1 << 1);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_clean_invalidated_cache_index(int index)
{
- asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+ asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
}
void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -372,7 +372,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
while(ptr < buffer + size)
{
- asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+ asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
ptr += CACHE_LINE_SIZE;
}
}
@@ -380,38 +380,38 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
{
- unsigned int ptr;
+ unsigned int ptr;
- ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+ ptr = buffer & ~(CACHE_LINE_SIZE - 1);
- while (ptr < buffer + size)
- {
- asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
- ptr += CACHE_LINE_SIZE;
- }
+ while (ptr < buffer + size)
+ {
+ asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+ ptr += CACHE_LINE_SIZE;
+ }
}
void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
{
- unsigned int ptr;
+ unsigned int ptr;
- ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+ ptr = buffer & ~(CACHE_LINE_SIZE - 1);
- while (ptr < buffer + size)
- {
- asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
- ptr += CACHE_LINE_SIZE;
- }
+ while (ptr < buffer + size)
+ {
+ asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+ ptr += CACHE_LINE_SIZE;
+ }
}
void mmu_invalidate_tlb()
{
- asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+ asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
}
void mmu_invalidate_icache()
{
- asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+ asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
}
void mmu_invalidate_dcache_all()
@@ -462,13 +462,13 @@ void mmu_create_pte(struct mem_desc *mdesc)
if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */
{
*pTT = pte_offset | sect_attr;
- p_pteentry = (rt_uint32_t *)pte_offset +
+ p_pteentry = (rt_uint32_t *)pte_offset +
((vaddr & 0x000ff000) >> 12);
pte_offset += 1024;
}
else /* using old Level 1 page table item */
{
- p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
+ p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
((vaddr & 0x000ff000) >> 12);
}
@@ -503,13 +503,13 @@ static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size)
void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
{
- /* disable I/D cache */
- mmu_disable_dcache();
- mmu_disable_icache();
- mmu_disable();
- mmu_invalidate_tlb();
+ /* disable I/D cache */
+ mmu_disable_dcache();
+ mmu_disable_icache();
+ mmu_disable();
+ mmu_invalidate_tlb();
- /* clear pgd and pte table */
+ /* clear pgd and pte table */
rt_memset((void *)_pgd_table, 0, 16*1024);
rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE);
build_pte_mem_desc(mdesc, size);
diff --git a/libcpu/arm/dm36x/mmu.h b/libcpu/arm/dm36x/mmu.h
index 3410b881ac..60a4e3c6e9 100644
--- a/libcpu/arm/dm36x/mmu.h
+++ b/libcpu/arm/dm36x/mmu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -12,7 +12,7 @@
#include <rtthread.h>
-#define CACHE_LINE_SIZE 32
+#define CACHE_LINE_SIZE 32
/*
* Hardware page table definitions.
@@ -30,7 +30,7 @@
/*
* - section
*/
-#define PGD_SECT_BUFFERABLE (1 << 2)
+#define PGD_SECT_BUFFERABLE (1 << 2)
#define PGD_SECT_CACHEABLE (1 << 3)
#define PGD_SECT_XN (1 << 4) /* ARMv6 */
#define PGD_SECT_AP0 (1 << 10)
@@ -133,14 +133,14 @@
#define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */
struct mem_desc {
- rt_uint32_t vaddr_start;
- rt_uint32_t vaddr_end;
- rt_uint32_t paddr_start;
- rt_uint32_t sect_attr; /* when page mapped */
- rt_uint32_t page_attr; /* only sector mapped valid */
- rt_uint32_t mapped_mode;
- #define SECT_MAPPED 0
- #define PAGE_MAPPED 1
+ rt_uint32_t vaddr_start;
+ rt_uint32_t vaddr_end;
+ rt_uint32_t paddr_start;
+ rt_uint32_t sect_attr; /* when page mapped */
+ rt_uint32_t page_attr; /* only sector mapped valid */
+ rt_uint32_t mapped_mode;
+ #define SECT_MAPPED 0
+ #define PAGE_MAPPED 1
};
diff --git a/libcpu/arm/dm36x/stack.c b/libcpu/arm/dm36x/stack.c
index 9d7385b9c8..e725d060c1 100644
--- a/libcpu/arm/dm36x/stack.c
+++ b/libcpu/arm/dm36x/stack.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-24 03:33:36 +0000