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-rw-r--r--libcpu/arm/s3c24x0/cpu.c126
-rw-r--r--libcpu/arm/s3c24x0/interrupt.c30
-rw-r--r--libcpu/arm/s3c24x0/mmu.c242
-rw-r--r--libcpu/arm/s3c24x0/rtc.c206
-rw-r--r--libcpu/arm/s3c24x0/rtc.h2
-rw-r--r--libcpu/arm/s3c24x0/s3c24x0.h78
-rw-r--r--libcpu/arm/s3c24x0/stack.c2
-rw-r--r--libcpu/arm/s3c24x0/system_clock.c108
-rw-r--r--libcpu/arm/s3c24x0/trap.c62
9 files changed, 428 insertions, 428 deletions
diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c
index 4d3bf3c1ab..ac4037c7b8 100644
--- a/libcpu/arm/s3c24x0/cpu.c
+++ b/libcpu/arm/s3c24x0/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -17,76 +17,76 @@
*/
/*@{*/
-#define ICACHE_MASK (rt_uint32_t)(1 << 12)
-#define DCACHE_MASK (rt_uint32_t)(1 << 2)
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
- rt_uint32_t i;
+ rt_uint32_t i;
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- return i;
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "orr r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
+ __asm__ __volatile__( \
+ "mrc p15,0,r0,c1,c0,0\n\t" \
+ "orr r0,r0,%0\n\t" \
+ "mcr p15,0,r0,c1,c0,0" \
+ : \
+ :"r" (bit) \
+ :"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "bic r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
+ __asm__ __volatile__( \
+ "mrc p15,0,r0,c1,c0,0\n\t" \
+ "bic r0,r0,%0\n\t" \
+ "mcr p15,0,r0,c1,c0,0" \
+ : \
+ :"r" (bit) \
+ :"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
- rt_uint32_t i;
+ rt_uint32_t i;
- __asm
- {
- mrc p15, 0, i, c1, c0, 0
- }
+ __asm
+ {
+ mrc p15, 0, i, c1, c0, 0
+ }
- return i;
+ return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
- rt_uint32_t value;
+ rt_uint32_t value;
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
+ __asm
+ {
+ mrc p15, 0, value, c1, c0, 0
+ orr value, value, bit
+ mcr p15, 0, value, c1, c0, 0
+ }
}
rt_inline void cache_disable(rt_uint32_t bit)
{
- rt_uint32_t value;
+ rt_uint32_t value;
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
+ __asm
+ {
+ mrc p15, 0, value, c1, c0, 0
+ bic value, value, bit
+ mcr p15, 0, value, c1, c0, 0
+ }
}
#endif
@@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
*/
void rt_hw_cpu_icache_enable()
{
- cache_enable(ICACHE_MASK);
+ cache_enable(ICACHE_MASK);
}
/**
@@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable()
*/
void rt_hw_cpu_icache_disable()
{
- cache_disable(ICACHE_MASK);
+ cache_disable(ICACHE_MASK);
}
/**
@@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable()
*/
rt_base_t rt_hw_cpu_icache_status()
{
- return (cp15_rd() & ICACHE_MASK);
+ return (cp15_rd() & ICACHE_MASK);
}
/**
@@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status()
*/
void rt_hw_cpu_dcache_enable()
{
- cache_enable(DCACHE_MASK);
+ cache_enable(DCACHE_MASK);
}
/**
@@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable()
*/
void rt_hw_cpu_dcache_disable()
{
- cache_disable(DCACHE_MASK);
+ cache_disable(DCACHE_MASK);
}
/**
@@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable()
*/
rt_base_t rt_hw_cpu_dcache_status()
{
- return (cp15_rd() & DCACHE_MASK);
+ return (cp15_rd() & DCACHE_MASK);
}
/**
@@ -150,21 +150,21 @@ rt_base_t rt_hw_cpu_dcache_status()
*/
void rt_hw_cpu_reset()
{
- /* Disable all interrupt except the WDT */
- INTMSK = (~((rt_uint32_t)1 << INTWDT));
+ /* Disable all interrupt except the WDT */
+ INTMSK = (~((rt_uint32_t)1 << INTWDT));
- /* Disable watchdog */
- WTCON = 0x0000;
+ /* Disable watchdog */
+ WTCON = 0x0000;
- /* Initialize watchdog timer count register */
- WTCNT = 0x0001;
+ /* Initialize watchdog timer count register */
+ WTCNT = 0x0001;
- /* Enable watchdog timer; assert reset at timer timeout */
- WTCON = 0x0021;
+ /* Enable watchdog timer; assert reset at timer timeout */
+ WTCON = 0x0021;
- while(1); /* loop forever and wait for reset to happen */
+ while(1); /* loop forever and wait for reset to happen */
- /* NEVER REACHED */
+ /* NEVER REACHED */
}
/**
@@ -173,14 +173,14 @@ void rt_hw_cpu_reset()
*/
void rt_hw_cpu_shutdown()
{
- rt_uint32_t level;
- rt_kprintf("shutdown...\n");
+ rt_uint32_t level;
+ rt_kprintf("shutdown...\n");
- level = rt_hw_interrupt_disable();
- while (level)
- {
- RT_ASSERT(0);
- }
+ level = rt_hw_interrupt_disable();
+ while (level)
+ {
+ RT_ASSERT(0);
+ }
}
/*@}*/
diff --git a/libcpu/arm/s3c24x0/interrupt.c b/libcpu/arm/s3c24x0/interrupt.c
index 8c7aebeb25..c985fc7c86 100644
--- a/libcpu/arm/s3c24x0/interrupt.c
+++ b/libcpu/arm/s3c24x0/interrupt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -13,7 +13,7 @@
#include <rthw.h>
#include "s3c24x0.h"
-#define MAX_HANDLERS 32
+#define MAX_HANDLERS 32
extern rt_uint32_t rt_interrupt_nest;
@@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
static void rt_hw_interrupt_handle(int vector, void *param)
{
- rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+ rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
@@ -77,7 +77,7 @@ void rt_hw_interrupt_init(void)
*/
void rt_hw_interrupt_mask(int vector)
{
- INTMSK |= 1 << vector;
+ INTMSK |= 1 << vector;
}
/**
@@ -86,15 +86,15 @@ void rt_hw_interrupt_mask(int vector)
*/
void rt_hw_interrupt_umask(int vector)
{
- if (vector == INTNOTUSED6)
- {
- rt_kprintf("Interrupt vec %d is not used!\n", vector);
- // while(1);
- }
- else if (vector == INTGLOBAL)
- INTMSK = 0x0;
- else
- INTMSK &= ~(1 << vector);
+ if (vector == INTNOTUSED6)
+ {
+ rt_kprintf("Interrupt vec %d is not used!\n", vector);
+ // while(1);
+ }
+ else if (vector == INTGLOBAL)
+ INTMSK = 0x0;
+ else
+ INTMSK &= ~(1 << vector);
}
/**
@@ -115,9 +115,9 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
- rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+ rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
- isr_table[vector].handler = handler;
+ isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c
index dc993ec9a3..4e5ef8d3c6 100644
--- a/libcpu/arm/s3c24x0/mmu.c
+++ b/libcpu/arm/s3c24x0/mmu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -12,158 +12,158 @@
#include <rtthread.h>
#include "s3c24x0.h"
-#define _MMUTT_STARTADDRESS 0x33FF0000
+#define _MMUTT_STARTADDRESS 0x33FF0000
-#define DESC_SEC (0x2|(1<<4))
-#define CB (3<<2) //cache_on, write_back
-#define CNB (2<<2) //cache_on, write_through
-#define NCB (1<<2) //cache_off,WR_BUF on
-#define NCNB (0<<2) //cache_off,WR_BUF off
-#define AP_RW (3<<10) //supervisor=RW, user=RW
-#define AP_RO (2<<10) //supervisor=RW, user=RO
+#define DESC_SEC (0x2|(1<<4))
+#define CB (3<<2) //cache_on, write_back
+#define CNB (2<<2) //cache_on, write_through
+#define NCB (1<<2) //cache_off,WR_BUF on
+#define NCNB (0<<2) //cache_off,WR_BUF off
+#define AP_RW (3<<10) //supervisor=RW, user=RW
+#define AP_RO (2<<10) //supervisor=RW, user=RO
-#define DOMAIN_FAULT (0x0)
-#define DOMAIN_CHK (0x1)
-#define DOMAIN_NOTCHK (0x3)
-#define DOMAIN0 (0x0<<5)
-#define DOMAIN1 (0x1<<5)
+#define DOMAIN_FAULT (0x0)
+#define DOMAIN_CHK (0x1)
+#define DOMAIN_NOTCHK (0x3)
+#define DOMAIN0 (0x0<<5)
+#define DOMAIN1 (0x1<<5)
-#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
+#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
-#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
-#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
-#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
-#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
+#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
+#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
+#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
#ifdef __GNUC__
void mmu_setttbase(register rt_uint32_t i)
{
- asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));
+ asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));
}
void mmu_set_domain(register rt_uint32_t i)
{
- asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
+ asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
}
void mmu_enable()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i |= 0x1;
+ i |= 0x1;
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~0x1;
+ i &= ~0x1;
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_enable_icache()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i |= (1 << 12);
+ i |= (1 << 12);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_enable_dcache()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i |= (1 << 2);
+ i |= (1 << 2);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable_icache()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(1 << 12);
+ i &= ~(1 << 12);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable_dcache()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(1 << 2);
+ i &= ~(1 << 2);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_enable_alignfault()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i |= (1 << 1);
+ i |= (1 << 1);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable_alignfault()
{
- register rt_uint32_t i;
+ register rt_uint32_t i;
- /* read control register */
- asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ /* read control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(1 << 1);
+ i &= ~(1 << 1);
- /* write back to control register */
- asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* write back to control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_clean_invalidated_cache_index(int index)
{
- asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+ asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
}
void mmu_invalidate_tlb()
{
- asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+ asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
}
void mmu_invalidate_icache()
{
- asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+ asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
}
#endif
@@ -320,71 +320,71 @@ void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
nSec=(vaddrEnd>>20)-(vaddrStart>>20);
for(i=0;i<=nSec;i++)
{
- *pTT = attr |(((paddrStart>>20)+i)<<20);
- pTT++;
+ *pTT = attr |(((paddrStart>>20)+i)<<20);
+ pTT++;
}
}
void rt_hw_mmu_init(void)
{
- int i,j;
- //========================== IMPORTANT NOTE =========================
- //The current stack and code area can't be re-mapped in this routine.
- //If you want memory map mapped freely, your own sophiscated mmu
- //initialization code is needed.
- //===================================================================
+ int i,j;
+ //========================== IMPORTANT NOTE =========================
+ //The current stack and code area can't be re-mapped in this routine.
+ //If you want memory map mapped freely, your own sophiscated mmu
+ //initialization code is needed.
+ //===================================================================
- mmu_disable_dcache();
- mmu_disable_icache();
+ mmu_disable_dcache();
+ mmu_disable_icache();
- //If write-back is used,the DCache should be cleared.
- for(i=0;i<64;i++)
- for(j=0;j<8;j++)
- mmu_clean_invalidated_cache_index((i<<26)|(j<<5));
+ //If write-back is used,the DCache should be cleared.
+ for(i=0;i<64;i++)
+ for(j=0;j<8;j++)
+ mmu_clean_invalidated_cache_index((i<<26)|(j<<5));
- mmu_invalidate_icache();
+ mmu_invalidate_icache();
- //To complete mmu_Init() fast, Icache may be turned on here.
- mmu_enable_icache();
+ //To complete mmu_Init() fast, Icache may be turned on here.
+ mmu_enable_icache();
- mmu_disable();
- mmu_invalidate_tlb();
+ mmu_disable();
+ mmu_invalidate_tlb();
- //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
- mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
- mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0
- mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0
- mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
- mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
- mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
- //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
- mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000
- mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
- //30f00000->30100000, 31000000->30200000
- mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
- mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2
+ //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
+ mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
+ mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0
+ mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0
+ mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
+ mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
+ mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
+ //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
+ mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000
+ mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
+ //30f00000->30100000, 31000000->30200000
+ mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
+ mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2
- mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3
- mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
+ mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3
+ mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
- mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
- mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
- mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
- mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
- mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR
+ mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
+ mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
+ mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
+ mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
+ mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR
- mmu_setttbase(_MMUTT_STARTADDRESS);
+ mmu_setttbase(_MMUTT_STARTADDRESS);
- /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
- mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
+ /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
+ mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
- mmu_enable_alignfault();
+ mmu_enable_alignfault();
- mmu_enable();
+ mmu_enable();
- /* ICache enable */
- mmu_enable_icache();
- /* DCache should be turned on after mmu is turned on. */
- mmu_enable_dcache();
+ /* ICache enable */
+ mmu_enable_icache();
+ /* DCache should be turned on after mmu is turned on. */
+ mmu_enable_dcache();
}
diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c
index d0c80bce6b..653bb09f77 100644
--- a/libcpu/arm/s3c24x0/rtc.c
+++ b/libcpu/arm/s3c24x0/rtc.c
@@ -1,14 +1,14 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
- * 2009-04-26 yi.qiu first version
- * 2010-03-18 Gary Lee add functions such as GregorianDay
- * and rtc_time_to_tm
- * 2009-03-20 yi.qiu clean up
+ * 2009-04-26 yi.qiu first version
+ * 2010-03-18 Gary Lee add functions such as GregorianDay
+ * and rtc_time_to_tm
+ * 2009-03-20 yi.qiu clean up
*/
#include <rtthread.h>
@@ -17,50 +17,50 @@
// #define RTC_DEBUG
-#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */
-#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */
-#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F))
-#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10))
+#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */
+#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */
+#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F))
+#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10))
/**
* This function get rtc time
*/
void rt_hw_rtc_get(struct tm *ti)
{
- rt_uint8_t sec, min, hour, mday, wday, mon, year;
+ rt_uint8_t sec, min, hour, mday, wday, mon, year;
- /* enable access to RTC registers */
- RTCCON |= RTC_ENABLE;
+ /* enable access to RTC registers */
+ RTCCON |= RTC_ENABLE;
- /* read RTC registers */
- do
- {
- sec = BCDSEC;
- min = BCDMIN;
- hour = BCDHOUR;
- mday = BCDDATE;
- wday = BCDDAY;
- mon = BCDMON;
- year = BCDYEAR;
+ /* read RTC registers */
+ do
+ {
+ sec = BCDSEC;
+ min = BCDMIN;
+ hour = BCDHOUR;
+ mday = BCDDATE;
+ wday = BCDDAY;
+ mon = BCDMON;
+ year = BCDYEAR;
} while (sec != BCDSEC);
#ifdef RTC_DEBUG
- rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n",
- sec, min, hour, mday, wday, mon, year);
+ rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n",
+ sec, min, hour, mday, wday, mon, year);
#endif
- /* disable access to RTC registers */
- RTC_DISABLE
+ /* disable access to RTC registers */
+ RTC_DISABLE
- ti->tm_sec = BCD2BIN(sec & 0x7F);
- ti->tm_min = BCD2BIN(min & 0x7F);
- ti->tm_hour = BCD2BIN(hour & 0x3F);
- ti->tm_mday = BCD2BIN(mday & 0x3F);
- ti->tm_mon = BCD2BIN(mon & 0x1F);
- ti->tm_year = BCD2BIN(year);
- ti->tm_wday = BCD2BIN(wday & 0x07);
- ti->tm_yday = 0;
- ti->tm_isdst = 0;
+ ti->tm_sec = BCD2BIN(sec & 0x7F);
+ ti->tm_min = BCD2BIN(min & 0x7F);
+ ti->tm_hour = BCD2BIN(hour & 0x3F);
+ ti->tm_mday = BCD2BIN(mday & 0x3F);
+ ti->tm_mon = BCD2BIN(mon & 0x1F);
+ ti->tm_year = BCD2BIN(year);
+ ti->tm_wday = BCD2BIN(wday & 0x07);
+ ti->tm_yday = 0;
+ ti->tm_isdst = 0;
}
/**
@@ -68,32 +68,32 @@ void rt_hw_rtc_get(struct tm *ti)
*/
void rt_hw_rtc_set(struct tm *ti)
{
- rt_uint8_t sec, min, hour, mday, wday, mon, year;
+ rt_uint8_t sec, min, hour, mday, wday, mon, year;
- year = BIN2BCD(ti->tm_year);
- mon = BIN2BCD(ti->tm_mon);
- wday = BIN2BCD(ti->tm_wday);
- mday = BIN2BCD(ti->tm_mday);
- hour = BIN2BCD(ti->tm_hour);
- min = BIN2BCD(ti->tm_min);
- sec = BIN2BCD(ti->tm_sec);
+ year = BIN2BCD(ti->tm_year);
+ mon = BIN2BCD(ti->tm_mon);
+ wday = BIN2BCD(ti->tm_wday);
+ mday = BIN2BCD(ti->tm_mday);
+ hour = BIN2BCD(ti->tm_hour);
+ min = BIN2BCD(ti->tm_min);
+ sec = BIN2BCD(ti->tm_sec);
- /* enable access to RTC registers */
- RTC_ENABLE
+ /* enable access to RTC registers */
+ RTC_ENABLE
- do{
- /* write RTC registers */
- BCDSEC = sec;
- BCDMIN = min;
- BCDHOUR = hour;
- BCDDATE = mday;
- BCDDAY = wday;
- BCDMON = mon;
- BCDYEAR = year;
- }while (sec != BCDSEC);
-
- /* disable access to RTC registers */
- RTC_DISABLE
+ do{
+ /* write RTC registers */
+ BCDSEC = sec;
+ BCDMIN = min;
+ BCDHOUR = hour;
+ BCDDATE = mday;
+ BCDDAY = wday;
+ BCDMON = mon;
+ BCDYEAR = year;
+ }while (sec != BCDSEC);
+
+ /* disable access to RTC registers */
+ RTC_DISABLE
}
/**
@@ -101,85 +101,85 @@ void rt_hw_rtc_set(struct tm *ti)
*/
void rt_hw_rtc_reset (void)
{
- RTCCON = (RTCCON & ~0x06) | 0x08;
- RTCCON &= ~(0x08|0x01);
+ RTCCON = (RTCCON & ~0x06) | 0x08;
+ RTCCON &= ~(0x08|0x01);
}
static struct rt_device rtc;
static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag)
{
- RTC_ENABLE
- return RT_EOK;
+ RTC_ENABLE
+ return RT_EOK;
}
static rt_err_t rtc_close(rt_device_t dev)
{
- RTC_DISABLE
- return RT_EOK;
+ RTC_DISABLE
+ return RT_EOK;
}
static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args)
{
- struct tm tm, *tm_ptr;
+ struct tm tm, *tm_ptr;
time_t *time;
- RT_ASSERT(dev != RT_NULL);
+ RT_ASSERT(dev != RT_NULL);
- time = (time_t *)args;
- switch (cmd)
- {
- case RT_DEVICE_CTRL_RTC_GET_TIME:
- /* read device */
- rt_hw_rtc_get(&tm);
- *((rt_time_t *)args) = mktime(&tm);
- break;
+ time = (time_t *)args;
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_RTC_GET_TIME:
+ /* read device */
+ rt_hw_rtc_get(&tm);
+ *((rt_time_t *)args) = mktime(&tm);
+ break;
- case RT_DEVICE_CTRL_RTC_SET_TIME:
- tm_ptr = localtime(time);
- /* write device */
- rt_hw_rtc_set(tm_ptr);
- break;
- }
+ case RT_DEVICE_CTRL_RTC_SET_TIME:
+ tm_ptr = localtime(time);
+ /* write device */
+ rt_hw_rtc_set(tm_ptr);
+ break;
+ }
- return RT_EOK;
+ return RT_EOK;
}
void rt_hw_rtc_init(void)
{
- rtc.type = RT_Device_Class_RTC;
+ rtc.type = RT_Device_Class_RTC;
+
+ /* register rtc device */
+ rtc.init = RT_NULL;
+ rtc.open = rtc_open;
+ rtc.close = rtc_close;
+ rtc.read = rtc_read;
+ rtc.write = RT_NULL;
+ rtc.control = rtc_control;
+
+ /* no private */
+ rtc.user_data = RT_NULL;
- /* register rtc device */
- rtc.init = RT_NULL;
- rtc.open = rtc_open;
- rtc.close = rtc_close;
- rtc.read = rtc_read;
- rtc.write = RT_NULL;
- rtc.control = rtc_control;
-
- /* no private */
- rtc.user_data = RT_NULL;
-
- rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
+ rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
}
#ifdef RT_USING_FINSH
#include <finsh.h>
void list_date()
{
- time_t time;
- rt_device_t device;
+ time_t time;
+ rt_device_t device;
- device = rt_device_find("rtc");
- if (device != RT_NULL)
- {
- rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time);
+ device = rt_device_find("rtc");
+ if (device != RT_NULL)
+ {
+ rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time);
- rt_kprintf("%d, %s\n", time, ctime(&time));
- }
+ rt_kprintf("%d, %s\n", time, ctime(&time));
+ }
}
FINSH_FUNCTION_EXPORT(list_date, list date);
#endif
diff --git a/libcpu/arm/s3c24x0/rtc.h b/libcpu/arm/s3c24x0/rtc.h
index aafa714b0e..78219325a5 100644
--- a/libcpu/arm/s3c24x0/rtc.h
+++ b/libcpu/arm/s3c24x0/rtc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/libcpu/arm/s3c24x0/s3c24x0.h b/libcpu/arm/s3c24x0/s3c24x0.h
index 03749c5227..75e1eb0119 100644
--- a/libcpu/arm/s3c24x0/s3c24x0.h
+++ b/libcpu/arm/s3c24x0/s3c24x0.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -22,7 +22,7 @@ extern "C" {
*/
/*@{*/
-// Memory control
+// Memory control
#define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status
#define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
#define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
@@ -101,7 +101,7 @@ extern "C" {
#define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control
#define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control
#define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control
-#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
+#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
// LCD CONTROLLER
@@ -114,7 +114,7 @@ extern "C" {
#define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2
#define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set
#define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table
-#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table
+#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table
#define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table
#define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode
#define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette
@@ -223,10 +223,10 @@ extern "C" {
#define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4
// Added for 2440
-#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only)
-#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0
-#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1
-#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register
+#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only)
+#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0
+#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1
+#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register
// USB DEVICE
@@ -388,9 +388,9 @@ extern "C" {
#define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data
#define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
-#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control
-#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data
-#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J
+#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control
+#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data
+#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J
#define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
#define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
@@ -495,7 +495,7 @@ extern "C" {
#ifdef __BIG_ENDIAN /* edited for 2440A */
#define SDIDAT (*(volatile unsigned *)0x5a00004c)
#else // Little Endian
-#define SDIDAT (*(volatile unsigned *)0x5a000040)
+#define SDIDAT (*(volatile unsigned *)0x5a000040)
#endif //SD Interface
// PENDING BIT
@@ -562,40 +562,40 @@ extern "C" {
#define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;}
//Wait until INTPND is changed for the case that the ISR is very short.
-#define INTGLOBAL 32
+#define INTGLOBAL 32
/*****************************/
/* CPU Mode */
/*****************************/
-#define USERMODE 0x10
-#define FIQMODE 0x11
-#define IRQMODE 0x12
-#define SVCMODE 0x13
-#define ABORTMODE 0x17
-#define UNDEFMODE 0x1b
-#define MODEMASK 0x1f
-#define NOINT 0xc0
+#define USERMODE 0x10
+#define FIQMODE 0x11
+#define IRQMODE 0x12
+#define SVCMODE 0x13
+#define ABORTMODE 0x17
+#define UNDEFMODE 0x1b
+#define MODEMASK 0x1f
+#define NOINT 0xc0
struct rt_hw_register
{
- rt_uint32_t r0;
- rt_uint32_t r1;
- rt_uint32_t r2;
- rt_uint32_t r3;
- rt_uint32_t r4;
- rt_uint32_t r5;
- rt_uint32_t r6;
- rt_uint32_t r7;
- rt_uint32_t r8;
- rt_uint32_t r9;
- rt_uint32_t r10;
- rt_uint32_t fp;
- rt_uint32_t ip;
- rt_uint32_t sp;
- rt_uint32_t lr;
- rt_uint32_t pc;
- rt_uint32_t cpsr;
- rt_uint32_t ORIG_r0;
+ rt_uint32_t r0;
+ rt_uint32_t r1;
+ rt_uint32_t r2;
+ rt_uint32_t r3;
+ rt_uint32_t r4;
+ rt_uint32_t r5;
+ rt_uint32_t r6;
+ rt_uint32_t r7;
+ rt_uint32_t r8;
+ rt_uint32_t r9;
+ rt_uint32_t r10;
+ rt_uint32_t fp;
+ rt_uint32_t ip;
+ rt_uint32_t sp;
+ rt_uint32_t lr;
+ rt_uint32_t pc;
+ rt_uint32_t cpsr;
+ rt_uint32_t ORIG_r0;
};
#ifdef __cplusplus
diff --git a/libcpu/arm/s3c24x0/stack.c b/libcpu/arm/s3c24x0/stack.c
index 82607c3590..99938e2317 100644
--- a/libcpu/arm/s3c24x0/stack.c
+++ b/libcpu/arm/s3c24x0/stack.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/libcpu/arm/s3c24x0/system_clock.c b/libcpu/arm/s3c24x0/system_clock.c
index 833b193cce..235c5e5e5c 100644
--- a/libcpu/arm/s3c24x0/system_clock.c
+++ b/libcpu/arm/s3c24x0/system_clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -11,21 +11,21 @@
#include <rtthread.h>
#include "s3c24x0.h"
-#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
+#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
#if CONFIG_SYS_CLK_FREQ == 12000000
- /* MPLL=2*12*100/6=400MHz */
- #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
- #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
- #define MPL_SDIV 0 /* s=MPL_SDIV=0 */
- /* UPLL=12*64/8=96MHz */
- #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
- #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
- #define UPL_SDIV 1 /* s=UPL_SDIV=1 */
- /* System clock divider FCLK:HCLK:PCLK=1:4:8 */
- #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
- #define HDIVN 0x2 /* HCLK = FCLK / 4 */
- #define PDIVN 0x1 /* PCLK = HCLK / 2 */
+ /* MPLL=2*12*100/6=400MHz */
+ #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
+ #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
+ #define MPL_SDIV 0 /* s=MPL_SDIV=0 */
+ /* UPLL=12*64/8=96MHz */
+ #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
+ #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
+ #define UPL_SDIV 1 /* s=UPL_SDIV=1 */
+ /* System clock divider FCLK:HCLK:PCLK=1:4:8 */
+ #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
+ #define HDIVN 0x2 /* HCLK = FCLK / 4 */
+ #define PDIVN 0x1 /* PCLK = HCLK / 2 */
#endif
rt_uint32_t PCLK;
@@ -35,60 +35,60 @@ rt_uint32_t UCLK;
void rt_hw_get_clock(void)
{
- rt_uint32_t val;
- rt_uint8_t m, p, s;
+ rt_uint32_t val;
+ rt_uint8_t m, p, s;
- val = MPLLCON;
- m = (val>>12)&0xff;
- p = (val>>4)&0x3f;
- s = val&3;
+ val = MPLLCON;
+ m = (val>>12)&0xff;
+ p = (val>>4)&0x3f;
+ s = val&3;
- FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100;
+ FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100;
- val = CLKDIVN;
- m = (val>>1)&3;
- p = val&1;
+ val = CLKDIVN;
+ m = (val>>1)&3;
+ p = val&1;
- switch (m) {
- case 0:
- HCLK = FCLK;
- break;
- case 1:
- HCLK = FCLK>>1;
- break;
- case 2:
- if(s&2)
- HCLK = FCLK>>3;
- else
- HCLK = FCLK>>2;
- break;
- case 3:
- if(s&1)
- HCLK = FCLK/6;
- else
- HCLK = FCLK/3;
- break;
+ switch (m) {
+ case 0:
+ HCLK = FCLK;
+ break;
+ case 1:
+ HCLK = FCLK>>1;
+ break;
+ case 2:
+ if(s&2)
+ HCLK = FCLK>>3;
+ else
+ HCLK = FCLK>>2;
+ break;
+ case 3:
+ if(s&1)
+ HCLK = FCLK/6;
+ else
+ HCLK = FCLK/3;
+ break;
}
- if(p)
- PCLK = HCLK>>1;
- else
- PCLK = HCLK;
+ if(p)
+ PCLK = HCLK>>1;
+ else
+ PCLK = HCLK;
}
void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
- MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
+ MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
}
void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
- UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
+ UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}
void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
{
- CLKDIVN = (hdivn<<1) | pdivn;
+ CLKDIVN = (hdivn<<1) | pdivn;
}
/**
@@ -96,9 +96,9 @@ void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
*/
void rt_hw_clock_init(void)
{
- LOCKTIME = 0xFFFFFFFF;
- rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
- rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
- rt_hw_set_divider(HDIVN, PDIVN);
+ LOCKTIME = 0xFFFFFFFF;
+ rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
+ rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
+ rt_hw_set_divider(HDIVN, PDIVN);
}
diff --git a/libcpu/arm/s3c24x0/trap.c b/libcpu/arm/s3c24x0/trap.c
index f2f389c6b0..f0e8a7097a 100644
--- a/libcpu/arm/s3c24x0/trap.c
+++ b/libcpu/arm/s3c24x0/trap.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -34,13 +34,13 @@ extern long list_thread(void);
void rt_hw_show_register (struct rt_hw_register *regs)
{
- rt_kprintf("Execption:\n");
- rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
- rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
- rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
- rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
- rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
- rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+ rt_kprintf("Execption:\n");
+ rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+ rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+ rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+ rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+ rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+ rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
}
/**
@@ -53,15 +53,15 @@ void rt_hw_show_register (struct rt_hw_register *regs)
*/
void rt_hw_trap_udef(struct rt_hw_register *regs)
{
- rt_hw_show_register(regs);
+ rt_hw_show_register(regs);
- rt_kprintf("undefined instruction\n");
- rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+ rt_kprintf("undefined instruction\n");
+ rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
#ifdef RT_USING_FINSH
- list_thread();
+ list_thread();
#endif
- rt_hw_cpu_shutdown();
+ rt_hw_cpu_shutdown();
}
/**
@@ -75,10 +75,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
*/
void rt_hw_trap_swi(struct rt_hw_register *regs)
{
- rt_hw_show_register(regs);
+ rt_hw_show_register(regs);
- rt_kprintf("software interrupt\n");
- rt_hw_cpu_shutdown();
+ rt_kprintf("software interrupt\n");
+ rt_hw_cpu_shutdown();
}
/**
@@ -91,15 +91,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
*/
void rt_hw_trap_pabt(struct rt_hw_register *regs)
{
- rt_hw_show_register(regs);
+ rt_hw_show_register(regs);
- rt_kprintf("prefetch abort\n");
- rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+ rt_kprintf("prefetch abort\n");
+ rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
#ifdef RT_USING_FINSH
- list_thread();
+ list_thread();
#endif
- rt_hw_cpu_shutdown();
+ rt_hw_cpu_shutdown();
}
/**
@@ -112,15 +112,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
*/
void rt_hw_trap_dabt(struct rt_hw_register *regs)
{
- rt_hw_show_register(regs);
+ rt_hw_show_register(regs);
- rt_kprintf("data abort\n");
- rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+ rt_kprintf("data abort\n");
+ rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
#ifdef RT_USING_FINSH
- list_thread();
+ list_thread();
#endif
- rt_hw_cpu_shutdown();
+ rt_hw_cpu_shutdown();
}
/**
@@ -132,9 +132,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
*/
void rt_hw_trap_resv(struct rt_hw_register *regs)
{
- rt_kprintf("not used\n");
- rt_hw_show_register(regs);
- rt_hw_cpu_shutdown();
+ rt_kprintf("not used\n");
+ rt_hw_show_register(regs);
+ rt_hw_cpu_shutdown();
}
extern struct rt_irq_desc isr_table[];
@@ -161,13 +161,13 @@ void rt_hw_trap_irq(void)
ClearPending(1 << irq);
#ifdef RT_USING_INTERRUPT_INFO
- isr_table[irq].counter++;
+ isr_table[irq].counter++;
#endif /* RT_USING_INTERRUPT_INFO */
}
void rt_hw_trap_fiq(void)
{
- rt_kprintf("fast interrupt request\n");
+ rt_kprintf("fast interrupt request\n");
}
/*@}*/
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-24 02:09:21 +0000