diff options
Diffstat (limited to 'libcpu/xilinx/microblaze/trap.c')
| -rwxr-xr-x | libcpu/xilinx/microblaze/trap.c | 180 |
1 files changed, 90 insertions, 90 deletions
diff --git a/libcpu/xilinx/microblaze/trap.c b/libcpu/xilinx/microblaze/trap.c index 3b3f98d105..bcfb3cc492 100755 --- a/libcpu/xilinx/microblaze/trap.c +++ b/libcpu/xilinx/microblaze/trap.c @@ -10,13 +10,13 @@ * Change Logs: * Date Author Notes * 2006-08-23 Bernard first version - * 2011-12-17 nl1031 for MicroBlaze + * 2011-12-17 nl1031 for MicroBlaze * */ -#include <rtthread.h> -#include "xparameters.h" -#include "xintc.h" +#include <rtthread.h> +#include "xparameters.h" +#include "xintc.h" #include "xintc_i.h" #include "xintc_l.h" @@ -33,7 +33,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -41,24 +41,24 @@ void rt_hw_interrupt_handler(int vector) */ void rt_hw_interrupt_init() { - rt_base_t index; + rt_base_t index; - XIntc_Config *CfgPtr; + XIntc_Config *CfgPtr; CfgPtr = &XIntc_ConfigTable[0]; - for (index = 0; index < MAX_HANDLERS; index ++) - { - CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -67,8 +67,8 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - XIntc_Disable(&int_ctl,vector); + /* disable interrupt */ + XIntc_Disable(&int_ctl,vector); } /** @@ -77,7 +77,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - XIntc_Enable(&int_ctl,vector); + XIntc_Enable(&int_ctl,vector); } /** @@ -88,15 +88,15 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - XIntc_Config *CfgPtr; + XIntc_Config *CfgPtr; CfgPtr = &XIntc_ConfigTable[0]; - if(vector >= 0 && vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler; - if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler; - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler; + if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler; + } } /*****************************************************************************/ @@ -117,7 +117,7 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha * calling an interrupt handler. * * -* @return None. +* @return None. * * @note * @@ -131,81 +131,81 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha void rt_hw_trap_irq(void ) { - u32 intr_status; - u32 intr_mask = 1; - int intr_number; - volatile u32 reg; /* used as bit bucket */ - XIntc_Config *cfg_ptr; + u32 intr_status; + u32 intr_mask = 1; + int intr_number; + volatile u32 reg; /* used as bit bucket */ + XIntc_Config *cfg_ptr; - /* Get the configuration data using the device ID */ - cfg_ptr = &XIntc_ConfigTable[0]; + /* Get the configuration data using the device ID */ + cfg_ptr = &XIntc_ConfigTable[0]; - /* Get the interrupts that are waiting to be serviced */ - intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR); + /* Get the interrupts that are waiting to be serviced */ + intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR); - /* Service each interrupt that is active and enabled by checking each - * bit in the register from LSB to MSB which corresponds to an interrupt - * intput signal - */ - for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++) - { - if (intr_status & 1) - { - XIntc_VectorTableEntry *table_ptr; + /* Service each interrupt that is active and enabled by checking each + * bit in the register from LSB to MSB which corresponds to an interrupt + * intput signal + */ + for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++) + { + if (intr_status & 1) + { + XIntc_VectorTableEntry *table_ptr; - /* If the interrupt has been setup to acknowledge it - * before servicing the interrupt, then ack it - */ - if (cfg_ptr->AckBeforeService & intr_mask) - { - XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); - } + /* If the interrupt has been setup to acknowledge it + * before servicing the interrupt, then ack it + */ + if (cfg_ptr->AckBeforeService & intr_mask) + { + XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); + } - /* The interrupt is active and enabled, call the - * interrupt handler that was setup with the specified - * parameter - */ - table_ptr = &(cfg_ptr->HandlerTable[intr_number]); - table_ptr->Handler(table_ptr->CallBackRef); + /* The interrupt is active and enabled, call the + * interrupt handler that was setup with the specified + * parameter + */ + table_ptr = &(cfg_ptr->HandlerTable[intr_number]); + table_ptr->Handler(table_ptr->CallBackRef); - /* If the interrupt has been setup to acknowledge it - * after it has been serviced then ack it - */ - if ((cfg_ptr->AckBeforeService & intr_mask) == 0) - { - XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); - } + /* If the interrupt has been setup to acknowledge it + * after it has been serviced then ack it + */ + if ((cfg_ptr->AckBeforeService & intr_mask) == 0) + { + XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); + } - /* - * Read the ISR again to handle architectures with posted write - * bus access issues. - */ - reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress); + /* + * Read the ISR again to handle architectures with posted write + * bus access issues. + */ + reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress); - /* - * If only the highest priority interrupt is to be - * serviced, exit loop and return after servicing - * the interrupt - */ - if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION) - { - return; - } - } + /* + * If only the highest priority interrupt is to be + * serviced, exit loop and return after servicing + * the interrupt + */ + if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION) + { + return; + } + } - /* Move to the next interrupt to check */ - intr_mask <<= 1; - intr_status >>= 1; + /* Move to the next interrupt to check */ + intr_mask <<= 1; + intr_status >>= 1; - /* If there are no other bits set indicating that all interrupts - * have been serviced, then exit the loop - */ - if (intr_status == 0) - { - break; - } - } + /* If there are no other bits set indicating that all interrupts + * have been serviced, then exit the loop + */ + if (intr_status == 0) + { + break; + } + } } |