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-rw-r--r--libcpu/arm/cortex-r4/cpu.c2
-rw-r--r--libcpu/arm/cortex-r4/start_gcc.S17
2 files changed, 19 insertions, 0 deletions
diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c
index dd82ef1cf4..b63a07732d 100644
--- a/libcpu/arm/cortex-r4/cpu.c
+++ b/libcpu/arm/cortex-r4/cpu.c
@@ -87,9 +87,11 @@ void rt_hw_cpu_dcache_disable()
}
#elif __GNUC__
+#ifdef RT_USING_CPU_FFS
int __rt_ffs(int value)
{
return __builtin_ffs(value);
}
#endif
+#endif
/*@}*/
diff --git a/libcpu/arm/cortex-r4/start_gcc.S b/libcpu/arm/cortex-r4/start_gcc.S
index de3059e821..10a74b251a 100644
--- a/libcpu/arm/cortex-r4/start_gcc.S
+++ b/libcpu/arm/cortex-r4/start_gcc.S
@@ -54,6 +54,23 @@ _reset:
@-------------------------------------------------------------------------------
@ Initialize CPU Registers
@ After reset, the CPU is in the Supervisor mode (M = 10011)
+ mov r0, #0x0000
+ mov r1, #0x0000
+ mov r2, #0x0000
+ mov r3, #0x0000
+ mov r4, #0x0000
+ mov r5, #0x0000
+ mov r6, #0x0000
+ mov r7, #0x0000
+ mov r8, #0x0000
+ mov r9, #0x0000
+ mov r10, #0x0000
+ mov r11, #0x0000
+ mov r12, #0x0000
+ mov r13, #0x0000
+ mrs r1, cpsr
+ msr spsr_cxsf, r1
+
cpsid if, #19
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)