diff options
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/SConscript | 21 | ||||
| -rw-r--r-- | libcpu/risc-v/common/context_gcc.S | 180 | ||||
| -rw-r--r-- | libcpu/risc-v/common/cpuport.c (renamed from libcpu/risc-v/e310/stack.c) | 73 | ||||
| -rw-r--r-- | libcpu/risc-v/common/cpuport.h | 27 | ||||
| -rw-r--r-- | libcpu/risc-v/common/riscv-ops.h | 41 | ||||
| -rw-r--r-- | libcpu/risc-v/common/riscv-plic.h | 113 | ||||
| -rw-r--r-- | libcpu/risc-v/e310/context_gcc.S | 227 | ||||
| -rw-r--r-- | libcpu/risc-v/e310/entry_gcc.S | 145 | ||||
| -rw-r--r-- | libcpu/risc-v/e310/interrupt_gcc.S | 129 | ||||
| -rw-r--r-- | libcpu/risc-v/rv32m1/interrupt.c | 33 | ||||
| -rw-r--r-- | libcpu/risc-v/rv32m1/interrupt_gcc.S | 130 |
11 files changed, 704 insertions, 415 deletions
diff --git a/libcpu/SConscript b/libcpu/SConscript index a42909e64c..568da67cc9 100644 --- a/libcpu/SConscript +++ b/libcpu/SConscript @@ -2,30 +2,37 @@ Import('RTT_ROOT') Import('rtconfig') from building import * +arch = rtconfig.ARCH comm = rtconfig.ARCH + '/common' path = rtconfig.ARCH + '/' + rtconfig.CPU +src = [] ASFLAGS = '' # The set of source files associated with this SConscript file. if rtconfig.PLATFORM == 'armcc': - src = Glob(path + '/*.c') + Glob(path + '/*_rvds.S') + Glob(comm + '/*.c') + src += Glob(path + '/*.c') + Glob(path + '/*_rvds.S') + src += Glob(comm + '/*.c') + Glob(comm + '/*_rvds.S') if rtconfig.PLATFORM == 'gcc': - src = Glob(path + '/*.c') + Glob(path + '/*_gcc.S') + Glob(comm + '/*.c') + Glob(path + '/*_init.S') + src += Glob(path + '/*_init.S') + src += Glob(path + '/*.c') + Glob(path + '/*_gcc.S') + src += Glob(comm + '/*.c') + Glob(comm + '/*_gcc.S') if rtconfig.PLATFORM == 'iar': - src = Glob(path + '/*.c') + Glob(path + '/*_iar.S') + Glob(comm + '/*.c') + src += Glob(path + '/*.c') + Glob(path + '/*_iar.S') + src += Glob(comm + '/*.c') + Glob(comm + '/*_iar.S') if rtconfig.PLATFORM == 'cl': - src = Glob(path + '/*.c') + src = Glob(path + '/*.c') if rtconfig.PLATFORM == 'mingw': - src = Glob(path + '/*.c') + src = Glob(path + '/*.c') if rtconfig.PLATFORM == 'armcc' and rtconfig.ARCH == 'arm' and rtconfig.CPU == 'arm926': ASFLAGS = ' --cpreproc' - -CPPPATH = [RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/common'] + +CPPPATH = [RTT_ROOT + '/libcpu/' + arch + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + arch + '/common'] + group = DefineGroup(rtconfig.CPU.upper(), src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S new file mode 100644 index 0000000000..94ae5d9df4 --- /dev/null +++ b/libcpu/risc-v/common/context_gcc.S @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting implementation + */ + +#include "cpuport.h" + +/* + * rt_base_t rt_hw_interrupt_disable(void); + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + csrrci a0, mstatus, 8 + ret + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + csrw mstatus, a0 + ret + +/* + * void rt_hw_context_switch_to(rt_ubase_t to) + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LOAD sp, (a0) + + /* load epc from stack */ + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + LOAD x1, 1 * REGBYTES(sp) + /* load mstatus from stack */ + LOAD a0, 2 * REGBYTES(sp) + csrw mstatus, a0 + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + mret + +/* + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + + /* saved from thread context + * x1/ra -> sp(0) + * x1/ra -> sp(1) + * mstatus.mie -> sp(2) + * x(i) -> sp(i-4) + */ + addi sp, sp, -32 * REGBYTES + STORE sp, (a0) + + STORE x1, 0 * REGBYTES(sp) + STORE x1, 1 * REGBYTES(sp) + + csrr a0, mstatus + andi a0, a0, 8 + beqz a0, save_mpie + li a0, 0x80 +save_mpie: + STORE a0, 2 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + /* restore to thread context + * sp(0) -> epc; + * sp(1) -> ra; + * sp(i) -> x(i+2) + */ + LOAD sp, (a1) + + /* resw ra to mepc */ + LOAD a1, 0 * REGBYTES(sp) + csrw mepc, a1 + LOAD x1, 1 * REGBYTES(sp) + + /* force to machin mode(MPP=11) */ + li a1, 0x00001800; + csrs mstatus, a1 + LOAD a1, 2 * REGBYTES(sp) + csrs mstatus, a1 + + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + mret diff --git a/libcpu/risc-v/e310/stack.c b/libcpu/risc-v/common/cpuport.c index a68c646e39..2ad77b99c5 100644 --- a/libcpu/risc-v/e310/stack.c +++ b/libcpu/risc-v/common/cpuport.c @@ -1,35 +1,23 @@ /* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2017-07-31 tanek first implementation + * 2018/10/28 Bernard The unify RISC-V porting code. */ +#include <rthw.h> #include <rtthread.h> -/* flag in interrupt handling */ -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; +#include "cpuport.h" -struct stack_frame +volatile rt_ubase_t rt_interrupt_from_thread = 0; +volatile rt_ubase_t rt_interrupt_to_thread = 0; +volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; + +struct rt_hw_stack_frame { rt_ubase_t epc; /* epc - epc - program counter */ rt_ubase_t ra; /* x1 - ra - return address for jumps */ @@ -75,30 +63,43 @@ struct stack_frame * * @return stack address */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) { - struct stack_frame *stack_frame; + struct rt_hw_stack_frame *frame; rt_uint8_t *stk; int i; - stk = stack_addr + sizeof(rt_uint32_t); - stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); - stk -= sizeof(struct stack_frame); + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); - stack_frame = (struct stack_frame *)stk; + frame = (struct rt_hw_stack_frame *)stk; - for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_ubase_t); i++) + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) { - ((rt_ubase_t *)stack_frame)[i] = 0xdeadbeef; + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; } - stack_frame->ra = (rt_ubase_t)texit; - stack_frame->a0 = (rt_ubase_t)parameter; - stack_frame->epc = (rt_ubase_t)tentry; + frame->ra = (rt_ubase_t)texit; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; - // force to machine mode(MPP=11) and set MPIE to 1 - stack_frame->mstatus = 0x00001880; + /* force to machine mode(MPP=11) and set MPIE to 1 */ + frame->mstatus = 0x00007880; return stk; } + +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + + return ; +} diff --git a/libcpu/risc-v/common/cpuport.h b/libcpu/risc-v/common/cpuport.h new file mode 100644 index 0000000000..95268732cb --- /dev/null +++ b/libcpu/risc-v/common/cpuport.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#include <rtconfig.h> + +/* bytes of register width */ +#ifdef ARCH_CPU_64BIT +#define STORE sd +#define LOAD ld +#define REGBYTES 8 +#else +#define STORE sw +#define LOAD lw +#define REGBYTES 4 +#endif + +#endif diff --git a/libcpu/risc-v/common/riscv-ops.h b/libcpu/risc-v/common/riscv-ops.h new file mode 100644 index 0000000000..0b321c6de4 --- /dev/null +++ b/libcpu/risc-v/common/riscv-ops.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ + +#ifndef RISCV_OPS_H__ +#define RISCV_OPS_H__ + +#if defined(__GNUC__) && !defined(__ASSEMBLER__) + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) +#endif /* end of __GNUC__ */ + +#endif diff --git a/libcpu/risc-v/common/riscv-plic.h b/libcpu/risc-v/common/riscv-plic.h new file mode 100644 index 0000000000..1da14b2e45 --- /dev/null +++ b/libcpu/risc-v/common/riscv-plic.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ + +#ifndef RISCV_PLIC_H__ +#define RISCV_PLIC_H__ + +#ifndef PLIC_BASE_ADDR +#define PLIC_BASE_ADDR 0x0 +#endif + +/* Priority Register - 32 bits per source */ +#define PLIC_PRIORITY_OFFSET (0x00000000UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per soirce */ +#define PLIC_PENDING_OFFSET (0x00001000UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +/* Enable Register - 0x80 per target */ +#define PLIC_ENABLE_OFFSET (0x00002000UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + +/* Claim Register - 0x1000 per target */ +#define PLIC_CLAIM_OFFSET (0x00200004UL) +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if defined(__GNUC__) && !defined(__ASSEMBLER__) +__attribute__((always_inline)) static inline void __plic_set_feature(unsigned int feature) +{ + volatile unsigned int *feature_ptr = (volatile unsigned int *)PLIC_BASE_ADDR; + *feature_ptr = feature; +} + +__attribute__((always_inline)) static inline void __plic_set_threshold(unsigned int threshold) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *threshold_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +__attribute__((always_inline)) static inline void __plic_set_priority(unsigned int source, unsigned int priority) +{ + volatile unsigned int *priority_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_PRIORITY_OFFSET + + (source << PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +__attribute__((always_inline)) static inline void __plic_set_pending(unsigned int source) +{ + volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_PENDING_OFFSET + + ((source >> 5) << 2)); + *current_ptr = (1 << (source & 0x1F)); +} + +__attribute__((always_inline)) static inline void __plic_irq_enable(unsigned int source) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + ((source >> 5) << 2)); + unsigned int current = *current_ptr; + current = current | (1 << (source & 0x1F)); + *current_ptr = current; +} + +__attribute__((always_inline)) static inline void __plic_irq_disable(unsigned int source) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + ((source >> 5) << 2)); + unsigned int current = *current_ptr; + current = current & ~((1 << (source & 0x1F))); + *current_ptr = current; +} + +__attribute__((always_inline)) static inline unsigned int __plic_irq_claim(void) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *claim_addr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +__attribute__((always_inline)) static inline void __plic_irq_complete(unsigned int source) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *claim_addr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = source; +} +#endif /* end of __GNUC__ */ + +#endif diff --git a/libcpu/risc-v/e310/context_gcc.S b/libcpu/risc-v/e310/context_gcc.S deleted file mode 100644 index 7aaa8db432..0000000000 --- a/libcpu/risc-v/e310/context_gcc.S +++ /dev/null @@ -1,227 +0,0 @@ -;/* -; * File : context_gcc.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2018, RT-Thread Development Team -; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -; * -; * Change Logs: -; * Date Author Notes -; * 2017-07-16 zhangjun for hifive1 -; * 2018-05-29 tanek optimize rt_hw_interrupt_* -; * 2018-05-29 tanek add mie register to context -; */ - -/* - * rt_base_t rt_hw_interrupt_disable(void); - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - csrrci a0, mstatus, 8 - ret - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - csrw mstatus, a0 - ret - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - - /* saved from thread context - * x1/ra -> sp(0) - * x1/ra -> sp(1) - * mstatus.mie -> sp(2) - * x(i) -> sp(i-4) - */ - addi sp, sp, -32 * 4 - sw sp, (a0) - - sw x1, 0 * 4(sp) - sw x1, 1 * 4(sp) - - csrr a0, mstatus - andi a0, a0, 8 - beqz a0, save_mpie - li a0, 0x80 -save_mpie: - sw a0, 2 * 4(sp) - - sw x4, 4 * 4(sp) - sw x5, 5 * 4(sp) - sw x6, 6 * 4(sp) - sw x7, 7 * 4(sp) - sw x8, 8 * 4(sp) - sw x9, 9 * 4(sp) - sw x10, 10 * 4(sp) - sw x11, 11 * 4(sp) - sw x12, 12 * 4(sp) - sw x13, 13 * 4(sp) - sw x14, 14 * 4(sp) - sw x15, 15 * 4(sp) - sw x16, 16 * 4(sp) - sw x17, 17 * 4(sp) - sw x18, 18 * 4(sp) - sw x19, 19 * 4(sp) - sw x20, 20 * 4(sp) - sw x21, 21 * 4(sp) - sw x22, 22 * 4(sp) - sw x23, 23 * 4(sp) - sw x24, 24 * 4(sp) - sw x25, 25 * 4(sp) - sw x26, 26 * 4(sp) - sw x27, 27 * 4(sp) - sw x28, 28 * 4(sp) - sw x29, 29 * 4(sp) - sw x30, 30 * 4(sp) - sw x31, 31 * 4(sp) - - /* restore to thread context - * sp(0) -> epc; - * sp(1) -> ra; - * sp(i) -> x(i+2) - */ - lw sp, (a1) - - /* resw ra to mepc */ - lw a1, 0 * 4(sp) - csrw mepc, a1 - lw x1, 1 * 4(sp) - - /* force to machin mode(MPP=11) */ - li a1, 0x00001800; - csrs mstatus, a1 - lw a1, 2 * 4(sp) - csrs mstatus, a1 - - lw x4, 4 * 4(sp) - lw x5, 5 * 4(sp) - lw x6, 6 * 4(sp) - lw x7, 7 * 4(sp) - lw x8, 8 * 4(sp) - lw x9, 9 * 4(sp) - lw x10, 10 * 4(sp) - lw x11, 11 * 4(sp) - lw x12, 12 * 4(sp) - lw x13, 13 * 4(sp) - lw x14, 14 * 4(sp) - lw x15, 15 * 4(sp) - lw x16, 16 * 4(sp) - lw x17, 17 * 4(sp) - lw x18, 18 * 4(sp) - lw x19, 19 * 4(sp) - lw x20, 20 * 4(sp) - lw x21, 21 * 4(sp) - lw x22, 22 * 4(sp) - lw x23, 23 * 4(sp) - lw x24, 24 * 4(sp) - lw x25, 25 * 4(sp) - lw x26, 26 * 4(sp) - lw x27, 27 * 4(sp) - lw x28, 28 * 4(sp) - lw x29, 29 * 4(sp) - lw x30, 30 * 4(sp) - lw x31, 31 * 4(sp) - - addi sp, sp, 32 * 4 - mret - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, (a0) - - /* load epc from stack */ - lw a0, 0 * 4(sp) - csrw mepc, a0 - lw x1, 1 * 4(sp) - /* load mstatus from stack */ - lw a0, 2 * 4(sp) - csrw mstatus, a0 - lw x4, 4 * 4(sp) - lw x5, 5 * 4(sp) - lw x6, 6 * 4(sp) - lw x7, 7 * 4(sp) - lw x8, 8 * 4(sp) - lw x9, 9 * 4(sp) - lw x10, 10 * 4(sp) - lw x11, 11 * 4(sp) - lw x12, 12 * 4(sp) - lw x13, 13 * 4(sp) - lw x14, 14 * 4(sp) - lw x15, 15 * 4(sp) - lw x16, 16 * 4(sp) - lw x17, 17 * 4(sp) - lw x18, 18 * 4(sp) - lw x19, 19 * 4(sp) - lw x20, 20 * 4(sp) - lw x21, 21 * 4(sp) - lw x22, 22 * 4(sp) - lw x23, 23 * 4(sp) - lw x24, 24 * 4(sp) - lw x25, 25 * 4(sp) - lw x26, 26 * 4(sp) - lw x27, 27 * 4(sp) - lw x28, 28 * 4(sp) - lw x29, 29 * 4(sp) - lw x30, 30 * 4(sp) - lw x31, 31 * 4(sp) - - addi sp, sp, 32 * 4 - mret - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - addi sp, sp, -16 - sw s0, 12(sp) - sw a0, 8(sp) - sw a5, 4(sp) - - la a0, rt_thread_switch_interrupt_flag - lw a5, (a0) - bnez a5, _reswitch - li a5, 1 - sw a5, (a0) - - la a5, rt_interrupt_from_thread - lw a0, 8(sp) - sw a0, (a5) - -_reswitch: - la a5, rt_interrupt_to_thread - sw a1, (a5) - - lw a5, 4(sp) - lw a0, 8(sp) - lw s0, 12(sp) - addi sp, sp, 16 - ret diff --git a/libcpu/risc-v/e310/entry_gcc.S b/libcpu/risc-v/e310/entry_gcc.S deleted file mode 100644 index 83631e67ee..0000000000 --- a/libcpu/risc-v/e310/entry_gcc.S +++ /dev/null @@ -1,145 +0,0 @@ -/* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2018-05-29 tanek first implementation - */ - - .section .text.entry - .align 2 - .global trap_entry -trap_entry: - - // save all from thread context - addi sp, sp, -32 * 4 - - sw x1, 1 * 4(sp) - li t0, 0x80 - sw t0, 2 * 4(sp) - - sw x4, 4 * 4(sp) - sw x5, 5 * 4(sp) - sw x6, 6 * 4(sp) - sw x7, 7 * 4(sp) - sw x8, 8 * 4(sp) - sw x9, 9 * 4(sp) - sw x10, 10 * 4(sp) - sw x11, 11 * 4(sp) - sw x12, 12 * 4(sp) - sw x13, 13 * 4(sp) - sw x14, 14 * 4(sp) - sw x15, 15 * 4(sp) - sw x16, 16 * 4(sp) - sw x17, 17 * 4(sp) - sw x18, 18 * 4(sp) - sw x19, 19 * 4(sp) - sw x20, 20 * 4(sp) - sw x21, 21 * 4(sp) - sw x22, 22 * 4(sp) - sw x23, 23 * 4(sp) - sw x24, 24 * 4(sp) - sw x25, 25 * 4(sp) - sw x26, 26 * 4(sp) - sw x27, 27 * 4(sp) - sw x28, 28 * 4(sp) - sw x29, 29 * 4(sp) - sw x30, 30 * 4(sp) - sw x31, 31 * 4(sp) - - // switch to interrupt stack - move s0, sp - la sp, _sp - - // interrupt handle - call rt_interrupt_enter - csrr a0, mcause - csrr a1, mepc - mv a2, sp - call handle_trap - call rt_interrupt_leave - - // switch to from thread stack - move sp, s0 - - // need to switch new thread - la s0, rt_thread_switch_interrupt_flag - lw s2, 0(s0) - beqz s2, spurious_interrupt - sw zero, 0(s0) - - csrr a0, mepc - sw a0, 0 * 4(sp) - - la s0, rt_interrupt_from_thread - lw s1, 0(s0) - sw sp, 0(s1) - - la s0, rt_interrupt_to_thread - lw s1, 0(s0) - lw sp, 0(s1) - - lw a0, 0 * 4(sp) - csrw mepc, a0 - -spurious_interrupt: - lw x1, 1 * 4(sp) - - // Remain in M-mode after mret - li t0, 0x00001800 - csrs mstatus, t0 - lw t0, 2 * 4(sp) - csrs mstatus, t0 - - lw x4, 4 * 4(sp) - lw x5, 5 * 4(sp) - lw x6, 6 * 4(sp) - lw x7, 7 * 4(sp) - lw x8, 8 * 4(sp) - lw x9, 9 * 4(sp) - lw x10, 10 * 4(sp) - lw x11, 11 * 4(sp) - lw x12, 12 * 4(sp) - lw x13, 13 * 4(sp) - lw x14, 14 * 4(sp) - lw x15, 15 * 4(sp) - lw x16, 16 * 4(sp) - lw x17, 17 * 4(sp) - lw x18, 18 * 4(sp) - lw x19, 19 * 4(sp) - lw x20, 20 * 4(sp) - lw x21, 21 * 4(sp) - lw x22, 22 * 4(sp) - lw x23, 23 * 4(sp) - lw x24, 24 * 4(sp) - lw x25, 25 * 4(sp) - lw x26, 26 * 4(sp) - lw x27, 27 * 4(sp) - lw x28, 28 * 4(sp) - lw x29, 29 * 4(sp) - lw x30, 30 * 4(sp) - lw x31, 31 * 4(sp) - - addi sp, sp, 32 * 4 - mret - -.weak handle_trap -handle_trap: -1: - j 1b diff --git a/libcpu/risc-v/e310/interrupt_gcc.S b/libcpu/risc-v/e310/interrupt_gcc.S new file mode 100644 index 0000000000..a71987b05d --- /dev/null +++ b/libcpu/risc-v/e310/interrupt_gcc.S @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/02 Bernard The first version + */ + +#include "port.h" + + .section .text.entry + .align 2 + .global trap_entry +trap_entry: + + /* save all from thread context */ + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) + li t0, 0x80 + STORE t0, 2 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + /* save break thread stack to s0 */ + move s0, sp + /* switch to interrupt stack */ + la sp, _sp + + /* interrupt handle */ + call rt_interrupt_enter + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call handle_trap + call rt_interrupt_leave + + /* switch to from_thread stack */ + move sp, s0 + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + LOAD s2, 0(s0) + beqz s2, spurious_interrupt + STORE zero, 0(s0) + + csrr a0, mepc + STORE a0, 0 * REGBYTES(sp) + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + +spurious_interrupt: + LOAD x1, 1 * REGBYTES(sp) + + /* Remain in M-mode after mret */ + li t0, 0x00001800 + csrs mstatus, t0 + LOAD t0, 2 * REGBYTES(sp) + csrs mstatus, t0 + + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + mret diff --git a/libcpu/risc-v/rv32m1/interrupt.c b/libcpu/risc-v/rv32m1/interrupt.c new file mode 100644 index 0000000000..72cb344ff7 --- /dev/null +++ b/libcpu/risc-v/rv32m1/interrupt.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/01 Bernard The first version + */ + +#include <rthw.h> + +#include <board.h> +#include <RV32M1_ri5cy.h> + +typedef void (*irq_handler_t)(void); +extern const irq_handler_t isrTable[]; + +void SystemIrqHandler(uint32_t mcause) +{ + uint32_t intNum; + + if (mcause & 0x80000000) /* For external interrupt. */ + { + intNum = mcause & 0x1FUL; + + /* Clear pending flag in EVENT unit .*/ + EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum); + + /* Now call the real irq handler for intNum */ + isrTable[intNum](); + } +} diff --git a/libcpu/risc-v/rv32m1/interrupt_gcc.S b/libcpu/risc-v/rv32m1/interrupt_gcc.S new file mode 100644 index 0000000000..d74cf441bc --- /dev/null +++ b/libcpu/risc-v/rv32m1/interrupt_gcc.S @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/02 Bernard The first version + */ + +#include "cpuport.h" + + .section .text.entry + .align 2 + .global IRQ_Handler +IRQ_Handler: + + /* save all from thread context */ + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) + li t0, 0x80 + STORE t0, 2 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + move s0, sp + + /* switch to interrupt stack */ + la sp, __stack + + /* interrupt handle */ + call rt_interrupt_enter + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call SystemIrqHandler + call rt_interrupt_leave + + /* switch to from thread stack */ + move sp, s0 + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + LOAD s2, 0(s0) + beqz s2, spurious_interrupt + /* clear switch interrupt flag */ + STORE zero, 0(s0) + + csrr a0, mepc + STORE a0, 0 * REGBYTES(sp) + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + +spurious_interrupt: + LOAD x1, 1 * REGBYTES(sp) + + /* Remain in M-mode after mret */ + li t0, 0x00001800 + csrs mstatus, t0 + LOAD t0, 2 * REGBYTES(sp) + csrs mstatus, t0 + + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + mret |