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-rw-r--r--libcpu/sparc-v8/bm3803/bm3803.h151
-rw-r--r--libcpu/sparc-v8/bm3803/context_gcc.S26
-rw-r--r--libcpu/sparc-v8/bm3803/interrupt.c44
-rw-r--r--libcpu/sparc-v8/bm3803/interrupt.h26
-rw-r--r--libcpu/sparc-v8/bm3803/stack.c83
-rw-r--r--libcpu/sparc-v8/bm3803/start_gcc.S26
-rw-r--r--libcpu/sparc-v8/bm3803/trap.c42
-rw-r--r--libcpu/sparc-v8/bm3803/vector_gcc.S26
8 files changed, 253 insertions, 171 deletions
diff --git a/libcpu/sparc-v8/bm3803/bm3803.h b/libcpu/sparc-v8/bm3803/bm3803.h
index a90663f199..4a4c750975 100644
--- a/libcpu/sparc-v8/bm3803/bm3803.h
+++ b/libcpu/sparc-v8/bm3803/bm3803.h
@@ -1,95 +1,106 @@
/*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-10-16 Dystopia the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date Author Notes
+2020-10-16 Dystopia the first version
+*/
+
#ifndef __BM3803_H__
#define __BM3803_H__
struct lregs
{
- /* address = 0x80000000 */
- unsigned int memcfg1; /* 0x00 */
- unsigned int memcfg2;
- unsigned int memcfg3;
- unsigned int failaddr;
+ /* address = 0x80000000 */
+ unsigned int memcfg1; /* 0x00 */
+ unsigned int memcfg2;
+ unsigned int memcfg3;
+ unsigned int failaddr;
- unsigned int memstatus; /* 0x10 */
- unsigned int cachectrl;
- unsigned int powerdown;
- unsigned int writeprot1;
+ unsigned int memstatus; /* 0x10 */
+ unsigned int cachectrl;
+ unsigned int powerdown;
+ unsigned int writeprot1;
- unsigned int writeprot2; /* 0x20 */
- unsigned int pcr;
- unsigned int dummy2;
- unsigned int dummy3;
+ unsigned int writeprot2; /* 0x20 */
+ unsigned int pcr;
+ unsigned int dummy2;
+ unsigned int dummy3;
- unsigned int dummy4; /* 0x30 */
- unsigned int dummy5;
- unsigned int dummy6;
- unsigned int dummy7;
+ unsigned int dummy4; /* 0x30 */
+ unsigned int dummy5;
+ unsigned int dummy6;
+ unsigned int dummy7;
- unsigned int timercnt1; /* 0x40 */
- unsigned int timerload1;
- unsigned int timerctrl1;
- unsigned int wdog;
+ unsigned int timercnt1; /* 0x40 */
+ unsigned int timerload1;
+ unsigned int timerctrl1;
+ unsigned int wdog;
- unsigned int timercnt2; /* 0x50 */
- unsigned int timerload2;
- unsigned int timerctrl2;
- unsigned int dummy8;
+ unsigned int timercnt2; /* 0x50 */
+ unsigned int timerload2;
+ unsigned int timerctrl2;
+ unsigned int dummy8;
- unsigned int scalercnt; /* 0x60 */
- unsigned int scalerload;
- unsigned int dummy9;
- unsigned int dummy10;
+ unsigned int scalercnt; /* 0x60 */
+ unsigned int scalerload;
+ unsigned int dummy9;
+ unsigned int dummy10;
- unsigned int uartdata1; /* 0x70 */
- unsigned int uartstatus1;
- unsigned int uartctrl1;
- unsigned int uartscaler1;
+ unsigned int uartdata1; /* 0x70 */
+ unsigned int uartstatus1;
+ unsigned int uartctrl1;
+ unsigned int uartscaler1;
- unsigned int uartdata2; /* 0x80 */
- unsigned int uartstatus2;
- unsigned int uartctrl2;
- unsigned int uartscaler2;
+ unsigned int uartdata2; /* 0x80 */
+ unsigned int uartstatus2;
+ unsigned int uartctrl2;
+ unsigned int uartscaler2;
- unsigned int irqmask; /* 0x90 */
- unsigned int irqpend;
- unsigned int irqforce;
- unsigned int irqclear;
+ unsigned int irqmask; /* 0x90 */
+ unsigned int irqpend;
+ unsigned int irqforce;
+ unsigned int irqclear;
- unsigned int piodata; /* 0xA0 */
- unsigned int piodir;
- unsigned int pioirq;
- unsigned int dummy11;
+ unsigned int piodata; /* 0xA0 */
+ unsigned int piodir;
+ unsigned int pioirq;
+ unsigned int dummy11;
- unsigned int imask2; /* 0xB0 */
- unsigned int ipend2;
- unsigned int istat2;
- unsigned int dummy12;
+ unsigned int imask2; /* 0xB0 */
+ unsigned int ipend2;
+ unsigned int istat2;
+ unsigned int dummy12;
- unsigned int dummy13; /* 0xC0 */
- unsigned int dcomstatus;
- unsigned int dcomctrl;
- unsigned int dcomscaler;
+ unsigned int dummy13; /* 0xC0 */
+ unsigned int dcomstatus;
+ unsigned int dcomctrl;
+ unsigned int dcomscaler;
- unsigned int dummy14; /* 0xD0 */
- unsigned int dummy15;
- unsigned int dummy16;
- unsigned int dummy17;
+ unsigned int dummy14; /* 0xD0 */
+ unsigned int dummy15;
+ unsigned int dummy16;
+ unsigned int dummy17;
- unsigned int uartdata3; /* 0xE0 */
- unsigned int uartstatus3;
- unsigned int uartctrl3;
- unsigned int uartscaler3;
+ unsigned int uartdata3; /* 0xE0 */
+ unsigned int uartstatus3;
+ unsigned int uartctrl3;
+ unsigned int uartscaler3;
};
-#define PREGS 0x80000000
+#define PREGS 0x80000000
#define UART1_BASE (PREGS + 0x70)
diff --git a/libcpu/sparc-v8/bm3803/context_gcc.S b/libcpu/sparc-v8/bm3803/context_gcc.S
index c0344a81d5..478793588e 100644
--- a/libcpu/sparc-v8/bm3803/context_gcc.S
+++ b/libcpu/sparc-v8/bm3803/context_gcc.S
@@ -1,12 +1,22 @@
/*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-10-16 Dystopia the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date Author Notes
+2020-10-16 Dystopia the first version
+*/
#define SPARC_PSR_PIL_MASK 0x00000F00
#define SPARC_PSR_ET_MASK 0x00000020
diff --git a/libcpu/sparc-v8/bm3803/interrupt.c b/libcpu/sparc-v8/bm3803/interrupt.c
index e3f9b5b3de..8ce03dd4c0 100644
--- a/libcpu/sparc-v8/bm3803/interrupt.c
+++ b/libcpu/sparc-v8/bm3803/interrupt.c
@@ -1,12 +1,22 @@
/*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-10-16 Dystopia the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date Author Notes
+2020-10-16 Dystopia the first version
+*/
#include <rthw.h>
#include <rtthread.h>
@@ -43,10 +53,10 @@ void rt_hw_interrupt_init(void)
*/
void rt_hw_interrupt_mask(int vector)
{
- if (vector > 0x1F || vector < 0x11)
- return;
- volatile struct lregs *regs = (struct lregs*)PREGS;
- regs->irqmask &= ~(1 << (vector - 0x10));
+ if (vector > 0x1F || vector < 0x11)
+ return;
+ volatile struct lregs *regs = (struct lregs *)PREGS;
+ regs->irqmask &= ~(1 << (vector - 0x10));
}
/**
@@ -55,10 +65,10 @@ void rt_hw_interrupt_mask(int vector)
*/
void rt_hw_interrupt_umask(int vector)
{
- if (vector > 0x1F || vector < 0x11)
- return;
- volatile struct lregs *regs = (struct lregs*)PREGS;
- regs->irqmask |= 1 << (vector - 0x10);
+ if (vector > 0x1F || vector < 0x11)
+ return;
+ volatile struct lregs *regs = (struct lregs *)PREGS;
+ regs->irqmask |= 1 << (vector - 0x10);
}
/**
@@ -72,7 +82,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
{
rt_isr_handler_t old_handler = RT_NULL;
- if(vector < MAX_HANDLERS || vector >= 0)
+ if (vector < MAX_HANDLERS || vector >= 0)
{
old_handler = isr_table[vector].handler;
diff --git a/libcpu/sparc-v8/bm3803/interrupt.h b/libcpu/sparc-v8/bm3803/interrupt.h
index 7632195e70..5c97d5caa5 100644
--- a/libcpu/sparc-v8/bm3803/interrupt.h
+++ b/libcpu/sparc-v8/bm3803/interrupt.h
@@ -1,12 +1,22 @@
/*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-10-16 Dystopia the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date Author Notes
+2020-10-16 Dystopia the first version
+*/
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
diff --git a/libcpu/sparc-v8/bm3803/stack.c b/libcpu/sparc-v8/bm3803/stack.c
index 3563692cdd..70c1b60d8c 100644
--- a/libcpu/sparc-v8/bm3803/stack.c
+++ b/libcpu/sparc-v8/bm3803/stack.c
@@ -1,12 +1,23 @@
/*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-10-16 Dystopia the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date Author Notes
+2020-10-16 Dystopia the first version
+*/
+
#include <rtthread.h>
/**
@@ -29,34 +40,34 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
stack_addr += sizeof(rt_uint32_t);
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint32_t *)stack_addr;
-
- stk -= 24;
- stk -= 8;
-
- for (register_index = 0; register_index != 8; register_index++)
- stk[register_index] = 0xdeadbeef;
-
- for (window_index = 0; window_index != 8; window_index++)
- {
- stk -= 16;
- for (register_index = 0; register_index != 16; register_index++)
- stk[register_index] = 0xdeadbeef;
- if (window_index == 0)
- {
- stk[8] = (rt_uint32_t)parameter;
- stk[15] = (rt_uint32_t)texit - 8;
- }
- }
-
- stk -= 34;
- for (register_index = 0; register_index != 34; register_index++)
- stk[register_index] = 0;
-
- stk -= 4;
- stk[0] = (rt_uint32_t)tentry; //pc
- stk[1] = (rt_uint32_t)tentry + 4; //npc
- stk[2] = 0x10C7; //psr
- stk[3] = 0x2; //wim
+
+ stk -= 24;
+ stk -= 8;
+
+ for (register_index = 0; register_index != 8; register_index++)
+ stk[register_index] = 0xdeadbeef;
+
+ for (window_index = 0; window_index != 8; window_index++)
+ {
+ stk -= 16;
+ for (register_index = 0; register_index != 16; register_index++)
+ stk[register_index] = 0xdeadbeef;
+ if (window_index == 0)
+ {
+ stk[8] = (rt_uint32_t)parameter;
+ stk[15] = (rt_uint32_t)texit - 8;
+ }
+ }
+
+ stk -= 34;
+ for (register_index = 0; register_index != 34; register_index++)
+ stk[register_index] = 0;
+
+ stk -= 4;
+ stk[0] = (rt_uint32_t)tentry; //pc
+ stk[1] = (rt_uint32_t)tentry + 4; //npc
+ stk[2] = 0x10C7; //psr
+ stk[3] = 0x2; //wim
/* return task's current stack address */
return (rt_uint8_t *)stk;
diff --git a/libcpu/sparc-v8/bm3803/start_gcc.S b/libcpu/sparc-v8/bm3803/start_gcc.S
index 0f87aa17db..fd613375c9 100644
--- a/libcpu/sparc-v8/bm3803/start_gcc.S
+++ b/libcpu/sparc-v8/bm3803/start_gcc.S
@@ -1,12 +1,22 @@
/*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-10-16 Dystopia the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date Author Notes
+2020-10-16 Dystopia the first version
+*/
#define PSR_INIT 0x10C0
#define PREGS 0x80000000
diff --git a/libcpu/sparc-v8/bm3803/trap.c b/libcpu/sparc-v8/bm3803/trap.c
index 05a0416dfa..545073ed18 100644
--- a/libcpu/sparc-v8/bm3803/trap.c
+++ b/libcpu/sparc-v8/bm3803/trap.c
@@ -1,12 +1,22 @@
/*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-10-16 Dystopia the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date Author Notes
+2020-10-16 Dystopia the first version
+*/
#include <rtthread.h>
#include <rthw.h>
@@ -15,14 +25,14 @@ extern struct rt_irq_desc isr_table[];
void rt_hw_trap(int tt, unsigned int *sp)
{
- void *param;
- rt_isr_handler_t isr_func;
-
- /* get interrupt service routine */
- isr_func = isr_table[tt].handler;
- param = isr_table[tt].param;
-
- /* turn to interrupt service routine */
+ void *param;
+ rt_isr_handler_t isr_func;
+
+ /* get interrupt service routine */
+ isr_func = isr_table[tt].handler;
+ param = isr_table[tt].param;
+
+ /* turn to interrupt service routine */
if (isr_func != RT_NULL)
isr_func(tt, param);
}
diff --git a/libcpu/sparc-v8/bm3803/vector_gcc.S b/libcpu/sparc-v8/bm3803/vector_gcc.S
index 0d243bee33..114fe45536 100644
--- a/libcpu/sparc-v8/bm3803/vector_gcc.S
+++ b/libcpu/sparc-v8/bm3803/vector_gcc.S
@@ -1,12 +1,22 @@
/*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-10-16 Dystopia the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date Author Notes
+2020-10-16 Dystopia the first version
+*/
#define TRAPL(H) mov %g0, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop;
#define TRAP(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop;
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 13:25:41 +0000