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-rw-r--r--libcpu/ti-dsp/c6x/c66xx.h18
-rw-r--r--libcpu/ti-dsp/c6x/context.asm2
-rw-r--r--libcpu/ti-dsp/c6x/interrupt.c7
-rw-r--r--libcpu/ti-dsp/c6x/intexc.asm2
-rw-r--r--libcpu/ti-dsp/c6x/stack.asm122
-rw-r--r--libcpu/ti-dsp/c6x/trap.c1
-rw-r--r--libcpu/ti-dsp/c6x/trap.h2
-rw-r--r--libcpu/ti-dsp/c6x/vector.asm2
8 files changed, 72 insertions, 84 deletions
diff --git a/libcpu/ti-dsp/c6x/c66xx.h b/libcpu/ti-dsp/c6x/c66xx.h
index 97d817a6d2..4d00ece2bf 100644
--- a/libcpu/ti-dsp/c6x/c66xx.h
+++ b/libcpu/ti-dsp/c6x/c66xx.h
@@ -74,21 +74,6 @@ struct rt_hw_exp_stack_register
struct rt_hw_register hw_register;
};
-extern cregister volatile unsigned int IERR; /* Internal Exception Report Register */
-extern cregister volatile unsigned int ECR; /* Exception Clear Register */
-extern cregister volatile unsigned int EFR; /* Exception Flag Register */
-extern cregister volatile unsigned int TSR; /* Task State Register */
-extern cregister volatile unsigned int ITSR; /* Interrupt Task State Register */
-extern cregister volatile unsigned int NTSR; /* NMI/exception Task State Register */
-extern cregister volatile unsigned int TSCL; /* Time Stamp Counter Register - Low Half */
-extern cregister volatile unsigned int TSCH; /* Time Stamp Counter Register - High Half */
-extern cregister volatile unsigned int DNUM; /* Core number */
-
-#define get_creg(reg) reg
-#define set_creg(reg, v) reg = (v)
-#define or_creg(reg, n) reg |= (n)
-#define and_creg(reg, n) reg &= (n)
-
#define __dint() asm(" DINT")
#define __rint() asm(" RINT")
#define __system_call() asm(" SWE")
@@ -99,7 +84,4 @@ extern cregister volatile unsigned int DNUM; /* Core number */
#define __SYSREG(ADDR, TYPE) (*(volatile TYPE*)(ADDR))
#define __SYSREGA(ADDR, TYPE) ((volatile TYPE*)(ADDR))
-extern void rt_hw_enable_exception(void);
-
#endif /* __C66XX_H__ */
-
diff --git a/libcpu/ti-dsp/c6x/context.asm b/libcpu/ti-dsp/c6x/context.asm
index f6972013f5..3f317583a4 100644
--- a/libcpu/ti-dsp/c6x/context.asm
+++ b/libcpu/ti-dsp/c6x/context.asm
@@ -9,7 +9,7 @@
;
;-----------------------------------------------------------
-; context switch for C6678 DSP
+; context switch for C6000 DSP
;-----------------------------------------------------------
.include "contextinc.asm"
diff --git a/libcpu/ti-dsp/c6x/interrupt.c b/libcpu/ti-dsp/c6x/interrupt.c
index d78de95abb..0d99201880 100644
--- a/libcpu/ti-dsp/c6x/interrupt.c
+++ b/libcpu/ti-dsp/c6x/interrupt.c
@@ -8,8 +8,10 @@
* 2021-11-16 Dystopia the first version
*/
-#include "c66xx.h"
+
#include "interrupt.h"
+#include "c66xx.h"
+#include "trap.h"
#define MAX_HANDLERS 128
@@ -24,6 +26,9 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
*/
void rt_hw_interrupt_init(void)
{
+ // initial system trap
+ rt_trap_init();
+
/* init exceptions table */
rt_memset(isr_table, 0x00, sizeof(isr_table));
diff --git a/libcpu/ti-dsp/c6x/intexc.asm b/libcpu/ti-dsp/c6x/intexc.asm
index d3ed54dc3b..709a9c4232 100644
--- a/libcpu/ti-dsp/c6x/intexc.asm
+++ b/libcpu/ti-dsp/c6x/intexc.asm
@@ -9,7 +9,7 @@
;
;-----------------------------------------------------------
-; interrupt and execption handler for C6678 DSP
+; interrupt and execption handler for C000 DSP
;-----------------------------------------------------------
;-----------------------------------------------------------
diff --git a/libcpu/ti-dsp/c6x/stack.asm b/libcpu/ti-dsp/c6x/stack.asm
index 6a523a1c95..6823ef7a66 100644
--- a/libcpu/ti-dsp/c6x/stack.asm
+++ b/libcpu/ti-dsp/c6x/stack.asm
@@ -9,7 +9,7 @@
;
;-----------------------------------------------------------
-; build system stack for C6678 DSP
+; build thread stack for C6000 DSP
;-----------------------------------------------------------
;-----------------------------------------------------------
@@ -35,73 +35,73 @@ ADDRESS_MSK .set 0xFFFFFFF0
;{
.global rt_hw_stack_init
rt_hw_stack_init:
- SUB A6,1,B1 ;
- MVKL ADDRESS_MSK,A1 ;
- MVKH ADDRESS_MSK,A1 ; Build address mask
- MVC CSR,B0 ;
- AND -2,B0,B0 ; Clear GIE bit
- OR 2,B0,B0 ; Set PGIE bit for interrupt return
- AND A1,B1,B1 ; Ensure alignment
+ SUB A6,1,B1 ;
+ MVKL ADDRESS_MSK,A1 ;
+ MVKH ADDRESS_MSK,A1 ; Build address mask
+ MVC CSR,B0 ;
+ AND -2,B0,B0 ; Clear GIE bit
+ OR 2,B0,B0 ; Set PGIE bit for interrupt return
+ AND A1,B1,B1 ; Ensure alignment
;
; Actually build the stack frame.
;
- MV B1,A3
- MV B14,A2
- STDW A3:A2,*--B1[1] ; Initial B15:B14
- SUBAW .D2 B1,2,B1
- ZERO A2
- ZERO A3 ; Clear value
- STDW A3:A2,*B1--[1] ; Initial A15:A14
- STDW A3:A2,*B1--[1] ; Initial A13:A12
- STDW A3:A2,*B1--[1] ; Initial A11:A10
- STDW A3:A2,*B1--[1] ; Initial A9:A8
- STDW A3:A2,*B1--[1] ; Initial A7:A6
- MV B4,A2
- STDW A3:A2,*B1--[1] ; Initial A5:A4
- ZERO A2
- STDW A3:A2,*B1--[1] ; Initial A3:A2
- STDW A3:A2,*B1--[1] ; Initial A1:A0
+ MV B1,A3
+ MV B14,A2
+ STDW A3:A2,*--B1[1] ; Initial B15:B14
+ SUBAW .D2 B1,2,B1
+ ZERO A2
+ ZERO A3 ; Clear value
+ STDW A3:A2,*B1--[1] ; Initial A15:A14
+ STDW A3:A2,*B1--[1] ; Initial A13:A12
+ STDW A3:A2,*B1--[1] ; Initial A11:A10
+ STDW A3:A2,*B1--[1] ; Initial A9:A8
+ STDW A3:A2,*B1--[1] ; Initial A7:A6
+ MV B4,A2
+ STDW A3:A2,*B1--[1] ; Initial A5:A4
+ ZERO A2
+ STDW A3:A2,*B1--[1] ; Initial A3:A2
+ STDW A3:A2,*B1--[1] ; Initial A1:A0
- STDW A3:A2,*B1--[1] ; Initial A31:A30
- STDW A3:A2,*B1--[1] ; Initial A29:A28
- STDW A3:A2,*B1--[1] ; Initial A27:A26
- STDW A3:A2,*B1--[1] ; Initial A25:A24
- STDW A3:A2,*B1--[1] ; Initial A23:A22
- STDW A3:A2,*B1--[1] ; Initial A21:A20
- STDW A3:A2,*B1--[1] ; Initial A19:A18
- STDW A3:A2,*B1--[1] ; Initial A17:A16
+ STDW A3:A2,*B1--[1] ; Initial A31:A30
+ STDW A3:A2,*B1--[1] ; Initial A29:A28
+ STDW A3:A2,*B1--[1] ; Initial A27:A26
+ STDW A3:A2,*B1--[1] ; Initial A25:A24
+ STDW A3:A2,*B1--[1] ; Initial A23:A22
+ STDW A3:A2,*B1--[1] ; Initial A21:A20
+ STDW A3:A2,*B1--[1] ; Initial A19:A18
+ STDW A3:A2,*B1--[1] ; Initial A17:A16
- STDW A3:A2,*B1--[1] ; Initial B13:B12
- STDW A3:A2,*B1--[1] ; Initial B11:B10
- STDW A3:A2,*B1--[1] ; Initial B9:B8
- STDW A3:A2,*B1--[1] ; Initial B7:B6
- STDW A3:A2,*B1--[1] ; Initial B5:B4
- MV B6,A3
- STDW A3:A2,*B1--[1] ; Initial B3:B2
- ZERO A3
- STDW A3:A2,*B1--[1] ; Initial B1:B0
+ STDW A3:A2,*B1--[1] ; Initial B13:B12
+ STDW A3:A2,*B1--[1] ; Initial B11:B10
+ STDW A3:A2,*B1--[1] ; Initial B9:B8
+ STDW A3:A2,*B1--[1] ; Initial B7:B6
+ STDW A3:A2,*B1--[1] ; Initial B5:B4
+ MV B6,A3
+ STDW A3:A2,*B1--[1] ; Initial B3:B2
+ ZERO A3
+ STDW A3:A2,*B1--[1] ; Initial B1:B0
- STDW A3:A2,*B1--[1] ; Initial B31:B30
- STDW A3:A2,*B1--[1] ; Initial B29:B28
- STDW A3:A2,*B1--[1] ; Initial B27:B26
- STDW A3:A2,*B1--[1] ; Initial B25:B24
- STDW A3:A2,*B1--[1] ; Initial B23:B22
- STDW A3:A2,*B1--[1] ; Initial B21:B20
- STDW A3:A2,*B1--[1] ; Initial B19:B18
- STDW A3:A2,*B1--[1] ; Initial B17:B16
+ STDW A3:A2,*B1--[1] ; Initial B31:B30
+ STDW A3:A2,*B1--[1] ; Initial B29:B28
+ STDW A3:A2,*B1--[1] ; Initial B27:B26
+ STDW A3:A2,*B1--[1] ; Initial B25:B24
+ STDW A3:A2,*B1--[1] ; Initial B23:B22
+ STDW A3:A2,*B1--[1] ; Initial B21:B20
+ STDW A3:A2,*B1--[1] ; Initial B19:B18
+ STDW A3:A2,*B1--[1] ; Initial B17:B16
- MV A4,A3
- MV B0,A2
- STDW A3:A2,*B1--[1] ; Initial PC:CSR
+ MV A4,A3
+ MV B0,A2
+ STDW A3:A2,*B1--[1] ; Initial PC:CSR
- ZERO A2
- ZERO A3
- STDW A3:A2,*B1--[1] ; Initial ILC:RILC
- B B3
- MVKL 0x3,B0
- MV B0,A3
- MVKL 1,A2
- STDW A3:A2,*B1--[1] ; Initial TSR:stack type
- MV B1,A4 ; Save to TCB
+ ZERO A2
+ ZERO A3
+ STDW A3:A2,*B1--[1] ; Initial ILC:RILC
+ B B3
+ MVKL 0x3,B0
+ MV B0,A3
+ MVKL 1,A2
+ STDW A3:A2,*B1--[1] ; Initial TSR:stack type
+ MV B1,A4 ; Save to TCB
;}
.end
diff --git a/libcpu/ti-dsp/c6x/trap.c b/libcpu/ti-dsp/c6x/trap.c
index f919467f2b..c9a013ff03 100644
--- a/libcpu/ti-dsp/c6x/trap.c
+++ b/libcpu/ti-dsp/c6x/trap.c
@@ -18,6 +18,7 @@
#define RT_SYS_STACK_SIZE 4096
+extern void rt_hw_enable_exception(void);
rt_uint8_t rt_system_stack[RT_SYS_STACK_SIZE];
rt_uint8_t *rt_system_stack_top;
diff --git a/libcpu/ti-dsp/c6x/trap.h b/libcpu/ti-dsp/c6x/trap.h
index 6d4312e243..414e425845 100644
--- a/libcpu/ti-dsp/c6x/trap.h
+++ b/libcpu/ti-dsp/c6x/trap.h
@@ -70,7 +70,7 @@ struct rt_exception_info {
#define __ffs(a) (_lmbd(1, _bitr(a)))
#define __fls(a) (!(a) ? 0 : (32 - _lmbd(1, (a))))
-void rt_trap_init(void);
+extern void rt_trap_init(void);
#endif /* __TRAP_H__ */
diff --git a/libcpu/ti-dsp/c6x/vector.asm b/libcpu/ti-dsp/c6x/vector.asm
index c942029d86..3c8123abd7 100644
--- a/libcpu/ti-dsp/c6x/vector.asm
+++ b/libcpu/ti-dsp/c6x/vector.asm
@@ -9,7 +9,7 @@
;
;-----------------------------------------------------------
-; interrupt vector table for C6678 DSP
+; interrupt vector table for C6000 DSP
;-----------------------------------------------------------
;-----------------------------------------------------------
generated by cgit v1.3.1 (git 2.54.0) at 2026-11-03 21:36:27 +0000