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-rw-r--r--libcpu/arm/cortex-a/armv7.h6
-rw-r--r--libcpu/arm/cortex-a/gtimer.c2
2 files changed, 7 insertions, 1 deletions
diff --git a/libcpu/arm/cortex-a/armv7.h b/libcpu/arm/cortex-a/armv7.h
index f284bb5255..325d0ed0ae 100644
--- a/libcpu/arm/cortex-a/armv7.h
+++ b/libcpu/arm/cortex-a/armv7.h
@@ -69,4 +69,10 @@ struct rt_hw_stack
#define E_Bit (1<<9)
#define J_Bit (1<<24)
+#define PABT_EXCEPTION 0x1
+#define DABT_EXCEPTION 0x2
+#define UND_EXCEPTION 0x3
+#define SWI_EXCEPTION 0x4
+#define RESV_EXCEPTION 0xF
+
#endif
diff --git a/libcpu/arm/cortex-a/gtimer.c b/libcpu/arm/cortex-a/gtimer.c
index b35acc6e6f..fd5f96950c 100644
--- a/libcpu/arm/cortex-a/gtimer.c
+++ b/libcpu/arm/cortex-a/gtimer.c
@@ -86,7 +86,7 @@ static inline rt_uint64_t __get_cntp_cval(void)
* This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
* param value: CNTP_CTL Register value to set
*/
-static inline void __set_cntp_ctl(uint32_t value)
+static inline void __set_cntp_ctl(rt_uint32_t value)
{
__set_cp(15, 0, value, 14, 2, 1);
}