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Increase RT_CPUS_NR from 4 to 8 in the K1 default configuration
and regenerate rtconfig.h.
Add the SpacemiT K1 entry and peripheral support matrix to the
BSP overview.
Verified eight-core boot and root filesystem mounting with the
RISC-V ticket spinlock fix.
Signed-off-by: GuEe-GUI <[email protected]>
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15.2 (#11870)
* [bsp][esp32] adapt C3/C6 to ESP-IDF v6.1 and bump RISC-V toolchain to gcc 15.2
- Adapt ESP32-C3/C6 BSP to ESP-IDF v6.1; bump RISC-V toolchain to gcc 15.2
- C6: re-enable SPI with board-local drv_spi.c; add devices.spi to CI
attachconfig; drop shared drv_spi.c spi_command_t hack
- C6: fix ADC oneshot multi-channel unit handle and mutex
- C3: fix portTRY_ENTER_CRITICAL_SAFE expansion in portmacro.h
- Compat with RT-Thread-packages/esp-idf rtt-dev used by CI: map
SYSTIMER_* to SYSTIMER_LL_* (C3 and C6 board.c), accept uart_periph.h
from hal/ or soc/
- Fix clang-format and cppcheck issues in the compat code
Signed-off-by: seteiro <[email protected]>
Co-Authored-By: Grok <[email protected]>
* ci: retrigger after esp-idf#18 merged
* bsp: ESP: fix C6 ADC for IDF 6.1 (adc_ll bus clock)
Replace removed PERIPH_SARADC_MODULE with adc_ll_enable_bus_clock /
adc_ll_reset_register when ESP_IDF_VERSION >= 6.0.0.
---------
Signed-off-by: seteiro <[email protected]>
Co-authored-by: Grok <[email protected]>
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Sync the HPMicro BSPs with hpm_sdk v1.13.0 and add the HPM5100EVK
(HPM5151) board.
- add the hpm5100evk BSP (board/startup/applications/Kconfig/docs) and
register it in .github/ALL_BSP_COMPILE.json, bsp/README.md and the
HPMicro READMEs
- re-sync the 11 existing boards (board/startup/debug scripts/linker
scripts/applications) with hpm_sdk v1.13.0, keeping the RT-Thread
specific parts: clock_time based drv_timer, CXX wired into the scons
environment, SConscript outputs under build/, named Kconfig choices,
rt_hw_us_delay in board_delay_*, board local codec files
- sync the shared driver layer with hpm_sdk v1.13.0 (GPTMRv2/PTMR,
PUART, soft I2C/SPI and the remaining peripheral driver updates)
- select the hpm_sdk v1.13.0 online package (PKG_USING_HPM_SDK_V113)
- use -Og instead of -O0 for the debug builds and print floats with the
RT-Thread klibc implementation instead of newlib nano
- initialize the RT-Thread heap before the SDK console init: the SDK
console_init() calls setvbuf(), which allocates through the C library
malloc() and tripped RT_ASSERT() in rt_smem_alloc() on the boards
built with RT_USING_DEBUG
- keep only ram_rtt.ld/flash_rtt.ld per board, align the DLM origin to
4KB on hpm5300evk/hpm5301evklite (the unaligned origin made the
linker emit a file backed PT_LOAD for the RAM area, which broke
"program rtthread.elf"), and anchor the generated .bin at the flash
base address 0x80000000
- sync the hpm6750evk openocd debug scripts with the new style used by
the other boards (hpm_common.cfg/hpm_reset.cfg with arp_halt)
- keep the upstream synced board/startup/libraries trees of bsp/hpmicro out of the
changed-file cppcheck run (same policy as bsp/hpmicro/.clang-format-ignore): the
check runs without the hpm_sdk include paths, so it reports ATTR_PLACE_AT and the
linker script symbol arithmetic in c_startup() as errors
- give the hpmicro boards in the changed-file scons trigger list the RV32 toolchain
they need (RISC-V-GCC-RV32) and add the matching installation step to that
workflow: the entries used sourcery-arm, which only provides the ARM toolchain,
so those legs could not find riscv32-unknown-elf-gcc
- keep hpm5100evk's ram_rtt.ld identical to the hpm_sdk v1.13.0
reference: the .fast_ram sections belong in DLM there (the DLM has
enough headroom), and that also makes its RAM and flash layouts agree
- skip the dependency pre-check when cleaning (scons -c): it runs from
DoBuilding() unconditionally, so a clean request with packages/ not
fetched yet was aborted with exit code 1 instead of cleaning
- make the manual scons trigger workflow runnable: it aborted while still
downloading actions because actions/upload-artifact@v3 is deprecated,
and scons was not on PATH because ~/.env/env.sh was never sourced.
Install tools/requirements.txt and source the Env PATH script in the
build step, and use @main action versions, as bsp_buildings.yml does
- start the LED demo thread only when rt_thread_create() succeeded
Tested:
- 12 boards x {ram_debug, ram_release, flash_debug, flash_release}:
48/48 clean builds
- flash boot + msh on hpm5100evk, hpm5300evk, hpm5e00evk, hpm6200evk,
hpm6300evk, hpm6750evk, hpm6750evk2, hpm6750evkmini, hpm6800evk,
hpm6e00evk, hpm6p00evk (list device/timer, ps, free, reset, rt_kprintf
float formatting)
- re-ran .github/workflows/manual_trigger_scons_except_STM32_all.yml with
the matrix reduced to the three hpmicro rows: all three legs build and
scons --dist succeeds with no local workarounds
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* [libcpu][risc-v] Refactor the RISC-V architecture port
Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.
- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration
Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.
Signed-off-by: GuEe-GUI <[email protected]>
* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk
Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.
Signed-off-by: seteiro <[email protected]>
* [libcpu][risc-v] Fix per-CPU page table mapping
- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings
Signed-off-by: GuEe-GUI <[email protected]>
---------
Signed-off-by: GuEe-GUI <[email protected]>
Signed-off-by: seteiro <[email protected]>
Co-authored-by: seteiro <[email protected]>
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gdma.c, early width check
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cppcheck follows spi_configure(NULL, NULL) into a dereference. clang-format also wants the macro backslashes left-aligned and a single space around the enum equals.
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Selecting BSP_USING_SPI on C6 links the IDF SPI master. The default image still leaves SPI off, and the peripheral table stays unsupported.
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with ci-attach
The N32H47x_48x and N32H49x series share drv_tim.c with N32H7xx, but only the
H7xx branch was ever implemented, so clock timer, LPTIM, PWM and pulse encoder
built to nothing on n32h487zgl7-evb and n32h497zgl7-evb. This adds those
branches and gives all three boards a ci-attach entry set that actually
compiles what the drivers claim to support.
Drivers
- drv_tim.c gains the H47x_48x/H49x clock-source and clock-enable branches,
the ATIM/GTIM/BTIM instance tables and n32_tim_clock_freq_get(), which
reads the real PCLK/HCLK/SYSCLK back from RCC rather than assuming one.
ATIMCLKSEL is inverted between the two families and is handled as such.
- drv_lptim.c derives its tick from the real LSI value instead of a
hard-coded one, unlocks the backup domain before touching RCC, latches
the prescaler, and returns -RT_EINVAL rather than clamping a bad rate.
- drv_pwm.c and drv_pulse_encoder.c are extended to the H47x_48x/H49x
instances; the H7xx encoder's update event is cleared through
TIM_EnableUpdateEvt() because that family has no TIM_ConfigUpdateEvt().
- config/{h47x_48x,h49x}/{tim,pwm,pulse_encoder,lptim}_config.h are new and
enumerate the instances each series has, for the existing drivers to read.
Kconfig
Each board defines the timer menus in its own board/Kconfig, so that a
board's peripheral options live with the board and the shared driver
Kconfig stays series-neutral; libraries/N32_Drivers/drivers/Kconfig is
byte-identical to upstream/master. All three copies enforce the mutual
exclusion drv_pulse_encoder.c documents (a timer instance enabled for both
clock timer and pulse encoder collides at link time on the shared ISR
symbol); N32H7xx's menus had none at all and are brought in line.
ci-attach
51 entries across the three boards (17/16/18). h487 carries three NAND
entries - peripheral.nand, peripheral.nand_16b and peripheral.nand_large -
and h497 and h760 carry one each. peripheral.nand_large exists because
drv_nand.c picks the row-address cycle count from pages_per_block *
block_count: 2 cycles up to 65536 pages, 3 up to 16777216, else 4. Every
other NAND entry takes the Kconfig default 64 * 1024 = 65536, which lands
exactly on the first boundary, so the >= 3 and >= 4 arms were compiled by
nothing at all - it takes a geometry past the 24-bit row width to reach the
top rung. The entry pins that geometry to arm them; it is not a claim about
the part on the board.
Fixes carried in the same series
- drv_nand.c emitted its third row-address byte under `== 3`, so a 4-cycle
part would set the count to 4 and then match no emitter, dropping the
high row-address bytes outright. The three guards are now >= 3 with the
>= 4 byte added. row_addr is uint32_t at all three sites.
- timer_ctrl() wrote the prescaler straight to a 16-bit PSC field.
TIM_ConfigPrescaler() neither masks nor validates, so any freq below
timer_clock/65537 was truncated and the timer ran at an unrelated rate
while timer->freq still recorded the requested one. That window is
reachable: both boards clock timers at 240 MHz, so the honest floor is
~3662 Hz while tim_config.h sets minfreq = 3000 and only [minfreq,
maxfreq] is checked - 3000 Hz lands in PSC as 14463, about 16.6 kHz.
Division by zero and any prescaler above 0xFFFF now return -RT_EINVAL.
The H7xx branch had the identical truncation, so the same two guards
are applied there too.
- n32_tim_enable_clock() closed each new branch with RT_ASSERT(RT_TRUE).
With RT_DEBUGING_ASSERT on, RT_ASSERT() expands to `if (!(EX))
rt_assert_handler(...)`, so that guard could never fire: a timer
matching none of the branch's instances enabled no clock at all and
the caller went on to touch an unclocked peripheral's registers. All
three branches are now RT_FALSE. The H7xx guard cannot fire today -
every instance its config header can hand out is already in that
branch's ladder - so fixing it arms the guard against a future
instance added to the table but not the ladder, rather than changing
any existing configuration.
- h497's sdram entry asked for BSP_SDRAM_SIZE=32 while sdram_port.h
documents the part as 8 MB and board/Kconfig declares `range 8 256` with
`default 8`; the 32 came from h760, whose own default happens to be 32.
- drv_hard_i2c.c had no init path at all for H47x_48x/H49x, leaving those
series with an unconfigured controller; the SCL rate now travels in the
config struct instead of being assumed.
- drv_qspi.c and drv_spi.c indexed buffers longer than 65535 bytes with
16-bit counters, which wraps at exactly 65536.
- n32eth_cfg.h is added because the H7xx and H49x SDKs' eth.h include it
but no package in the tree ships it. It probes for the series headers
because the SDK includes it before rtconfig.h can define SOC_SERIES_*,
with a part-macro fallback for ARM Compiler 5, which has no
__has_include() and is what every Keil project in this BSP uses.
- n32h487zgl7-evb now builds with its real 8 MHz crystal; left at the
header's 16 MHz default, RCC_GetClocksFreqValue() reports every clock at
twice its value and the timer prescalers come out twice too large.
- n32h760zil7-stb's timer menus had no mutual exclusion at all, so a timer
instance could be enabled as both a clock timer and a pulse encoder; 24
ISR symbols are defined by both drivers under those two guards, so only
the linker would have caught it. Its 14 PWM menus and its 14 encoder
entries now carry the same guard as the two new boards', using the
PWMn == PULSE_ENCODERN == instance n mapping that config/h7xx's
pulse_encoder_config.h establishes. On the PWM side that guard is a
resource guard, not a link one: drv_pwm.c defines no ISRs.
- the same board's LPTIM menu selected RT_USING_LPTIMER, which is not
declared anywhere in the tree. A select of an undeclared symbol is an
implicit symbol and raises no diagnostic, so the line had never done
anything; it is dropped, as the two new menus already do. Three stm32
boards still carry it and are left alone.
The H49x LPTIM EXTI lines needed the user manual rather than the SDK to
settle, and the manual sides with the driver: N32H49x maps EXTI line 21 to
the LPTIM1 wakeup event and line 22 to LPTIM2, which is what
n32_lptim_get_exti_line() returns. The headers disagree only because
n32h49x_exti.h's EXTI_LINE16..24 block is a verbatim copy of
n32h47x_48x_exti.h's - that one carries on past line 24 and names 25/26 as
the LPTIM events with 21/22 as COMP1/COMP4 - while the H49x series has no
comparator in its SDK at all, so its copy of that text is stale. The
driver states the reasoning in a comment rather than the bare value.
The H49x timer clock-source bits needed the user manual rather than the SDK
to settle. For GTIM8/9/10 (RCC_CFG2 bit 27) h49x names the cleared case
RCC_GTIM_CLKSRC_SYSCLKDIV where h47x_48x names it RCC_GTIM_CLKSRC_PCLK, and
the manual sides with the driver's arithmetic: bit 27 selects SYSCLK, or
SYSCLK/(APB2 prescaler / 2) when that prescaler is engaged - the same rule
the driver writes from the HCLK side as PCLK2 doubled whenever PCLK2 is
below HCLK. Both boards hold AHBPRES at RCC_SYSCLK_DIV1, so HCLK and SYSCLK
are the same 240 MHz and either spelling gives the same number. The driver
tests the raw bit and not either family's constant, so the naming difference
never reaches the code. The same chapter confirms bit 28's inversion, which
the ATIM branches already follow.
Verified: all three boards build from scratch under --strict (gcc -Werror)
with zero diagnostics; all 51 ci-attach entries build clean; the three
series were rebuilt after the assert fix, each through the --attach path
that compiles its branch (devices.timer on all three boards - h760's
default leaves BSP_USING_CLOCK_TIMER off, so drv_tim.c is not compiled by
it at all), rebuilt again after the Kconfig guards, whose
effect was checked by loading the tree with kconfiglib and confirming that
clock-timer ATIM1 with pulse encoder1 goes from satisfiable to unsatisfiable
while a non-colliding pair is left alone); the NAND row-address arms were
confirmed compiled by injecting #error markers and rebuilding through the
real --attach path; each board's committed .config and rtconfig.h reproduce
byte-for-byte from a fresh defconfig; and the CI clang-format gate reports
0 files / 0 lines.
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A question mark matches any one character, so *bt?* also matches libbtdm. Restrict that separator to a slash.
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Object paths on Windows use backslashes, so the forward-slash globs left _global_interrupt_handler in flash and the vector JAL could not reach it.
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- Enable SPI6 on-chip driver with TX/RX selectable DMA/BDMA modes
(BDMA options come from the shared HAL_Drivers Kconfig)
- Reserve the WS2812 BDMA buffer section (.ws2812_bdma) in SRAM4
across GCC/IAR/MDK5 linker scripts for a standalone package
- Sync CubeMX configuration and regenerate MDK5 project
- Update README with SPI6/BDMA support status
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Newer GCC emits C++ global constructors into .init_array, which many
linker scripts keep outside [__ctors_start__, __ctors_end__), so they
never ran. Walk __init_array_start/__init_array_end (weak) as well,
skipping entries already covered by the ctors range.
Add RT_USING_CPP_CRT_INIT for ports whose startup runtime already runs
.init_array, default on for the simulator. With it set, only the
.init_array walk is skipped; the ctors range is still walked.
Renesas RA/RA_WIRELESS/RZ families select it when C++ is enabled: FSP
SystemInit() already walks .init_array, so boards whose linker script
only provides __init_array_* would run constructors twice. Boards that
fold .init_array into the ctors range (ra6m3-hmi-board, ra8d1, rz)
still run them once via RT-Thread.
Also source env.sh and restore RTT_EXEC_PATH in ToolsCI project generate
and dist steps so scons is on PATH (exit 127) and the ARM toolchain path
is not overwritten by env.sh.
Fixes #11778
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* [bsp][esp32-c6] add ESP32-C6-DevKitC-1 support
Add bsp/ESP/ESP32_C6. Default image is GPIO, UART0 and ADC. The C6 IDF sources are not in RT-Thread-packages/esp-idf yet.
* [bsp][esp32-c6] fix CI format, C6 package and CH32V203 D6 build
clang-format the files the format check rejected. Fetch the C6 scons
branch when the downloaded ESP-IDF package has no C6 target. Patch the
CH32V20x SDK under libraries so a D6 build no longer calls Exit().
* [bsp][esp32-c6] fetch mbedtls and stop pkgs from pulling the C6 branch
* [bsp][esp32-c6] rebuild CI against the package branch tip
* [bsp][esp32-c6] rebuild CI against the strict-mode package tip
* [bsp][esp32-c6] fix the reviewed ADC, math and package pin bugs
Keep the IDF tree on the reviewed commit, and stop the ADC and critical-section paths from reporting success when they did not.
* [bsp][esp32-c6] reserve stuck interrupt lines and lock ADC
CPU lines 3 and 4 never latch an enable, so copying the handler left the non-IRAM mask on the old line. Reserve those lines and let the allocator write the mask and the route together. The C6 oneshot registers are shared, so one mutex covers enable and convert.
* [bsp][esp32-c6] list the peripherals this board actually runs
GPIO, UART0 and ADC1 have been read on the DevKitC-1. Radios and the untested buses stay marked unsupported.
* [bsp][esp32-c6] keep SPI unsupported after the loopback mismatch
GPIO7 shorted to GPIO2 returned 0xA5000000 for a sent 0xA5, so the table does not mark SPI supported.
---------
Co-authored-by: seteiro <[email protected]>
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IlinkIcfFile in 5 BSP template.ewp files pointed to absolute paths on other developers' machines, which scons --target=iar copies into the generated project.ewp and breaks builds elsewhere.
Affected: asm9260t, mm32f3270-100ask-pitaya, stm32f103-100ask-mini, stm32f103-100ask-pro and imxrt1180-nxp-evk/cm7 (3 configurations).
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* [bsp/Infineon] Fix PWM macro mismatches left by the CHx_PORTy rename
Commit e5382cb733 renamed the PWM table guards in drv_pwm.c to the
CHx_PORTy convention but only adapted the psoc6-evk Kconfig, leaving
several mismatches behind:
- The psoc6-evaluationkit-062S2 slider sample still tested the old
flat name BSP_USING_PWM0_PORT0 while the board Kconfig defines
BSP_USING_PWM0_CH0_PORT0, so the PWM init was compiled out.
- The PORT13 entry was renamed to BSP_USING_PWM0_CH7_PORT13, a macro
that no Kconfig defines, and the channel is wrong anyway:
PWM0_CH3_PORT13_CONFIG carries .channel = 3, PORT13 sits under the
PWM0 CH3 menu, and the slider demo selects CH3 + PORT13.
- The PSOC62 template and five psoc6 boards (cy8ckit-062-BLE,
cy8ckit-062-WIFI-BT, cy8ckit-062S2-43012, cy8ckit-062s4,
cy8cproto-062S3-4343W) still define the old flat names.
Fix all of them by migrating the evaluationkit sample to
BSP_USING_PWM0_CH0_PORT0 and renaming the PORT13 group to
BSP_USING_PWM0_CH3_PORT13 across drv_pwm.c, the PSOC62 template and
the five boards' Kconfigs/slider samples, so Kconfig, driver table
and samples match again.
Note: the sibling guards BSP_USING_PWM0_CH7_PORT2/5/7/9/10/12 are
still not generated by these boards' Kconfigs; left untouched for a
separate discussion.
* style: format code with clang-format [skip ci]
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Configure TX as alternate-function push-pull and RX as pull-up input on GD32E50x/F10x/F20x/F30x. Remove the GPIO API alias that incorrectly configured both pins as general-purpose push-pull outputs.
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Add the missing UART4 RX DMA definitions for STM32H7.
UART4 RX DMA uses DMA1 Stream0 with the UART4 RX DMA request.
The configuration is enabled when BSP_UART4_RX_USING_DMA is selected.
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'NAME_MAX' to 24 #11798
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将函数声明从static改为extern，解决跨文件调用时的链接错误，
确保DMA、BDMA和GPDMA类型的日志标签能够正确生成。
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The N32H7xx branch of drv_hard_i2c.c had never been compiled. The file takes
its peripheral declarations from board.h, and only n32h497zgl7-evb includes
n32h49x_i2c.h, so on H7xx every I2C symbol was undefined and the option could
not build at all. Include the peripheral header from the driver itself, the way
drv_sdram.c already does.
I2C_ABORT_ON_TIMEOUT also degraded to a bare `state = I2C_READY` on H7xx, at the
four rt_completion_wait() timeouts in n32_i2c_master_xfer(). The H49x
implementation is written against the older IP - I2C_ClrIntPendingBit,
I2C_STS2_BUSY, I2C_CTRL1_STOPGEN - none of which exist in the H7xx SDK, so give
H7xx its own teardown. It disables the interrupt and DMA request sources,
disables the DMA channel that would otherwise stay armed against the caller's
buffer, releases the bus and clears the status residue.
Only flags with a matching INTCLR bit may be passed to I2C_ClrFlag(), which is a
plain "INTCLR |= flag" write; TFC (0x40) and BUSY (0x8000) have none.
I2C_Configuration() was called from n32_i2c_init() but defined nowhere in the
tree. It is a board hook for pin mux, which is not the driver's job - the H49x
path configures no pins either - so drop the call.
Verified by building n32h760zil7-stb with BSP_USING_HARD_I2C1 and its TX/RX DMA
enabled, which now compiles and links with no warnings, and n32h497zgl7-evb with
I2C1/I2C2 DMA enabled, whose image size is unchanged. Neither board routes I2C
pins yet, so this is build-verified only, not hardware-verified.
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drv_sdram.c includes <sdram_port.h> unconditionally under BSP_USING_SDRAM,
and n32h497zgl7-evb had no such header, so the option could not build at
all. Add one for the M12L64164A fitted on this board: 4 banks x 1M x 16
bits = 8 MB, 12 row address bits, 8 column address bits, SDRAM1 mapped at
0x98000000. The timing values are the ones validated on this board in
hardware.
Three of the Kconfig defaults described a different part:
BSP_SDRAM_DATA_WIDTH_SEL default 32 -> 16
BSP_SDRAM_COLUMN_BITS_SEL default 9 -> 8
BSP_SDRAM_SIZE default 32 -> 8
BANK1, ROW_BIT_12 and CAS_LATENCY_3 already matched and are unchanged.
Verified by building n32h497zgl7-evb with BSP_PERIPH_PIN_CFG_READY and
BSP_USING_SDRAM enabled: drv_sdram.c and the SDK's n32h49x_sdram.c compile
and link with no warnings.
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- qspi: both XSPI variants poll the status flags with no bound, so an
unresponsive bus hangs the caller and silently defeats the timeout it
passed in. Route every wait through the timeout-carrying helpers,
return -RT_ETIMEOUT and disable the controller on failure, and replace
the "poll then send" loops with one bounded wait per element.
- hard_i2c: the interrupt receive path programs the BYTENUM window once
and never reloads it, so a longer message was truncated and still
reported as success; refuse it with -RT_EINVAL (enable RX DMA for
longer reads) instead of capping XferSize. Stop capping the transmit
byte count at the window size as well: BYTENUM counts received bytes
only, and the cap stopped feeding DAT after byte 255 while TXDATE
stayed asserted. Reject RT_I2C_NO_START/RT_I2C_NO_STOP on the series
without frame chaining, where they would silently become a fresh START
and a STOP, and tear the DMA channel down when the address phase times
out instead of leaving it armed against a buffer about to unwind.
- spi: the H7xx LLI chain advanced the memory side by SPI_DMA_BLOCK_MAX
bytes although BlkTfrSize counts elements, so a 16-bit transfer walked
half a word early per node; advance by elements and scale both the
chunk offset and the staging buffer by the data width. Propagate the
DMA arm failure that was ignored.
- nand: an odd data length has no halfword-only encoding on the 16-bit
bus and padding would program a byte the caller never asked for, so
refuse it before the command phase; issue the empty-page dummy store
as a halfword there too, where 8-bit AHB writes are unsupported.
- Kconfig: gate the Ethernet/SDRAM/LCD/QSPI/NAND options behind
BSP_PERIPH_PIN_CFG_READY on all three boards. The peripheral clock and
IO are not configured for these boards yet, so selecting one of them
builds a driver whose pins stay in the reset function.
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- libraries/N32_Drivers: add ADC/DAC/I2C/SPI config headers for the
h47x_48x, h49x and h7xx series, and extend the shared drivers
(adc, dac, eth, gpio, hard_i2c, nand, qspi, sdram, spi, usart, wdt).
- n32h487zgl7-evb / n32h497zgl7-evb: add board ports (femc_timing,
phy_reset, usb_config) and update Kconfig, SConscript, rtconfig and
the IAR/Keil project files.
- n32h760zil7-stb: update Kconfig and rtconfig.
- CI: register the three n32hxxx boards.
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* [bsp][stm32] Add stm32n657-st-nucleo BSP
* style: format STM32 HAL drivers and STM32N657 BSP with clang-format
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- Unify DMA/BDMA/GPDMA descriptors in drv_dma (common fields + per-type union)
- Support BDMA in SPI driver with h7 dma/spi config header updates
- Add SPI6 TX/RX BDMA Kconfig options for H7
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The link points to launchpad.net, which shut down its gcc-arm-embedded
downloads years ago (the URL now returns 503), and the tarball it names
is a 2016 Q3 build (gcc 5.4).
- Point to Arm GNU Toolchain Downloads, matching the link already used
in bsp/nxp/imx/imx91/README.md. The old gnu-rm page covers the
GNU Arm Embedded Toolchain, which Arm has superseded.
- Mention installing the toolchain from the distribution package
manager, with Debian/Ubuntu as an example, since rtconfig.py already
defaults EXEC_PATH to /usr/bin. libstdc++-arm-none-eabi-newlib is
listed because LFLAGS links with -lsupc++.
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修复 SCI SPI 分频参数和运行时配置生命周期，保持位宽单位一致，应用模式及片选配置，并在收发超时或错误后停止传输、清理状态。
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Without CXX = rtconfig.CXX the scons Environment falls back to the
default host 'g++', and CXXFLAGS stays an empty CLVar, so the C++
group flags appended by DefineGroup end up as a single unquoted
argument and the build fails as soon as RT_USING_CPLUSPLUS is on:
g++: error: -fno-exceptions -fno-rtti ... -Wl,--gc-sections:
linker input file not found: No such file or directory
Found by the CI C++ ctor (.init_array) check.
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在 v1/v2 串口文件边界复制已知用户参数，补齐 v2 unread count 和 termios 缓冲区保护。
在 imx6ull UART 编程前校验波特率，并在硬件配置成功后提交串口状态。
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