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* [libcpu][risc-v] Refactor the RISC-V architecture port
Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.
- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration
Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.
Signed-off-by: GuEe-GUI <[email protected]>
* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk
Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.
Signed-off-by: seteiro <[email protected]>
* [libcpu][risc-v] Fix per-CPU page table mapping
- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings
Signed-off-by: GuEe-GUI <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
Signed-off-by: seteiro <[email protected]>
Co-authored-by: seteiro <[email protected]>
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* [DM/OFW][PCI] Fix address translation and PCI resource enumeration
Rework OFW address translation to walk nested bus ranges in the correct
direction and cache "ranges" and "dma-ranges" independently. Handle PCI
three-cell addresses without treating the PCI flags cell as part of the
address, and fix CPU-to-DMA and DMA-to-CPU translation across nested
buses.
Fix PCI BAR sizing and assignment by disabling address decoding during
probing, preserving BAR attribute bits, and programming 64-bit BARs
correctly. Add device enable and disable helpers so resources and bus
mastering are enabled before driver probe.
Program bridge memory and prefetch windows while scanning downstream
buses, correctly link child buses into the PCI bus hierarchy, and avoid
unnecessary PCIe link retraining when the link is already active.
Allow host bridges without a device-tree pci-domain property by
allocating unique domains dynamically, while preserving explicit domain
assignments.
Fix MSI and MSI-X IRQ setup, rollback, vector addressing, and affinity
selection.
Add the Raspberry Pi PCI vendor ID for RP1 and other downstream devices.
Signed-off-by: GuEe-GUI <[email protected]>
* style: format code with clang-format
* style: format complete changed files with clang-format
* drivers: pci: address OFW review feedback
* style: format PCI and OFW changes for current master
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Signed-off-by: GuEe-GUI <[email protected]>
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Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.
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Fixup fdt address reg and cells parse.
Support only option name way for earlycon.
Find the console device when using "stdout-path".
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Fix garble caused by empty implementation of earlycon series
function in driver.If driver doesn't offer earlycon_id or rt_f
dt_earlycon_id.setup function but open option, the checking
of best_earlycon_id will failed.
Signed-off-by: 1078249029 <[email protected]>
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device node should not probe in stub if device is not available.
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Signed-off-by: GuEe-GUI <[email protected]>
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The `rt_fdt_scan_chosen_stdout` will init fdt_earlycon data
without `msg` only, the `msg_idx` should not clean, too.
Because we check if have old messages by `msg_idx`
Signed-off-by: GuEe-GUI <[email protected]>
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* [DM/FEATURE] Support reset controller
Reset controllers are central units that control
the reset signals to multiple peripherals.
The reset controller API is split into two parts:
1. The consumer driver interface, which allows
peripheral drivers to request control over
their reset input signals
2. The reset controller driver interface
which is used by drivers for reset controller devices to
register their reset controls to provide them to the consumers.
* [RESET/SIMPLE] Support simple reset
Currently this driver supports:
- Altera SoCFPGAs
- ASPEED BMC SoCs
- Bitmain BM1880 SoC
- Realtek SoCs
- RCC reset controller in STM32 MCUs
- Allwinner SoCs
- SiFive FU740 SoCs
- Sophgo SoCs
Signed-off-by: GuEe-GUI <[email protected]>
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1. Default return OK when input NULL (if is not necessary in device).
2. Support object parse in OFW.
3. Support CLK depends fix auto.
4. Fixup rt_clk_array_prepare_enable and rt_clk_array_disable_unprepare.
Signed-off-by: GuEe-GUI <[email protected]>
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1.Fixup `fdt_reserved_memory_reg` loop time.
2.Fixup `rt_fdt_translate_address` cells value reader.
Signed-off-by: GuEe-GUI <[email protected]>
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DMA and CPU address view is different, we need to convert them:
+--------+ +--------+ +---------+ +--------+
| | | | | | | |
| CPUs | | DEV0 | | IOMMU <----+ | DEV1 |
| | | | | | | | |
+----+---+ +----+---+ +----+----+ | +----+---+
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0x200000 | 0x1000 | 0x1000 | | 0x8000 |
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+-------------+-----------+ +----------+
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+--------v----------------------------------------------------+
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| Address BUS |
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+-------------------------------------------------------------+
Signed-off-by: GuEe-GUI <[email protected]>
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Maybe use for memory/DMA buffer init before
ofw_node unflatten.
Signed-off-by: GuEe-GUI <[email protected]>
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The ofw parse should:
1. Check obj_name EQU the current node's rt_data.
2. Find the next object name.
3. goto "2" until obj_name EQU the cmp_cell's obj_name.
Signed-off-by: GuEe-GUI <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
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rt_ofw_append_child append a new child node and return,
ref_get is necessary.
Signed-off-by: GuEe-GUI <[email protected]>
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* memory setup using memblock
* map pages later
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* [Feature] Power domain for device
1.Support device power on/off.
2.Support attach/detach device.
3.Support power domain driver api.
Signed-off-by: GuEe-GUI <[email protected]>
* [DM/platform] Enhanced platform bus
1.Add power domain for device.
2.Support `remove` and `shutdown` bus interface.
Signed-off-by: GuEe-GUI <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
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[OFW] io ranges use ptr array to storage without ofw data
ofw data is private data for every ofw node that
the drivers of ofw node will use item.
replace the ranges supported to a ptr array.
the ptr array size is config by `RT_USING_OFW_BUS_RANGES_NUMBER`
Signed-off-by: GuEe-GUI <[email protected]>
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The OFW map id is always use in DMA, PCI, IOMMU
bus system to find the device identity. this is
a access interface.
Signed-off-by: GuEe-GUI <[email protected]>
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`map_len` and `map_mask_len` is the count of elements,
not the bytes size of elements.
Signed-off-by: GuEe-GUI <[email protected]>
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* fix ofw_alias_scan() bug
* fix tag_len
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* Fixed fdt memory adjustment bug
* Modify the memory adjustment logic
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fix some uninitialize err
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In this patch, a hook list has been introduced to address the concerns
regarding coupling issues arising from modifications to the serial code
for integrating TTY logic.
Signed-off-by: Shell <[email protected]>
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: xqyjlj <[email protected]>
Signed-off-by: Shell <[email protected]>
Co-authored-by: xqyjlj <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
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We support OFW API to replace fdt old API, and add
IRQ, IO, Platform-Bus, CPUs ... OFW node contorl.
To support work with Device Tree or ACPI in drivers
that use IRQ, we make a programmable interrupt
controller driver's model.
Signed-off-by: GuEe-GUI <[email protected]>
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