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2026-08-12feat(dm): support OFW on Cortex-M targetsRbb666
Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.
2026-06-22[utest][pin] add pin loopback utest (#11445)CYFS
* [utest][pin] add pin loopback utest * [utest][pin] add BSP CI coverage * [utest][pin] fix BSP CI config * [utest][pin] fix ra8p1 utest link section
2025-12-10[dm][pin][pinctrl] add new driverGuEe-GUI
1. ARM PL061 GPIO 2. Single Pinctrl Signed-off-by: GuEe-GUI <[email protected]>
2025-12-10[dm][pin] fixup the DM Kconfig import in DM mode onlyGuEe-GUI
Signed-off-by: GuEe-GUI <[email protected]>
2025-12-10[dm][pinctrl] new interface for 'pin_gpio_request'GuEe-GUI
Some GPIO should apply GPIO mode by pinctrl, add `pin_ctrl_gpio_request` for GPIO driver to apply it auto. Signed-off-by: GuEe-GUI <[email protected]>
2025-02-11[DM] Replace spinlock static init by RT_DEFINE_SPINLOCKGuEe-GUI
Signed-off-by: GuEe-GUI <[email protected]>
2024-12-02[DM/FEATURE] Support import SoC PIN configGuEe-GUI
Signed-off-by: GuEe-GUI <[email protected]>
2024-12-02[DM/FEATURE] Support virtual pinGuEe-GUI
1. There is only one GPIO device in System. 2. For Pin API input is pin number 3. Add sets pin debounce time API. So we need a virtual pin for multi gpio chip. Signed-off-by: GuEe-GUI <[email protected]>
2024-12-02[DM/FIXUP] Fixup pin propname checkGuEe-GUI
Signed-off-by: GuEe-GUI <[email protected]>
2024-12-02[DM/FIXUP] Fixup pin flags get from OFWGuEe-GUI
Only check HIGH or LOW Signed-off-by: GuEe-GUI <[email protected]>
2024-12-02[DM/FIXUP] Fixup pin depend autoGuEe-GUI
Signed-off-by: GuEe-GUI <[email protected]>
2024-08-23[device] add dev_ prefix for file namesCXSforHPU
2024-03-29fix pin ofw variable init.geniusgogo
2024-03-23[pin] pin_read/write rt_uint8_t to rt_ssize_tkk
2024-02-29[component][drivers]add pinctrl/pin-irqchip (#8383)zms123456