1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
|
/**
*****************************************************************************
* @file cmem7_ddr.h
*
* @brief CMEM7 AES header file
*
*
* @version V1.0
* @date 3. September 2013
*
* @note
*
*****************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2>
*****************************************************************************
*/
#ifndef __CMEM7_DDR_H
#define __CMEM7_DDR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmem7.h"
#include "cmem7_conf.h"
/** @defgroup _MEM_TYPE
* @{
*/
enum _MEM_TYPE
{
MEM_DDR2=1,
MEM_DDR3
} ;
/**
* @}
*/
/** @defgroup _BUS_WIDTH
* @{
*/
enum _BUS_WIDTH
{
BUS_WIDTH_8,
BUS_WIDTH_16,
BUS_WIDTH_MAX
};
/**
* @}
*/
/** @defgroup _CHIP_TYPE
* @{
*/
enum _CHIP_TYPE
{
_32Mbx8,
_64Mbx8,
_128Mbx8,
_256Mbx8,
_512Mbx8,
_16Mbx16,
_32Mbx16,
_64Mbx16,
_128Mbx16,
_256Mbx16,
_512Mbx16,
CHIP_TYPE_MAX
};
/**
* @}
*/
/** @defgroup _CHIP_NUM
* @{
*/
enum _CHIP_NUM
{
CHIP_NUM_x1,
CHIP_NUM_x2,
CHIP_NUM_MAX
};
/**
* @}
*/
/** @defgroup MEM_CHIP_INFO
* @{
*/
typedef struct {
uint8_t mem_type; /*!< ddr type @ref _MEM_TYPE*/
uint8_t Bus_width; /*!< ddr qs bus width @ref _BUS_WIDTH*/
uint8_t Chip_type; /*!< chip type @ref _CHIP_TYPE*/
uint8_t Chip_num; /*!< chip number @ref _CHIP_NUM*/
uint8_t Chip_bank; /*!< chip bank number*/
} MEM_CHIP_INFO;
/**
* @}
*/
/** @defgroup DDR2MEM
* @{
*/
typedef struct {
uint32_t tCK; /*!< Period of clock(ps), not data period */
uint32_t tCL; /*!< tCL */
uint32_t tRCD; /*!< tRCD */
uint32_t tRP; /*!< tRP */
uint32_t tRC; /*!< tRC */
uint32_t tRAS; /*!< tRAS */
uint32_t tWR; /*!< tWR */
uint32_t tRRD; /*!< tRRD */
uint32_t tWTR; /*!< tWTR */
uint32_t tRTP; /*!< tRTP */
uint32_t tFAW; /*!< tFAW */
} DDR2MEM; /*!< DDR2时序定义 */
/**
* @}
*/
/** @defgroup DDR3MEM
* @{
*/
typedef struct {
uint32_t tCK; /*!< Period of clock(ps), not data period */
uint32_t tCL; /*!< tCL */
uint32_t tWCL; /*!< tWCL */
uint32_t tRCD; /*!< tRCD */
uint32_t tRAS; /*!< tRAS */
uint32_t tRP; /*!< tRP */
uint32_t tRC; /*!< tRC */
uint32_t tRRD; /*!< tRRD */
uint32_t tFAW; /*!< tFAW */
uint32_t tWR; /*!< tWR */
uint32_t tRTP; /*!< tRTP */
uint32_t tZQoper; /*!< tZQCL */
uint32_t tZQCS; /*!< tZQCS */
} DDR3MEM; /*!< DDR3时序定义 */
/**
* @}
*/
/** @defgroup DDR2PREDEF
* @{
*/
extern const DDR2MEM DDR2PREDEF[]; /*!< Pre-defined DDR2 Timing in library */
#define DDR2_400C 0 /*!< sg5E: DDR2-400C CL=4, tCK=5000ps */
/**
* @}
*/
/** @defgroup DDR3PREDEF
* @{
*/
extern const DDR3MEM DDR3PREDEF[]; /*!< Pre-defined DDR3 Timing in library */
#define DDR3_400 0
#define DDR3_667 1
/**
* @}
*/
/**
* @brief DDR Timing Configuration
* @param[in] chip information ,A pointer to struct @ref MEM_CHIP_INFO
* @param[in] ddr A pointer to struct @ref DDR2MEM or @ref DDR3MEM that specified DDR Timing. Some typital DDR2/3 Timings are defined in arrays @ref DDR2PREDEF and @ref DDR3PREDEF.
* @retval void
*/
BOOL DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr);
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_DDR_H */
|
