summaryrefslogtreecommitdiff
path: root/bsp/allwinner/libraries/sunxi-hal/hal/source/ce/platform/ce_sun20iw2.h
blob: c5dd3a42026fef019207d3add34410d26abe2f83 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
#ifndef __CE_PLATFORM_H
#define __CE_PLARFORM_H


#ifdef __cplusplus
extern "C"
{
#endif

/*define CE version*/
#define CE_SUPPORT_CE_V3_1

#define CE_NS_BASE_REG          (0x40004000)
#define CE_S_BASE_REG           (0x40004800)

#define SUNXI_IRQ_CE            79
#define SUNXI_IRQ_CE_NS         80

#define SUNXI_CLK_CE CLK_BUS_SS
#define SUNXI_CLK_MBUS_CE CLK_MBUS_CE
#define SUNXI_RST_CE RST_SS

#define SUNXI_CCM_BASE          (0x03001000)
#define CCMU_CE_CLK_REG         (SUNXI_CCM_BASE + 0x680)
#define CCMU_CE_BGR_REG         (SUNXI_CCM_BASE + 0x68C)
#define MBUS_MAT_CLK_GATING_REG     (SUNXI_CCM_BASE + 0x804)

#define CE_CLK_SRC_MASK         (0x1)
#define CE_CLK_SRC_SEL_BIT      (24)
#define CE_CLK_SRC          (0x01)
#define CE_CLK_DIV_RATION_N_BIT     (8)
#define CE_CLK_DIV_RATION_N_MASK    (0x3)
#define CE_CLK_DIV_RATION_N     (0)

#define CE_CLK_DIV_RATION_M_BIT     (0)
#define CE_CLK_DIV_RATION_M_MASK    (0xF)
#define CE_CLK_DIV_RATION_M     (3)

#define CE_SCLK_ONOFF_BIT       (31)
#define CE_SCLK_ON          (1)

#define CE_GATING_PASS          (1)
#define CE_GATING_BIT           (0)
#define CE_RST_BIT          (16)
#define CE_DEASSERT         (1)

#endif