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/*
* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
*
* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
* the the People's Republic of China and other countries.
* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
*
* DISCLAIMER
* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
* IF YOU NEED TO INTEGRATE THIRD PARTY'S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
* IN ALLWINNERS'SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY'S TECHNOLOGY.
*
*
* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DMA_SUN50IW11_H__
#define __DMA_SUN50IW11_H__
#if defined(CONFIG_CORE_DSP0)
#include <hal_prcm.h>
#define SUNXI_DMAC_PBASE (0x07091000)
#define DMA_IRQ_NUM (6)
#define NR_MAX_CHAN 8 /* total of channels */
#define START_CHAN_OFFSET 0
#define HAL_CLK_PERIPH_DMA CCU_MOD_CLK_R_DMA
#else
/* CPUX */
#endif /* CONFIG_CORE_DSP0 */
/*
* The source DRQ type and port corresponding relation
*/
#define DRQSRC_SRAM 0
#define DRQSRC_PSRAM_CBUS 0
#define DRQSRC_SDRAM 0
/* #define DRQSRC_RESEVER 2 */
#define DRQSRC_DAUDIO_0_RX 3
#define DRQSRC_DAUDIO_1_RX 4
#define DRQSRC_UART0_RX 5
/* #define DRQSRC_RESEVER 6 */
#define DRQSRC_TWI0_RX 7
#define DRQSRC_DMIC 8
#define DRQSRC_AUDIO_CODEC 9
/* #define DRQSRC_RESEVER 10 */
#define DRQSRC_MAD_RX 11
#define DRQSRC_PSRAM_SBUS 12
/*
* The destination DRQ type and port corresponding relation
*/
#define DRQDST_SRAM 0
#define DRQDST_PSRAM_CBUS 0
#define DRQDST_SDRAM 0
/* #define DRQDST_RESEVER 2 */
#define DRQDST_DAUDIO_0_TX 3
#define DRQDST_DAUDIO_1_TX 4
#define DRQDST_UART0_TX 5
/* #define DRQDST_RESEVER 6 */
#define DRQDST_TWI0_TX 7
/* #define DRQDST_RESEVER 8 */
#define DRQDST_AUDIO_CODEC 9
/* #define DRQDST_RESEVER 10 */
#define DRQDST_MAD_TX 11
#define DRQDST_PSRAM_SBUS 12
#endif /*__DMA_SUN50IW11_H__ */
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