1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
|
//*****************************************************************************
//
// am_reg_nvic.h
//! @file
//!
//! @brief Register macros for the NVIC module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2017, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_NVIC_H
#define AM_REG_NVIC_H
//*****************************************************************************
//
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_NVIC_NUM_MODULES 1
#define AM_REG_NVICn(n) \
(REG_NVIC_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_NVIC_ISER0_O 0xE000E100
#define AM_REG_NVIC_ICER0_O 0xE000E180
#define AM_REG_NVIC_ISPR0_O 0xE000E200
#define AM_REG_NVIC_ICPR0_O 0xE000E280
#define AM_REG_NVIC_IABR0_O 0xE000E300
#define AM_REG_NVIC_IPR0_O 0xE000E400
#define AM_REG_NVIC_IPR1_O 0xE000E404
#define AM_REG_NVIC_IPR2_O 0xE000E408
#define AM_REG_NVIC_IPR3_O 0xE000E40C
#define AM_REG_NVIC_IPR4_O 0xE000E410
#define AM_REG_NVIC_IPR5_O 0xE000E414
#define AM_REG_NVIC_IPR6_O 0xE000E418
#define AM_REG_NVIC_IPR7_O 0xE000E41C
//*****************************************************************************
//
// NVIC_ISER0 - Interrupt Set-Enable Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0.
#define AM_REG_NVIC_ISER0_BITS_S 0
#define AM_REG_NVIC_ISER0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_ISER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_ICER0 - Interrupt Clear-Enable Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0.
#define AM_REG_NVIC_ICER0_BITS_S 0
#define AM_REG_NVIC_ICER0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_ICER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_ISPR0 - Interrupt Set-Pending Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0.
#define AM_REG_NVIC_ISPR0_BITS_S 0
#define AM_REG_NVIC_ISPR0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_ISPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_ICPR0 - Interrupt Clear-Pending Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0.
#define AM_REG_NVIC_ICPR0_BITS_S 0
#define AM_REG_NVIC_ICPR0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_ICPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_IABR0 - Interrupt Active Bit Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0.
#define AM_REG_NVIC_IABR0_BITS_S 0
#define AM_REG_NVIC_IABR0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_IABR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_IPR0 - Interrupt Priority Register 0
//
//*****************************************************************************
// Priority assignment for interrupt vector 3.
#define AM_REG_NVIC_IPR0_PRI_N3_S 24
#define AM_REG_NVIC_IPR0_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR0_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 2.
#define AM_REG_NVIC_IPR0_PRI_N2_S 16
#define AM_REG_NVIC_IPR0_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR0_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 1.
#define AM_REG_NVIC_IPR0_PRI_N1_S 8
#define AM_REG_NVIC_IPR0_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR0_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 0.
#define AM_REG_NVIC_IPR0_PRI_N0_S 0
#define AM_REG_NVIC_IPR0_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR0_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR1 - Interrupt Priority Register 1
//
//*****************************************************************************
// Priority assignment for interrupt vector 7.
#define AM_REG_NVIC_IPR1_PRI_N3_S 24
#define AM_REG_NVIC_IPR1_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR1_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 6.
#define AM_REG_NVIC_IPR1_PRI_N2_S 16
#define AM_REG_NVIC_IPR1_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR1_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 5.
#define AM_REG_NVIC_IPR1_PRI_N1_S 8
#define AM_REG_NVIC_IPR1_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR1_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 4.
#define AM_REG_NVIC_IPR1_PRI_N0_S 0
#define AM_REG_NVIC_IPR1_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR1_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR2 - Interrupt Priority Register 2
//
//*****************************************************************************
// Priority assignment for interrupt vector 11.
#define AM_REG_NVIC_IPR2_PRI_N3_S 24
#define AM_REG_NVIC_IPR2_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR2_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 10.
#define AM_REG_NVIC_IPR2_PRI_N2_S 16
#define AM_REG_NVIC_IPR2_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR2_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 9.
#define AM_REG_NVIC_IPR2_PRI_N1_S 8
#define AM_REG_NVIC_IPR2_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR2_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 8.
#define AM_REG_NVIC_IPR2_PRI_N0_S 0
#define AM_REG_NVIC_IPR2_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR2_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR3 - Interrupt Priority Register 3
//
//*****************************************************************************
// Priority assignment for interrupt vector 15.
#define AM_REG_NVIC_IPR3_PRI_N3_S 24
#define AM_REG_NVIC_IPR3_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR3_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 14.
#define AM_REG_NVIC_IPR3_PRI_N2_S 16
#define AM_REG_NVIC_IPR3_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR3_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 13.
#define AM_REG_NVIC_IPR3_PRI_N1_S 8
#define AM_REG_NVIC_IPR3_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR3_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 12.
#define AM_REG_NVIC_IPR3_PRI_N0_S 0
#define AM_REG_NVIC_IPR3_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR3_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR4 - Interrupt Priority Register 4
//
//*****************************************************************************
// Priority assignment for interrupt vector 19.
#define AM_REG_NVIC_IPR4_PRI_N3_S 24
#define AM_REG_NVIC_IPR4_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR4_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 18.
#define AM_REG_NVIC_IPR4_PRI_N2_S 16
#define AM_REG_NVIC_IPR4_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR4_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 17.
#define AM_REG_NVIC_IPR4_PRI_N1_S 8
#define AM_REG_NVIC_IPR4_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR4_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 16.
#define AM_REG_NVIC_IPR4_PRI_N0_S 0
#define AM_REG_NVIC_IPR4_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR4_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR5 - Interrupt Priority Register 5
//
//*****************************************************************************
// Priority assignment for interrupt vector 23.
#define AM_REG_NVIC_IPR5_PRI_N3_S 24
#define AM_REG_NVIC_IPR5_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR5_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 22.
#define AM_REG_NVIC_IPR5_PRI_N2_S 16
#define AM_REG_NVIC_IPR5_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR5_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 21.
#define AM_REG_NVIC_IPR5_PRI_N1_S 8
#define AM_REG_NVIC_IPR5_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR5_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 20.
#define AM_REG_NVIC_IPR5_PRI_N0_S 0
#define AM_REG_NVIC_IPR5_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR5_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR6 - Interrupt Priority Register 6
//
//*****************************************************************************
// Priority assignment for interrupt vector 27.
#define AM_REG_NVIC_IPR6_PRI_N3_S 24
#define AM_REG_NVIC_IPR6_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR6_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 26.
#define AM_REG_NVIC_IPR6_PRI_N2_S 16
#define AM_REG_NVIC_IPR6_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR6_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 25.
#define AM_REG_NVIC_IPR6_PRI_N1_S 8
#define AM_REG_NVIC_IPR6_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR6_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 24.
#define AM_REG_NVIC_IPR6_PRI_N0_S 0
#define AM_REG_NVIC_IPR6_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR6_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR7 - Interrupt Priority Register 7
//
//*****************************************************************************
// Priority assignment for interrupt vector 31.
#define AM_REG_NVIC_IPR7_PRI_N3_S 24
#define AM_REG_NVIC_IPR7_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR7_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 30.
#define AM_REG_NVIC_IPR7_PRI_N2_S 16
#define AM_REG_NVIC_IPR7_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR7_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 29.
#define AM_REG_NVIC_IPR7_PRI_N1_S 8
#define AM_REG_NVIC_IPR7_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR7_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 28.
#define AM_REG_NVIC_IPR7_PRI_N0_S 0
#define AM_REG_NVIC_IPR7_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR7_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
#endif // AM_REG_NVIC_H
|
