1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
|
#include "bflb_i2s.h"
#include "bflb_clock.h"
#include "hardware/i2s_reg.h"
void bflb_i2s_init(struct bflb_device_s *dev, const struct bflb_i2s_config_s *config)
{
uint32_t reg_base;
uint32_t regval;
uint32_t div;
reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
/* disable I2S */
regval &= ~I2S_CR_I2S_M_EN;
regval &= ~I2S_CR_I2S_S_EN;
regval &= ~I2S_CR_I2S_TXD_EN;
regval &= ~I2S_CR_I2S_TXD_EN;
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
if (config->channel_mode == I2S_CHANNEL_MODE_NUM_1) {
/* Mono mode */
regval |= I2S_CR_MONO_MODE;
regval &= ~I2S_CR_FS_CH_CNT_MASK;
} else {
regval &= ~I2S_CR_MONO_MODE;
regval &= ~I2S_CR_FS_CH_CNT_MASK;
regval |= (config->channel_mode - 1) << I2S_CR_FS_CH_CNT_SHIFT;
}
/* disable mute */
regval &= ~I2S_CR_MUTE_MODE;
if (config->format_mode == I2S_MODE_DSP_SHORT_FRAME_SYNC) {
/* dsp modeA/B short frame sync, there is only one bclk cycle */
regval |= I2S_CR_FS_1T_MODE;
} else {
regval &= ~I2S_CR_FS_1T_MODE;
}
/* frame/data width */
regval &= ~I2S_CR_FRAME_SIZE_MASK;
regval &= ~I2S_CR_DATA_SIZE_MASK;
regval |= config->frame_width << I2S_CR_FRAME_SIZE_SHIFT;
regval |= config->data_width << I2S_CR_DATA_SIZE_SHIFT;
if (config->format_mode == I2S_MODE_LEFT_JUSTIFIED) {
/* left justified*/
regval &= ~I2S_CR_I2S_MODE_MASK;
} else if (config->format_mode == I2S_MODE_RIGHT_JUSTIFIED) {
/* right justified*/
regval &= ~I2S_CR_I2S_MODE_MASK;
regval |= 1 << I2S_CR_I2S_MODE_SHIFT;
} else {
/* dsp mode */
regval &= ~I2S_CR_I2S_MODE_MASK;
regval |= 2 << I2S_CR_I2S_MODE_SHIFT;
}
/* fs_offset_cycle */
if (config->fs_offset_cycle) {
regval |= I2S_CR_OFS_EN;
regval &= ~I2S_CR_OFS_CNT_MASK;
regval |= ((config->fs_offset_cycle - 1) << I2S_CR_OFS_CNT_SHIFT) & I2S_CR_OFS_CNT_MASK;
} else {
regval &= ~I2S_CR_OFS_EN;
}
/* rx mono mode L-channel */
regval &= ~I2S_CR_MONO_RX_CH;
/* MSB */
regval &= ~I2S_CR_ENDIAN;
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
/* integer frequency segmentation by rounding */
div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_I2S, dev->idx) / 2 * 10 / config->bclk_freq_hz + 5) / 10;
div = (div) ? (div - 1) : 0;
div = (div > 0xfff) ? 0xfff : div;
/* bclk timing config */
regval = getreg32(reg_base + I2S_BCLK_CONFIG_OFFSET);
regval &= ~I2S_CR_BCLK_DIV_L_MASK;
regval &= ~I2S_CR_BCLK_DIV_H_MASK;
regval |= div << I2S_CR_BCLK_DIV_L_SHIFT;
regval |= div << I2S_CR_BCLK_DIV_H_SHIFT;
putreg32(regval, reg_base + I2S_BCLK_CONFIG_OFFSET);
/* fifo threshold config */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_1_OFFSET);
regval &= ~I2S_TX_FIFO_TH_MASK;
regval &= ~I2S_RX_FIFO_TH_MASK;
regval |= (config->tx_fifo_threshold << I2S_TX_FIFO_TH_SHIFT) & I2S_TX_FIFO_TH_MASK;
regval |= (config->tx_fifo_threshold << I2S_RX_FIFO_TH_SHIFT) & I2S_RX_FIFO_TH_MASK;
putreg32(regval, reg_base + I2S_FIFO_CONFIG_1_OFFSET);
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
/* 32bit to 24bit */
regval &= ~I2S_CR_FIFO_24B_LJ;
/* Exchange L/R channel data */
regval &= ~I2S_CR_FIFO_LR_EXCHG;
/* Each FIFO entry contains both L/R channel data */
regval &= ~I2S_CR_FIFO_LR_MERGE;
/* disable dma */
regval &= ~I2S_DMA_TX_EN;
regval &= ~I2S_DMA_RX_EN;
/* clean fifo */
regval |= I2S_TX_FIFO_CLR;
regval |= I2S_RX_FIFO_CLR;
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET);
/* disable deglitch */
regval &= ~I2S_CR_DEG_EN;
/* disable inverse signal */
regval &= ~I2S_CR_I2S_BCLK_INV;
regval &= ~I2S_CR_I2S_FS_INV;
regval &= ~I2S_CR_I2S_RXD_INV;
regval &= ~I2S_CR_I2S_TXD_INV;
putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET);
/* enable I2S, but disable tx and rx */
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
if (config->role == I2S_ROLE_MASTER) {
regval |= I2S_CR_I2S_M_EN;
} else {
regval |= I2S_CR_I2S_S_EN;
}
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
}
void bflb_i2s_deinit(struct bflb_device_s *dev)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
/* disable I2S */
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
regval &= ~I2S_CR_I2S_S_EN;
regval &= ~I2S_CR_I2S_M_EN;
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
}
void bflb_i2s_link_txdma(struct bflb_device_s *dev, bool enable)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
if (enable) {
regval |= I2S_DMA_TX_EN;
} else {
regval &= ~I2S_DMA_TX_EN;
}
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
}
void bflb_i2s_link_rxdma(struct bflb_device_s *dev, bool enable)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
if (enable) {
regval |= I2S_DMA_RX_EN;
} else {
regval &= ~I2S_DMA_RX_EN;
}
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
}
void bflb_i2s_txint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t regval;
uint32_t reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
if (mask) {
regval |= I2S_CR_I2S_TXF_MASK;
} else {
regval &= ~I2S_CR_I2S_TXF_MASK;
}
putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
}
void bflb_i2s_rxint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t regval;
uint32_t reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
if (mask) {
regval |= I2S_CR_I2S_RXF_MASK;
} else {
regval &= ~I2S_CR_I2S_RXF_MASK;
}
putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
}
void bflb_i2s_errint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t regval;
uint32_t reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
if (mask) {
regval |= I2S_CR_I2S_FER_MASK;
} else {
regval &= ~I2S_CR_I2S_FER_MASK;
}
putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
}
uint32_t bflb_i2s_get_intstatus(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t int_status;
uint32_t int_mask;
reg_base = dev->reg_base;
int_status = getreg32(reg_base + I2S_INT_STS_OFFSET) & 0x1f;
int_mask = (getreg32(reg_base + I2S_INT_STS_OFFSET) >> 8) & 0x1f;
return (int_status & ~int_mask);
}
int bflb_i2s_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
{
int ret = 0;
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
switch (cmd) {
case I2S_CMD_CLEAR_TX_FIFO:
/* clear tx fifo */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
regval |= I2S_TX_FIFO_CLR;
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
break;
case I2S_CMD_CLEAR_RX_FIFO:
/* clear rx fifo */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
regval |= I2S_RX_FIFO_CLR;
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
break;
case I2S_CMD_RX_DEGLITCH:
/* set rx deglitch, arg: deglitch cycle count (unit: cycle of I2S kernel clock) */
regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET);
if (arg) {
regval |= I2S_CR_DEG_EN;
regval &= ~I2S_CR_DEG_CNT_MASK;
regval |= (arg << I2S_CR_DEG_CNT_SHIFT) & I2S_CR_DEG_CNT_MASK;
} else {
regval &= ~I2S_CR_DEG_EN;
}
putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET);
break;
case I2S_CMD_DATA_ENABLE:
/* data enable, arg: use @ref I2S_CMD_DATA_ENABLE_TYPE */
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
/* enable tx data signal */
if (arg & I2S_CMD_DATA_ENABLE_TX) {
regval |= I2S_CR_I2S_TXD_EN;
} else {
regval &= ~I2S_CR_I2S_TXD_EN;
}
/* enable rx data signal */
if (arg & I2S_CMD_DATA_ENABLE_RX) {
regval |= I2S_CR_I2S_RXD_EN;
} else {
regval &= ~I2S_CR_I2S_RXD_EN;
}
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
break;
case I2S_CMD_CHANNEL_LR_MERGE:
/* Each FIFO entry contains both L/R channel data ,
can only be enabled if data size is 8 or 16 bits,
arg use true or false */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
if (arg) {
regval |= I2S_CR_FIFO_LR_MERGE;
} else {
regval &= ~I2S_CR_FIFO_LR_MERGE;
}
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
break;
case I2S_CMD_CHANNEL_LR_EXCHG:
/* The position of L/R channel data within each entry is exchanged,
can only be enabled if data size is 8 or 16 bits and I2S_CMD_CHANNEL_LR_MERGE is enabled,
arg use true or false */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
if (arg) {
regval |= I2S_CR_FIFO_LR_EXCHG;
} else {
regval &= ~I2S_CR_FIFO_LR_EXCHG;
}
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
break;
case I2S_CMD_MUTE:
/* Enable mute, arg use true or false */
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
if (arg) {
regval |= I2S_CR_MUTE_MODE;
} else {
regval &= ~I2S_CR_MUTE_MODE;
}
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
break;
case I2S_CMD_BIT_REVERSE:
/* Data endian (bit reverse), arg use true or false, true: MSB goes out first, false: LSB goes out first*/
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
if (arg) {
regval |= I2S_CR_MUTE_MODE;
} else {
regval &= ~I2S_CR_MUTE_MODE;
}
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
break;
default:
ret = -EPERM;
break;
}
return ret;
}
|
