1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
|
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-10-23 yuzrain the first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <drv_hwtimer.h>
#include <board.h>
#include "md_ad16c4t.h"
#include "md_rcu.h"
#ifdef RT_USING_HWTIMER
/* Defien the hardware timer control struct */
struct es32f0_hwtimer_dev
{
rt_hwtimer_t parent;
AD16C4T_TypeDef *hwtimer_periph;
IRQn_Type IRQn;
};
#ifdef BSP_USING_HWTIMER1
static struct es32f0_hwtimer_dev hwtimer1;
void BS16T1_IRQHandler(void)
{
/* if BS16T1 IT */
if (BS16T1->IFM & AD16C4T_RIF_UI_MSK)
{
SET_BIT(BS16T1->ICR, AD16C4T_ICR_UI_MSK);
rt_device_hwtimer_isr(&hwtimer1.parent);
if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
{
CLEAR_BIT(BS16T1->CON1, AD16C4T_CON1_CNTEN_MSK);
}
}
}
#endif
static struct rt_hwtimer_info es32f0_hwtimer_info =
{
48000000, /* maximum count frequency */
1, /* minimum count frequency */
65535, /* counter maximum value */
HWTIMER_CNTMODE_UP
};
static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
{
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
if (1 == state)
{
/* Set frequency */
WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/hwtimer->parent.freq - 1));
/* Enable timer IT */
SET_BIT(hwtimer->hwtimer_periph->IER, AD16C4T_IER_UI_MSK);
NVIC_EnableIRQ(hwtimer->IRQn);
}
else
{
/* Dsiable timer IT */
SET_BIT(hwtimer->hwtimer_periph->IDR, AD16C4T_IER_UI_MSK);
}
}
static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
rt_uint32_t cnt,
rt_hwtimer_mode_t mode)
{
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
WRITE_REG(hwtimer->hwtimer_periph->AR, cnt);
SET_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
return RT_EOK;
}
static void es32f0_hwtimer_stop(rt_hwtimer_t *timer)
{
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
}
static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer)
{
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
uint32_t hwtimer_count = 0;
RT_ASSERT(hwtimer != RT_NULL);
hwtimer_count = READ_REG(hwtimer->hwtimer_periph->COUNT);
return hwtimer_count;
}
static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer,
rt_uint32_t cmd,
void *args)
{
rt_err_t ret = RT_EOK;
rt_uint32_t freq = 0;
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
switch (cmd)
{
case HWTIMER_CTRL_FREQ_SET:
freq = *(rt_uint32_t *)args;
if ((freq < hwtimer->parent.info->minfreq) || (freq > hwtimer->parent.info->maxfreq))
{
ret = RT_EINVAL;
}
/* Set frequency */
WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/freq - 1));
break;
case HWTIMER_CTRL_STOP:
CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
break;
default:
ret = RT_EINVAL;
break;
}
return ret;
}
static struct rt_hwtimer_ops es32f0_hwtimer_ops =
{
es32f0_hwtimer_init,
es32f0_hwtimer_start,
es32f0_hwtimer_stop,
es32f0_hwtimer_count_get,
es32f0_hwtimer_control
};
int rt_hw_hwtimer_init(void)
{
rt_err_t ret = RT_EOK;
#ifdef BSP_USING_HWTIMER1
/*Open clock*/
SET_BIT(RCU->APB1EN, RCU_APB1EN_BS16T1EN_MSK);
hwtimer1.hwtimer_periph = BS16T1;
hwtimer1.IRQn = BS16T1_IRQn;
hwtimer1.parent.info = &es32f0_hwtimer_info;
hwtimer1.parent.ops = &es32f0_hwtimer_ops;
ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1);
#endif
return ret;
}
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
#endif
|
