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/*
* Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd.
*
*/
#ifndef __ES_CONF_INFO_DMA_H__
#define __ES_CONF_INFO_DMA_H__
#include "rtconfig.h"
#ifdef BSP_EUART0_TX_USING_DMA
#endif
#ifdef BSP_CUART2_TX_USING_DMA
#define ES_CONF_CUART2_DMA_TX
#endif
#ifdef BSP_CUART2_RX_USING_DMA
#define ES_CONF_CUART2_DMA_RX
#endif
enum ES_DMA_CHANNELS
{
#ifdef ES_CONF_EUART0_DMA_TX
ES_EUART0_DMATX_CHANNEL,
#endif
#ifdef ES_CONF_EUART0_DMA_RX
ES_EUART0_DMARX_CHANNEL,
#endif
#ifdef ES_CONF_EUART1_DMA_TX
ES_EUART1_DMATX_CHANNEL,
#endif
#ifdef ES_CONF_EUART1_DMA_RX
ES_EUART1_DMARX_CHANNEL,
#endif
#ifdef ES_CONF_CUART0_DMA_TX
ES_CUART0_DMATX_CHANNEL,
#endif
#ifdef ES_CONF_CUART0_DMA_RX
ES_CUART0_DMARX_CHANNEL,
#endif
#ifdef ES_CONF_CUART1_DMA_TX
ES_CUART1_DMATX_CHANNEL,
#endif
#ifdef ES_CONF_CUART1_DMA_RX
ES_CUART1_DMARX_CHANNEL,
#endif
#ifdef ES_CONF_CUART2_DMA_TX
ES_CUART2_DMATX_CHANNEL,
#endif
#ifdef ES_CONF_CUART2_DMA_RX
ES_CUART2_DMARX_CHANNEL,
#endif
#ifdef ES_SPI0_I2S_MODE
ES_SPI0_I2S_DMATX_CHANNEL,
ES_SPI0_I2S_DMARX_CHANNEL,
#endif
#ifdef ES_SPI1_I2S_MODE
ES_SPI1_I2S_DMATX_CHANNEL,
ES_SPI1_I2S_DMARX_CHANNEL,
#endif
ES_DMA_CHANNEL_NUM
};
#define ES_DMA_INVAILD_CHANNEL (ES_DMA_CHANNEL_NUM)
#define ES_DMA_USER_CHANNEL (ES_DMA_CHANNEL_NUM)
#endif /* __ES_CONF_INFO_DMA_H__ */
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