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/***************************************************************************//**
* \file HC32F448.icf
* \version 1.0
*
* \brief Linker file for the IAR compiler.
*
********************************************************************************
* \copyright
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*******************************************************************************/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
// Check that necessary symbols have been passed to linker via command line interface
if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
error "Link location not defined or not supported!";
}
if((!isdefinedsymbol(_HC32F448_256K_)) && (!isdefinedsymbol(_HC32F448_128K_))) {
error "Mcu type or size not defined or not supported!";
}
/*******************************************************************************
* Memory address and size definitions
******************************************************************************/
define symbol ram1_base_address = 0x1FFF8000;
define symbol ram1_end_address = 0x20007FFF;
if(isdefinedsymbol(_LINK_RAM_)) {
define symbol ram_start_reserve = 0x8000;
define symbol rom1_base_address = ram1_base_address;
define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01;
define symbol rom2_base_address = 0x0;
define symbol rom2_end_address = 0x0;
} else {
define symbol ram_start_reserve = 0x0;
define symbol rom1_base_address = 0x0;
define symbol rom2_base_address = 0x03000C00;
define symbol rom2_end_address = 0x03000FFF;
if(isdefinedsymbol(_HC32F448_256K_)) {
define symbol rom1_end_address = 0x0003FFFF;
} else if (isdefinedsymbol(_HC32F448_128K_)) {
define symbol rom1_end_address = 0x0001FFFF;
}
}
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address;
define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x0;
/**** End of ICF editor section. ###ICF###*/
/*******************************************************************************
* Memory definitions
******************************************************************************/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region OTP_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in OTP_region { readonly section .otp_data };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
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