1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
|
/*
* Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-03 CDT first version
*/
#ifndef __TMR_CONFIG_H__
#define __TMR_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_TMRA_1
#ifndef TMRA_1_CONFIG
#define TMRA_1_CONFIG \
{ \
.tmr_handle = CM_TMRA_1, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_1, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_1_OVF, \
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
}, \
.name = "tmra_1" \
}
#endif /* TMRA_1_CONFIG */
#endif /* BSP_USING_TMRA_1 */
#ifdef BSP_USING_TMRA_2
#ifndef TMRA_2_CONFIG
#define TMRA_2_CONFIG \
{ \
.tmr_handle = CM_TMRA_2, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_2, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_2_OVF, \
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
}, \
.name = "tmra_2" \
}
#endif /* TMRA_2_CONFIG */
#endif /* BSP_USING_TMRA_2 */
#ifdef BSP_USING_TMRA_3
#ifndef TMRA_3_CONFIG
#define TMRA_3_CONFIG \
{ \
.tmr_handle = CM_TMRA_3, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_3, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_3_OVF, \
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
}, \
.name = "tmra_3" \
}
#endif /* TMRA_3_CONFIG */
#endif /* BSP_USING_TMRA_3 */
#ifdef BSP_USING_TMRA_4
#ifndef TMRA_4_CONFIG
#define TMRA_4_CONFIG \
{ \
.tmr_handle = CM_TMRA_4, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_4, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_4_OVF, \
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
}, \
.name = "tmra_4" \
}
#endif /* TMRA_4_CONFIG */
#endif /* BSP_USING_TMRA_4 */
#ifdef BSP_USING_TMRA_5
#ifndef TMRA_5_CONFIG
#define TMRA_5_CONFIG \
{ \
.tmr_handle = CM_TMRA_5, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_5, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_5_OVF, \
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
}, \
.name = "tmra_5" \
}
#endif /* TMRA_5_CONFIG */
#endif /* BSP_USING_TMRA_5 */
#ifdef BSP_USING_TMRA_6
#ifndef TMRA_6_CONFIG
#define TMRA_6_CONFIG \
{ \
.tmr_handle = CM_TMRA_6, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_6, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_6_OVF, \
.enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \
}, \
.name = "tmra_6" \
}
#endif /* TMRA_6_CONFIG */
#endif /* BSP_USING_TMRA_6 */
#ifdef BSP_USING_TMRA_7
#ifndef TMRA_7_CONFIG
#define TMRA_7_CONFIG \
{ \
.tmr_handle = CM_TMRA_7, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_7, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_7_OVF, \
.enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \
}, \
.name = "tmra_7" \
}
#endif /* TMRA_7_CONFIG */
#endif /* BSP_USING_TMRA_7 */
#ifdef BSP_USING_TMRA_8
#ifndef TMRA_8_CONFIG
#define TMRA_8_CONFIG \
{ \
.tmr_handle = CM_TMRA_8, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_8, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_8_OVF, \
.enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \
}, \
.name = "tmra_8" \
}
#endif /* TMRA_8_CONFIG */
#endif /* BSP_USING_TMRA_8 */
#endif /* __TMR_CONFIG_H__ */
|
