1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
|
/*
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-06-09 CDT first version
*/
#include "board.h"
#include "drv_config.h"
#ifdef RT_USING_PULSE_ENCODER
#include "drv_irq.h"
// #define DRV_DEBUG
#define LOG_TAG "drv_pulse_encoder"
#include <drv_log.h>
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
#if !defined(BSP_USING_PULSE_ENCODER_TMRA_1) && !defined(BSP_USING_PULSE_ENCODER_TMRA_2) && !defined(BSP_USING_PULSE_ENCODER_TMRA_3) && \
!defined(BSP_USING_PULSE_ENCODER_TMRA_4) && !defined(BSP_USING_PULSE_ENCODER_TMRA_5) && !defined(BSP_USING_PULSE_ENCODER_TMRA_6) && \
!defined(BSP_USING_PULSE_ENCODER_TMRA_7) && !defined(BSP_USING_PULSE_ENCODER_TMRA_8) && !defined(BSP_USING_PULSE_ENCODER_TMRA_9) && \
!defined(BSP_USING_PULSE_ENCODER_TMRA_10) && !defined(BSP_USING_PULSE_ENCODER_TMRA_11) && !defined(BSP_USING_PULSE_ENCODER_TMRA_12)
#error "Please define at least one BSP_USING_PULSE_ENCODERx"
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
enum
{
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
PULSE_ENCODER_TMRA_1_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
PULSE_ENCODER_TMRA_2_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
PULSE_ENCODER_TMRA_3_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
PULSE_ENCODER_TMRA_4_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
PULSE_ENCODER_TMRA_5_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
PULSE_ENCODER_TMRA_6_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_7
PULSE_ENCODER_TMRA_7_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_8
PULSE_ENCODER_TMRA_8_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_9
PULSE_ENCODER_TMRA_9_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_10
PULSE_ENCODER_TMRA_10_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_11
PULSE_ENCODER_TMRA_11_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_12
PULSE_ENCODER_TMRA_12_INDEX,
#endif
};
struct hc32_pulse_encoder_tmra_device
{
struct rt_pulse_encoder_device pulse_encoder;
CM_TMRA_TypeDef *tmr_handler;
uint32_t u32Fcg2Periph;
struct
{
uint16_t u16CountUpCond;
uint16_t u16CountDownCond;
} hw_count;
struct
{
en_int_src_t enIntSrc_Ovf;
IRQn_Type enIRQn_Ovf;
uint8_t u8Int_Prio_Ovf;
func_ptr_t Irq_Ovf_Callback;
en_int_src_t enIntSrc_Udf;
IRQn_Type enIRQn_Udf;
uint8_t u8Int_Prio_Udf;
func_ptr_t Irq_Udf_Callback;
} isr;
rt_uint32_t u32PeriodValue;
rt_int32_t Over_Under_Flowcount;
char *name;
};
static struct hc32_pulse_encoder_tmra_device hc32_pulse_encoder_tmra_obj[] =
{
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
PULSE_ENCODER_TMRA_1_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
PULSE_ENCODER_TMRA_2_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
PULSE_ENCODER_TMRA_3_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
PULSE_ENCODER_TMRA_4_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
PULSE_ENCODER_TMRA_5_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
PULSE_ENCODER_TMRA_6_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_7
PULSE_ENCODER_TMRA_7_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_8
PULSE_ENCODER_TMRA_8_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_9
PULSE_ENCODER_TMRA_9_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_10
PULSE_ENCODER_TMRA_10_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_11
PULSE_ENCODER_TMRA_11_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_12
PULSE_ENCODER_TMRA_12_CONFIG,
#endif
};
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
static void TMRA_1_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].Over_Under_Flowcount++;
}
static void TMRA_1_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
static void TMRA_2_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].Over_Under_Flowcount++;
}
static void TMRA_2_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
static void TMRA_3_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].Over_Under_Flowcount++;
}
static void TMRA_3_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
static void TMRA_4_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].Over_Under_Flowcount++;
}
static void TMRA_4_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
static void TMRA_5_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].Over_Under_Flowcount++;
}
static void TMRA_5_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
static void TMRA_6_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].Over_Under_Flowcount++;
}
static void TMRA_6_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_7
static void TMRA_7_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].Over_Under_Flowcount++;
}
static void TMRA_7_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_8
static void TMRA_8_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].Over_Under_Flowcount++;
}
static void TMRA_8_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_9
static void TMRA_9_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].Over_Under_Flowcount++;
}
static void TMRA_9_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_10
static void TMRA_10_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].Over_Under_Flowcount++;
}
static void TMRA_10_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_11
static void TMRA_11_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].Over_Under_Flowcount++;
}
static void TMRA_11_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_12
static void TMRA_12_Ovf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].tmr_handler, TMRA_FLAG_OVF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].Over_Under_Flowcount++;
}
static void TMRA_12_Udf_callback(void)
{
TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].tmr_handler, TMRA_FLAG_UDF);
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].Over_Under_Flowcount--;
}
#endif
/**
* @brief This function gets pulse_encoder_tima irq handle.
* @param None
* @retval None
*/
static void hc32_get_pulse_encoder_tmra_callback(void)
{
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].isr.Irq_Ovf_Callback = TMRA_1_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].isr.Irq_Udf_Callback = TMRA_1_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].isr.Irq_Ovf_Callback = TMRA_2_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].isr.Irq_Udf_Callback = TMRA_2_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].isr.Irq_Ovf_Callback = TMRA_3_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].isr.Irq_Udf_Callback = TMRA_3_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].isr.Irq_Ovf_Callback = TMRA_4_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].isr.Irq_Udf_Callback = TMRA_4_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].isr.Irq_Ovf_Callback = TMRA_5_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].isr.Irq_Udf_Callback = TMRA_5_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].isr.Irq_Ovf_Callback = TMRA_6_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].isr.Irq_Udf_Callback = TMRA_6_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_7
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].isr.Irq_Ovf_Callback = TMRA_7_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].isr.Irq_Udf_Callback = TMRA_7_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_8
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].isr.Irq_Ovf_Callback = TMRA_8_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].isr.Irq_Udf_Callback = TMRA_8_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_9
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].isr.Irq_Ovf_Callback = TMRA_9_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].isr.Irq_Udf_Callback = TMRA_9_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_10
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].isr.Irq_Ovf_Callback = TMRA_10_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].isr.Irq_Udf_Callback = TMRA_10_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_11
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].isr.Irq_Ovf_Callback = TMRA_11_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].isr.Irq_Udf_Callback = TMRA_11_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMRA_12
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].isr.Irq_Ovf_Callback = TMRA_12_Ovf_callback;
hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].isr.Irq_Udf_Callback = TMRA_12_Udf_callback;
#endif
}
rt_err_t _tmra_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
{
stc_tmra_init_t stcTmraInit;
struct hc32_irq_config irq_config;
struct hc32_pulse_encoder_tmra_device *hc32_device;
hc32_device = (struct hc32_pulse_encoder_tmra_device *)pulse_encoder;
/* Enable TimerA peripheral clock. */
FCG_Fcg2PeriphClockCmd(hc32_device->u32Fcg2Periph, ENABLE);
(void)TMRA_StructInit(&stcTmraInit);
/* Initializes position-count unit. */
stcTmraInit.u8CountSrc = TMRA_CNT_SRC_HW;
stcTmraInit.hw_count.u16CountUpCond = hc32_device->hw_count.u16CountUpCond;
stcTmraInit.hw_count.u16CountDownCond = hc32_device->hw_count.u16CountDownCond;
stcTmraInit.u32PeriodValue = hc32_device->u32PeriodValue;
(void)TMRA_Init(hc32_device->tmr_handler, &stcTmraInit);
/* OVF interrupt configuration */
irq_config.irq_num = hc32_device->isr.enIRQn_Ovf;
irq_config.int_src = hc32_device->isr.enIntSrc_Ovf;
irq_config.irq_prio = hc32_device->isr.u8Int_Prio_Ovf;
/* register interrupt */
hc32_install_irq_handler(&irq_config,
hc32_device->isr.Irq_Ovf_Callback,
RT_TRUE);
/* UDF interrupt configuration */
irq_config.irq_num = hc32_device->isr.enIRQn_Udf;
irq_config.int_src = hc32_device->isr.enIntSrc_Udf;
irq_config.irq_prio = hc32_device->isr.u8Int_Prio_Udf;
/* register interrupt */
hc32_install_irq_handler(&irq_config,
hc32_device->isr.Irq_Udf_Callback,
RT_TRUE);
/* Enable the specified interrupts of TimerA. */
TMRA_IntCmd(hc32_device->tmr_handler, TMRA_INT_OVF | TMRA_INT_UDF, ENABLE);
LOG_D("_tmra_pulse_encoder_init");
return RT_EOK;
}
rt_err_t _tmra_pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
{
rt_uint8_t startFlag = RT_FALSE;
struct hc32_pulse_encoder_tmra_device *hc32_device;
hc32_device = (struct hc32_pulse_encoder_tmra_device *)pulse_encoder;
hc32_device->Over_Under_Flowcount = 0;
if (READ_REG8_BIT(hc32_device->tmr_handler->BCSTRL, TMRA_BCSTRL_START) == TMRA_BCSTRL_START)
{
startFlag = RT_TRUE;
}
TMRA_Stop(hc32_device->tmr_handler);
TMRA_SetCountValue(hc32_device->tmr_handler, 0);
if (RT_TRUE == startFlag)
{
TMRA_Start(hc32_device->tmr_handler);
}
return RT_EOK;
}
rt_int32_t _tmra_pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
{
struct hc32_pulse_encoder_tmra_device *hc32_device;
hc32_device = (struct hc32_pulse_encoder_tmra_device *)pulse_encoder;
return (rt_int32_t)((rt_int16_t)TMRA_GetCountValue(hc32_device->tmr_handler) + (hc32_device->Over_Under_Flowcount * (hc32_device->u32PeriodValue + 1)));
}
rt_err_t _tmra_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
{
rt_err_t result;
struct hc32_pulse_encoder_tmra_device *hc32_device;
hc32_device = (struct hc32_pulse_encoder_tmra_device *)pulse_encoder;
result = RT_EOK;
switch (cmd)
{
case PULSE_ENCODER_CMD_ENABLE:
TMRA_Start(hc32_device->tmr_handler);
LOG_D("TMRA_Start");
break;
case PULSE_ENCODER_CMD_DISABLE:
TMRA_Stop(hc32_device->tmr_handler);
LOG_D("TMRA_Stop");
break;
default:
result = -RT_ENOSYS;
break;
}
return result;
}
static const struct rt_pulse_encoder_ops _tmra_ops =
{
.init = _tmra_pulse_encoder_init,
.get_count = _tmra_pulse_encoder_get_count,
.clear_count = _tmra_pulse_encoder_clear_count,
.control = _tmra_pulse_encoder_control,
};
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
#if !defined(BSP_USING_PULSE_ENCODER_TMR6_1) && !defined(BSP_USING_PULSE_ENCODER_TMR6_2) && !defined(BSP_USING_PULSE_ENCODER_TMR6_3) && \
!defined(BSP_USING_PULSE_ENCODER_TMR6_4) && !defined(BSP_USING_PULSE_ENCODER_TMR6_5) && !defined(BSP_USING_PULSE_ENCODER_TMR6_6) && \
!defined(BSP_USING_PULSE_ENCODER_TMR6_7) && !defined(BSP_USING_PULSE_ENCODER_TMR6_8)
#error "Please define at least one BSP_USING_PULSE_ENCODERx"
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
enum
{
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
PULSE_ENCODER_TMR6_1_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
PULSE_ENCODER_TMR6_2_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
PULSE_ENCODER_TMR6_3_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_4
PULSE_ENCODER_TMR6_4_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_5
PULSE_ENCODER_TMR6_5_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_6
PULSE_ENCODER_TMR6_6_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_7
PULSE_ENCODER_TMR6_7_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_8
PULSE_ENCODER_TMR6_8_INDEX,
#endif
};
struct hc32_pulse_encoder_tmr6_device
{
struct rt_pulse_encoder_device pulse_encoder;
CM_TMR6_TypeDef *tmr_handler;
uint32_t u32Fcg2Periph;
struct
{
uint32_t u32CountUpCond;
uint32_t u32CountDownCond;
} hw_count;
struct
{
en_int_src_t enIntSrc_Ovf;
IRQn_Type enIRQn_Ovf;
uint8_t u8Int_Prio_Ovf;
func_ptr_t Irq_Ovf_Callback;
en_int_src_t enIntSrc_Udf;
IRQn_Type enIRQn_Udf;
uint8_t u8Int_Prio_Udf;
func_ptr_t Irq_Udf_Callback;
} isr;
rt_uint32_t u32PeriodValue;
rt_int32_t Over_Under_Flowcount;
char *name;
};
static struct hc32_pulse_encoder_tmr6_device hc32_pulse_encoder_tmr6_obj[] =
{
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
PULSE_ENCODER_TMR6_1_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
PULSE_ENCODER_TMR6_2_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
PULSE_ENCODER_TMR6_3_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_4
PULSE_ENCODER_TMR6_4_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_5
PULSE_ENCODER_TMR6_5_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_6
PULSE_ENCODER_TMR6_6_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_7
PULSE_ENCODER_TMR6_7_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_8
PULSE_ENCODER_TMR6_8_CONFIG,
#endif
};
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
void TMR6_1_Ovf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].tmr_handler, TMR6_FLAG_OVF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].Over_Under_Flowcount++;
}
void TMR6_1_Udf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].tmr_handler, TMR6_FLAG_UDF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
void TMR6_2_Ovf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].tmr_handler, TMR6_FLAG_OVF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].Over_Under_Flowcount++;
}
void TMR6_2_Udf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].tmr_handler, TMR6_FLAG_UDF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
void TMR6_3_Ovf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].tmr_handler, TMR6_FLAG_OVF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].Over_Under_Flowcount++;
}
void TMR6_3_Udf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].tmr_handler, TMR6_FLAG_UDF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_4
void TMR6_4_Ovf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].tmr_handler, TMR6_FLAG_OVF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].Over_Under_Flowcount++;
}
void TMR6_4_Udf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].tmr_handler, TMR6_FLAG_UDF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_5
void TMR6_5_Ovf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].tmr_handler, TMR6_FLAG_OVF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].Over_Under_Flowcount++;
}
void TMR6_5_Udf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].tmr_handler, TMR6_FLAG_UDF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_6
void TMR6_6_Ovf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].tmr_handler, TMR6_FLAG_OVF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].Over_Under_Flowcount++;
}
void TMR6_6_Udf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].tmr_handler, TMR6_FLAG_UDF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_7
void TMR6_7_Ovf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].tmr_handler, TMR6_FLAG_OVF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].Over_Under_Flowcount++;
}
void TMR6_7_Udf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].tmr_handler, TMR6_FLAG_UDF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].Over_Under_Flowcount--;
}
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_8
void TMR6_8_Ovf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].tmr_handler, TMR6_FLAG_OVF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].Over_Under_Flowcount++;
}
void TMR6_8_Udf_callback(void)
{
TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].tmr_handler, TMR6_FLAG_UDF);
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].Over_Under_Flowcount--;
}
#endif
/**
* @brief This function gets pulse_encoder_tim6 irq handle.
* @param None
* @retval None
*/
static void hc32_get_pulse_encoder_tmr6_callback(void)
{
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].isr.Irq_Ovf_Callback = TMR6_1_Ovf_callback;
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].isr.Irq_Udf_Callback = TMR6_1_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].isr.Irq_Ovf_Callback = TMR6_2_Ovf_callback;
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].isr.Irq_Udf_Callback = TMR6_2_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].isr.Irq_Ovf_Callback = TMR6_3_Ovf_callback;
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].isr.Irq_Udf_Callback = TMR6_3_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_4
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].isr.Irq_Ovf_Callback = TMR6_4_Ovf_callback;
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].isr.Irq_Udf_Callback = TMR6_4_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_5
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].isr.Irq_Ovf_Callback = TMR6_5_Ovf_callback;
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].isr.Irq_Udf_Callback = TMR6_5_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_6
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].isr.Irq_Ovf_Callback = TMR6_6_Ovf_callback;
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].isr.Irq_Udf_Callback = TMR6_6_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_7
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].isr.Irq_Ovf_Callback = TMR6_7_Ovf_callback;
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].isr.Irq_Udf_Callback = TMR6_7_Udf_callback;
#endif
#ifdef BSP_USING_PULSE_ENCODER_TMR6_8
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].isr.Irq_Ovf_Callback = TMR6_8_Ovf_callback;
hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].isr.Irq_Udf_Callback = TMR6_8_Udf_callback;
#endif
}
rt_err_t _tmr6_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
{
stc_tmr6_init_t stcTmr6Init;
struct hc32_irq_config irq_config;
struct hc32_pulse_encoder_tmr6_device *hc32_device;
hc32_device = (struct hc32_pulse_encoder_tmr6_device *)pulse_encoder;
/* Enable Timer6 peripheral clock. */
FCG_Fcg2PeriphClockCmd(hc32_device->u32Fcg2Periph, ENABLE);
(void)TMR6_StructInit(&stcTmr6Init);
/* Initializes position-count unit. */
stcTmr6Init.u8CountSrc = TMR6_CNT_SRC_HW;
stcTmr6Init.hw_count.u32CountUpCond = hc32_device->hw_count.u32CountUpCond;
stcTmr6Init.hw_count.u32CountDownCond = hc32_device->hw_count.u32CountDownCond;
stcTmr6Init.u32PeriodValue = hc32_device->u32PeriodValue;
(void)TMR6_Init(hc32_device->tmr_handler, &stcTmr6Init);
/* OVF interrupt configuration */
irq_config.irq_num = hc32_device->isr.enIRQn_Ovf;
irq_config.int_src = hc32_device->isr.enIntSrc_Ovf;
irq_config.irq_prio = hc32_device->isr.u8Int_Prio_Ovf;
/* register interrupt */
hc32_install_irq_handler(&irq_config,
hc32_device->isr.Irq_Ovf_Callback,
RT_TRUE);
/* UDF interrupt configuration */
irq_config.irq_num = hc32_device->isr.enIRQn_Udf;
irq_config.int_src = hc32_device->isr.enIntSrc_Udf;
irq_config.irq_prio = hc32_device->isr.u8Int_Prio_Udf;
/* register interrupt */
hc32_install_irq_handler(&irq_config,
hc32_device->isr.Irq_Udf_Callback,
RT_TRUE);
/* Enable the specified interrupts of Timer6. */
TMR6_IntCmd(hc32_device->tmr_handler, TMR6_INT_OVF | TMR6_INT_UDF, ENABLE);
LOG_D("_tmr6_pulse_encoder_init");
return RT_EOK;
}
rt_err_t _tmr6_pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
{
rt_uint8_t startFlag = RT_FALSE;
struct hc32_pulse_encoder_tmr6_device *hc32_device;
hc32_device = (struct hc32_pulse_encoder_tmr6_device *)pulse_encoder;
hc32_device->Over_Under_Flowcount = 0;
if (READ_REG32_BIT(hc32_device->tmr_handler->GCONR, TMR6_GCONR_START) == TMR6_GCONR_START)
{
startFlag = RT_TRUE;
}
TMR6_Stop(hc32_device->tmr_handler);
TMR6_SetCountValue(hc32_device->tmr_handler, 0);
if (RT_TRUE == startFlag)
{
TMR6_Start(hc32_device->tmr_handler);
}
return RT_EOK;
}
rt_int32_t _tmr6_pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
{
struct hc32_pulse_encoder_tmr6_device *hc32_device;
hc32_device = (struct hc32_pulse_encoder_tmr6_device *)pulse_encoder;
return (rt_int32_t)((rt_int16_t)TMR6_GetCountValue(hc32_device->tmr_handler) + (hc32_device->Over_Under_Flowcount * (hc32_device->u32PeriodValue + 1)));
}
rt_err_t _tmr6_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
{
rt_err_t result;
struct hc32_pulse_encoder_tmr6_device *hc32_device;
hc32_device = (struct hc32_pulse_encoder_tmr6_device *)pulse_encoder;
result = RT_EOK;
switch (cmd)
{
case PULSE_ENCODER_CMD_ENABLE:
TMR6_Start(hc32_device->tmr_handler);
LOG_D("TMR6_Start");
break;
case PULSE_ENCODER_CMD_DISABLE:
TMR6_Stop(hc32_device->tmr_handler);
LOG_D("TMR6_Stop");
break;
default:
result = -RT_ENOSYS;
break;
}
return result;
}
static const struct rt_pulse_encoder_ops _tmr6_ops =
{
.init = _tmr6_pulse_encoder_init,
.get_count = _tmr6_pulse_encoder_get_count,
.clear_count = _tmr6_pulse_encoder_clear_count,
.control = _tmr6_pulse_encoder_control,
};
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
static int rt_hw_pulse_encoder_init(void)
{
int result;
result = RT_EOK;
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
extern rt_err_t rt_hw_board_pulse_encoder_tmra_init(void);
result = rt_hw_board_pulse_encoder_tmra_init();
hc32_get_pulse_encoder_tmra_callback();
for (int i = 0; i < sizeof(hc32_pulse_encoder_tmra_obj) / sizeof(hc32_pulse_encoder_tmra_obj[0]); i++)
{
hc32_pulse_encoder_tmra_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
hc32_pulse_encoder_tmra_obj[i].pulse_encoder.ops = &_tmra_ops;
if (rt_device_pulse_encoder_register(&hc32_pulse_encoder_tmra_obj[i].pulse_encoder, hc32_pulse_encoder_tmra_obj[i].name, RT_NULL) != RT_EOK)
{
LOG_E("%s register failed", hc32_pulse_encoder_tmra_obj[i].name);
result = -RT_ERROR;
}
}
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
extern rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void);
result = rt_hw_board_pulse_encoder_tmr6_init();
hc32_get_pulse_encoder_tmr6_callback();
for (int i = 0; i < sizeof(hc32_pulse_encoder_tmr6_obj) / sizeof(hc32_pulse_encoder_tmr6_obj[0]); i++)
{
hc32_pulse_encoder_tmr6_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
hc32_pulse_encoder_tmr6_obj[i].pulse_encoder.ops = &_tmr6_ops;
if (rt_device_pulse_encoder_register(&hc32_pulse_encoder_tmr6_obj[i].pulse_encoder, hc32_pulse_encoder_tmr6_obj[i].name, RT_NULL) != RT_EOK)
{
LOG_E("%s register failed", hc32_pulse_encoder_tmr6_obj[i].name);
result = -RT_ERROR;
}
}
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
return result;
}
INIT_BOARD_EXPORT(rt_hw_pulse_encoder_init);
#endif /* RT_USING_PULSE_ENCODER */
|
