blob: a9924231dcea6e92982111e7c31c4558ad2774a1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
|
# Copyright 2021 hpmicro
# SPDX-License-Identifier: BSD-3-Clause
#
set _CHIP hpm6280
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
targets $_TARGET0
source [file join [file dirname [info script]] hpm_common.cfg]
source [file join [file dirname [info script]] hpm_common_csr.cfg]
proc dmi_write {reg value} {
$::_TARGET0 riscv dmi_write ${reg} ${value}
}
proc dmi_read {reg} {
set v [$::_TARGET0 riscv dmi_read ${reg}]
return ${v}
}
proc dmi_write_memory {addr value} {
dmi_write 0x39 ${addr}
dmi_write 0x3C ${value}
}
proc dmi_read_memory {addr} {
set sbcs [expr { 0x100000 | [dmi_read 0x38] }]
dmi_write 0x38 ${sbcs}
dmi_write 0x39 ${addr}
set value [dmi_read 0x3C]
return ${value}
}
proc release_core1 {} {
# set start point for core1
dmi_write_memory 0xF4002C08 0x20012588
# set boot flag for core1
dmi_write_memory 0xF4002C0C 0xC1BEF1A9
# release core1
dmi_write_memory 0xF4002C00 0x1000
}
set _TARGET1 $_CHIP.cpu1
target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
$_TARGET1 configure -event examine-start {
release_core1
}
$_TARGET1 configure -event reset-deassert-pre {
$::_TARGET0 arp_poll
release_core1
}
|
