blob: 7fb3a7a74c30f73af0dfb9d6838de5c30d9c67fd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
|
# Copyright (c) 2021 HPMicro
# SPDX-License-Identifier: BSD-3-Clause
#
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - option1:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3040000
# - base address: 0x80000000
# - flash size: 0x1000000
flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
proc init_sdram { } {
# configure femc frequency
# 166Mhz pll0_clk1: 333Mhz divide by 2
mww 0xF4001808 0x201
# PA25
mww 0xF40400C8 0xC
# PA26
mww 0xF40400D0 0xC
# PA27
mww 0xF40400D8 0xC
# PA28
mww 0xF40400E0 0xC
# PA29
mww 0xF40400E8 0xC
# PA30
mww 0xF40400F0 0xC
# PA31
mww 0xF40400F8 0xC
# PB00
mww 0xF4040100 0xC
# PB01
mww 0xF4040108 0xC
# PB02
mww 0xF4040110 0xC
# PB03
mww 0xF4040118 0xC
# PB04
mww 0xF4040120 0xC
# PB05
mww 0xF4040128 0xC
# PB06
mww 0xF4040130 0xC
# PB07
mww 0xF4040138 0xC
# PB08
mww 0xF4040140 0xC
# PB09
mww 0xF4040148 0xC
# PB10
mww 0xF4040150 0xC
# PB11
mww 0xF4040158 0xC
# PB12
mww 0xF4040160 0xC
# PB13
mww 0xF4040168 0xC
# PB14
mww 0xF4040170 0xC
# PB15
mww 0xF4040178 0xC
# PB16
mww 0xF4040180 0xC
# PB17
mww 0xF4040188 0xC
# PB18
mww 0xF4040190 0xC
# PB19
mww 0xF4040198 0xC
# PB20
mww 0xF40401A0 0xC
# PB21
mww 0xF40401A8 0xC
# PB22
mww 0xF40401B0 0xC
# PB23
mww 0xF40401B8 0xC
# PB24
mww 0xF40401C0 0xC
# PB25
mww 0xF40401C8 0xC
# PB26
mww 0xF40401D0 0xC
# PB27
mww 0xF40401D8 0xC
# PB28
mww 0xF40401E0 0xC
# PB29
mww 0xF40401E8 0xC
# PB30
mww 0xF40401F0 0xC
# PB31
mww 0xF40401F8 0xC
# femc configuration
mww 0xF3050000 0x1
sleep 10
mww 0xF3050000 0x2
mww 0xF3050008 0x30524
mww 0xF305000C 0x6030524
mww 0xF3050000 0x10000004
# 32MB
mww 0xF3050010 0x4000001b
mww 0xF3050014 0
# 16-bit
mww 0xF3050040 0xf31
# 166Mhz configuration
mww 0xF3050044 0x884e33
mww 0xF3050048 0x1020d0d
mww 0xF3050048 0x1020d0d
mww 0xF305004C 0x2020300
# config delay cell
mww 0xF3050150 0x2000
mww 0xF3050094 0
mww 0xF3050098 0
# precharge all
mww 0xF3050090 0x40000000
mww 0xF305009C 0xA55A000F
sleep 500
mww 0xF305003C 0x3
# auto refresh
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
# set mode
mww 0xF30500A0 0x33
mww 0xF305009C 0xA55A000A
sleep 500
mww 0xF305003C 0x3
mww 0xF305004C 0x2020301
echo "SDRAM has been initialized"
}
$_TARGET0 configure -event reset-init {
init_clock
init_sdram
}
$_TARGET0 configure -event gdb-attach {
reset halt
}
|
