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# Copyright (c) 2021 HPMicro
# SPDX-License-Identifier: BSD-3-Clause
#
# openocd flash driver argument:
# - ARG7:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - ARG8:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3040000
# - base address: 0x80000000
# - flash size: 0x1000000
# - flash option0: 0x7
flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
proc init_sdram { } {
# configure femc frequency
# 133Mhz pll1_clk0: 266Mhz divide by 2
#mww 0xF4001820 0x201
# 166Mhz pll2_clk0: 333Mhz divide by 2
mww 0xF4001820 0x401
# PD13
mww 0xF4040368 0xC
# PD12
mww 0xF4040360 0xC
# PD10
mww 0xF4040350 0xC
# PD09
mww 0xF4040348 0xC
# PD08
mww 0xF4040340 0xC
# PD07
mww 0xF4040338 0xC
# PD06
mww 0xF4040330 0xC
# PD05
mww 0xF4040328 0xC
# PD04
mww 0xF4040320 0xC
# PD03
mww 0xF4040318 0xC
# PD02
mww 0xF4040310 0xC
# PD01
mww 0xF4040308 0xC
# PD00
mww 0xF4040300 0xC
# PC29
mww 0xF40402E8 0xC
# PC28
mww 0xF40402E0 0xC
# PC27
mww 0xF40402D8 0xC
# PC22
mww 0xF40402B0 0xC
# PC21
mww 0xF40402A8 0xC
# PC17
mww 0xF4040288 0xC
# PC15
mww 0xF4040278 0xC
# PC12
mww 0xF4040260 0xC
# PC11
mww 0xF4040258 0xC
# PC10
mww 0xF4040250 0xC
# PC09
mww 0xF4040248 0xC
# PC08
mww 0xF4040240 0xC
# PC07
mww 0xF4040238 0xC
# PC06
mww 0xF4040230 0xC
# PC05
mww 0xF4040228 0xC
# PC04
mww 0xF4040220 0xC
# PC14
mww 0xF4040270 0xC
# PC13
mww 0xF4040268 0xC
# PC16
# mww 0xF4040280 0x1000C
# PC26
mww 0xF40402D0 0xC
# PC25
mww 0xF40402C8 0xC
# PC19
mww 0xF4040298 0xC
# PC18
mww 0xF4040290 0xC
# PC23
mww 0xF40402B8 0xC
# PC24
mww 0xF40402C0 0xC
# PC30
mww 0xF40402F0 0xC
# PC31
mww 0xF40402F8 0xC
# PC02
mww 0xF4040210 0xC
# PC03
mww 0xF4040218 0xC
# femc configuration
mww 0xF3050000 0x1
sleep 10
mww 0xF3050000 0x2
mww 0xF3050008 0x30524
mww 0xF305000C 0x6030524
mww 0xF3050000 0x10000000
# 16MB
mww 0xF3050010 0x40000019
mww 0xF3050014 0
# 16-bit
mww 0xF3050040 0xf31
# 133Mhz configuration
#mww 0xF3050044 0x884e22
# 166Mhz configuration
mww 0xF3050044 0x884e33
mww 0xF3050048 0x1020d0d
mww 0xF3050048 0x1020d0d
mww 0xF305004C 0x2020300
# config delay cell
mww 0xF3050150 0x3b
mww 0xF3050150 0x203b
mww 0xF3050094 0
mww 0xF3050098 0
# precharge all
mww 0xF3050090 0x40000000
mww 0xF305009C 0xA55A000F
sleep 500
mww 0xF305003C 0x3
# auto refresh
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
# set mode
mww 0xF30500A0 0x33
mww 0xF305009C 0xA55A000A
sleep 500
mww 0xF305003C 0x3
mww 0xF305004C 0x2020301
echo "SDRAM has been initialized"
}
$_TARGET0 configure -event reset-init {
init_clock
init_sdram
}
$_TARGET0 configure -event gdb-attach {
reset halt
}
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