1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
|
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version
* 2015-07-09 chinesebear modified for loongson 1c
*/
#include <rthw.h>
#include <rtthread.h>
#include "uart.h"
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
struct rt_uart_ls1c
{
struct rt_device parent;
rt_uint32_t hw_base;
rt_uint32_t irq;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
static void rt_uart_irqhandler(int irqno, void *param)
{
rt_ubase_t level;
rt_uint8_t isr;
struct rt_uart_ls1c *uart = &uart_device;
/* read interrupt status and clear it */
isr = UART_IIR(uart->hw_base);
isr = (isr >> 1) & 0x3;
/* receive data available */
if (isr & 0x02)
{
/* Receive Data Available */
while (UART_LSR(uart->hw_base) & UARTLSR_DR)
{
uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
level = rt_hw_interrupt_disable();
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
}
/* invoke callback */
if (uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
return;
}
static rt_err_t rt_uart_init(rt_device_t dev)
{
rt_uint32_t baud_div;
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
//#if 0
/* init UART Hardware */
UART_IER(uart->hw_base) = 0; /* clear interrupt */
UART_FCR(uart->hw_base) = 0xc3; /* reset UART Rx/Tx */
/* enable UART clock */
/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
UART_LCR(uart->hw_base) = 0x80;
/* set baudrate */
baud_div = DEV_CLK / 16 / UART_BAUDRATE /2;
UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
UART_LSB(uart->hw_base) = baud_div & 0xff;
UART_LCR(uart->hw_base) = 0x03;
/* Enable UART unit, enable and clear FIFO */
//UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
/* enable RX interrupt */
UART_IER(uart->hw_base) = UARTIER_IRXE|UARTIER_ILE;
//#endif
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
UART_IER(uart->hw_base) |= UARTIER_IRXE;
/* install interrupt */
rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
rt_hw_interrupt_umask(uart->irq);
}
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
}
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
rt_uint8_t *ptr;
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t *)buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
char *ptr;
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
ptr = (char *)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = '\r';
}
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while (size != 0)
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr++;
size--;
}
}
return (rt_size_t)ptr - (rt_size_t)buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_ls1c *uart;
/* get uart device */
uart = &uart_device;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
#if defined(RT_USING_UART0)
uart->hw_base = UART0_BASE;
uart->irq = LS1C_UART0_IRQ;
#elif defined(RT_USING_UART2)
uart->hw_base = UART2_BASE;
uart->irq = LS1C_UART2_IRQ;
#elif defined(RT_USING_UART3)
uart->hw_base = UART3_BASE;
uart->irq = LS1C_UART3_IRQ;
#endif
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent, "uart2",
RT_DEVICE_FLAG_RDWR |
RT_DEVICE_FLAG_STREAM |
RT_DEVICE_FLAG_INT_RX);
}
#endif /* end of UART */
/*@}*/
|
