blob: 8a5ce3fb541efc583df6e0848b8867d9bd626256 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-04-09 fify the first version
*
* For : Renesas M16C
* Toolchain : IAR's EW for M16C v3.401
*/
;********************************************************************************************************
; RELOCATABLE EXCEPTION VECTOR TABLE
;********************************************************************************************************
MODULE ?vectors
EXTERN rt_hw_timer_handler
EXTERN rt_hw_uart0_receive_handler
EXTERN os_context_switch
PUBLIC RelocatableVectTbl
RSEG INTVEC:NOROOT
RelocatableVectTbl:
ORG 0
DC32 os_context_switch ; Vector 0: BRK
DC32 0 ; Vector 1: Reserved
DC32 0 ; Vector 2: Reserved
DC32 0 ; Vector 3: Reserved
DC32 0 ; Vector 4: INT3
DC32 0 ; Vector 5: Timer B5
DC32 0 ; Vector 6: Timer B4, UART1 Bus Collision Detect
DC32 0 ; Vector 7: Timer B3, UART0 Bus Collision Detect
DC32 0 ; Vector 8: SI/O4, INT5
DC32 0 ; Vector 9: SI/O3, INT4
DC32 0 ; Vector 10: UART2 Bus Collision Detect
DC32 0 ; Vector 11: DMA0
DC32 0 ; Vector 12: DMA1
DC32 0 ; Vector 13: Key Input Interrupt
DC32 0 ; Vector 14: A/D
DC32 0 ; Vector 15: UART2 Transmit, NACK2
DC32 0 ; Vector 16: UART2 Receive, ACK2
DC32 0 ; Vector 17: UART0 Transmit, NACK0
DC32 rt_hw_uart0_receive_handler ; Vector 18: UART0 Receive, ACK0
DC32 0 ; Vector 19: UART1 Transmit, NACK1
DC32 0 ; Vector 20: UART1 Receive, ACK1
DC32 0 ; Vector 21: Timer A0
DC32 0 ; Vector 22: Timer A1
DC32 0 ; Vector 23: Timer A2
DC32 0 ; Vector 24: Timer A3
DC32 0 ; Vector 25: Timer A4
DC32 rt_hw_timer_handler ; Vector 26: Timer B0
DC32 0 ; Vector 27: Timer B1
DC32 0 ; Vector 28: Timer B2
DC32 0 ; Vector 29:
DC32 0 ; Vector 30:
DC32 0 ; Vector 31:
ENDMOD
END
|
