1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
|
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: gpio2_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
// Function to configure IOMUXC for gpio2 module.
void gpio2_iomux_config(void)
{
// Config gpio2.GPIO2_IO11 to pad SD4_DATA3(A20)
// CAN2_NERR_B
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR(0x00000005);
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3(0x020E034C)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA3
// ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO11
HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_V(ALT5));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3(0x020E0734)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE_V(SLOW));
// Config gpio2.GPIO2_IO12 to pad SD4_DATA4(E18)
// PROG
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR(0x00000005);
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4(0x020E0350)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA4
// ALT2 (2) - Select instance: uart2 signal: UART2_RX_DATA
// ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO12
HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_V(ALT5));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4(0x020E0738)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_V(SLOW));
// Config gpio2.GPIO2_IO15 to pad SD4_DATA7(D19)
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR(0x00000005);
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7(0x020E035C)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA7
// ALT2 (2) - Select instance: uart2 signal: UART2_TX_DATA
// ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO15
HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_V(ALT5));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7(0x020E0744)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE_V(SLOW));
// Config gpio2.GPIO2_IO24 to pad EIM_CS1(J23)
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR(0x00000005);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR(0x0000B0B1);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_CS1(0x020E0140)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_CS1
// ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN06
// ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MOSI
// ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO24
// ALT8 (8) - Select instance: epdc signal: EPDC_DATA08
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE_V(ALT5));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_CS1(0x020E0510)
// HYS [16] - Hysteresis Enable Field Reset: DISABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: FAST
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE_V(FAST));
// Config gpio2.GPIO2_IO27 to pad EIM_LBA(K22)
// GPS_INT_B
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR(0x00000005);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR(0x0000B0B1);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_LBA(0x020E01D4)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_LBA
// ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN17
// ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SS1
// ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO27
// ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG26
// ALT8 (8) - Select instance: epdc signal: EPDC_DATA04
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE_V(ALT5));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_LBA(0x020E05A4)
// HYS [16] - Hysteresis Enable Field Reset: DISABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: FAST
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE_V(FAST));
// Config gpio2.GPIO2_IO28 to pad EIM_EB0(K21)
// TOUCH_INT_B
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR(0x00000005);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR(0x0000B0B1);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_EB0(0x020E01C4)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_EB0
// ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA11
// ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA11
// ALT4 (4) - Select instance: ccm signal: CCM_PMIC_READY
// ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO28
// ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG27
// ALT8 (8) - Select instance: epdc signal: EPDC_PWR_COM
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE_V(ALT5));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_EB0(0x020E0594)
// HYS [16] - Hysteresis Enable Field Reset: DISABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: FAST
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE_V(FAST));
// Config gpio2.GPIO2_IO29 to pad EIM_EB1(K23)
// COMPASS_INT
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR(0x00000005);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR(0x0000B0B1);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_EB1(0x020E01C8)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_EB1
// ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA10
// ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA10
// ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO29
// ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG28
// ALT8 (8) - Select instance: epdc signal: EPDC_SDSHR
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE_V(ALT5));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_EB1(0x020E0598)
// HYS [16] - Hysteresis Enable Field Reset: DISABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: FAST
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE_V(FAST));
}
|
