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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: uart4_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
// Function to configure IOMUXC for uart4 module.
void uart4_iomux_config(void)
{
// Config uart4.UART4_RX_DATA to pad KEY_ROW0(V6)
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(0x00000004);
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(0x0001B0B0);
// HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(0x00000003);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0(0x020E0258)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_MOSI
// ALT1 (1) - Select instance: enet signal: ENET_TX_DATA3
// ALT2 (2) - Select instance: audmux signal: AUD5_TXD
// ALT3 (3) - Select instance: kpp signal: KEY_ROW0
// ALT4 (4) - Select instance: uart4 signal: UART4_RX_DATA
// ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO07
// ALT6 (6) - Select instance: dcic2 signal: DCIC2_OUT
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_V(ALT4));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0(0x020E0640)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE_V(SLOW));
// Pad KEY_ROW0 is involved in Daisy Chain.
// Input Select Register:
// IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT(0x020E0914)
// DAISY [1:0] - MUX Mode Select Field Reset: CSI0_DATA12_ALT3
// Selecting Pads Involved in Daisy Chain.
// CSI0_DATA12_ALT3 (0) - Select signal uart4 UART4_TX_DATA as input from pad CSI0_DATA12(ALT3).
// CSI0_DATA13_ALT3 (1) - Select signal uart4 UART4_RX_DATA as input from pad CSI0_DATA13(ALT3).
// KEY_COL0_ALT4 (2) - Select signal uart4 UART4_TX_DATA as input from pad KEY_COL0(ALT4).
// KEY_ROW0_ALT4 (3) - Select signal uart4 UART4_RX_DATA as input from pad KEY_ROW0(ALT4).
HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(
BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY_V(KEY_ROW0_ALT4));
// Config uart4.UART4_TX_DATA to pad KEY_COL0(W5)
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(0x00000004);
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(0x0001B0B0);
// HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(0x00000003);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_KEY_COL0(0x020E0244)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SCLK
// ALT1 (1) - Select instance: enet signal: ENET_RX_DATA3
// ALT2 (2) - Select instance: audmux signal: AUD5_TXC
// ALT3 (3) - Select instance: kpp signal: KEY_COL0
// ALT4 (4) - Select instance: uart4 signal: UART4_TX_DATA
// ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO06
// ALT6 (6) - Select instance: dcic1 signal: DCIC1_OUT
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_V(ALT4));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_KEY_COL0(0x020E062C)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE_V(SLOW));
// Pad KEY_COL0 is involved in Daisy Chain.
// Input Select Register:
// IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT(0x020E0914)
// DAISY [1:0] - MUX Mode Select Field Reset: CSI0_DATA12_ALT3
// Selecting Pads Involved in Daisy Chain.
// CSI0_DATA12_ALT3 (0) - Select signal uart4 UART4_TX_DATA as input from pad CSI0_DATA12(ALT3).
// CSI0_DATA13_ALT3 (1) - Select signal uart4 UART4_RX_DATA as input from pad CSI0_DATA13(ALT3).
// KEY_COL0_ALT4 (2) - Select signal uart4 UART4_TX_DATA as input from pad KEY_COL0(ALT4).
// KEY_ROW0_ALT4 (3) - Select signal uart4 UART4_RX_DATA as input from pad KEY_ROW0(ALT4).
HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(
BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY_V(KEY_ROW0_ALT4));
}
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