1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
|
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fadc_intr.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:28:45
* Description: This files is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
#include "fparameters.h"
#include "fassert.h"
#include "finterrupt.h"
#include "fadc.h"
#include "fadc_hw.h"
#define FADC_DEBUG_TAG "FT_ADC_INTR"
#define FADC_DEBUG(format, ...) FT_DEBUG_PRINT_D(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
#define FADC_INFO(format, ...) FT_DEBUG_PRINT_I(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
#define FADC_WARN(format, ...) FT_DEBUG_PRINT_W(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
#define FADC_ERROR(format, ...) FT_DEBUG_PRINT_E(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
#define FADC_CALL_INTR_EVENT_HANDLDER(instance_p, event) \
if (instance_p->event_handler[event]) \
instance_p->event_handler[event](instance_p->event_param[event])
/**
* @name: FAdcRegisterInterruptHandler
* @msg: register FAdc interrupt handler function
* @param {FAdc} *instance_p, pointer to the adc instance
* @param {FAdcIntrEvtType} event_type, interrupt event type
* @param {FAdcEvtHandler} handler, interrupt event handler
* @param {void} *param, contains a pointer to the driver instance
* @return {*}
*/
void FAdcRegisterInterruptHandler(FAdcCtrl *instance_p, FAdcIntrEventType event_type,
FAdcIntrEventHandler handler, void *param)
{
FASSERT(instance_p);
FASSERT(event_type < FADC_INTR_EVENT_NUM);
instance_p->event_handler[event_type] = handler;
instance_p->event_param[event_type] = param;
}
/**
* @name: FAdcIntrHandler
* @msg: This function is the interrupt handler for the driver.
* It must be connected to an interrupt system by the application such that it
* can be called when an interrupt occurs.
* @param vector Irq num ,Don't need attention .
* @param args contains a pointer to the driver instance
*/
void FAdcIntrHandler(s32 vector, void *args)
{
FASSERT(args != NULL);
FAdcCtrl *pctrl = (FAdcCtrl *)args;
u32 status = 0;
u32 intrmask = 0;
u32 cfg = 0;
u32 channel = 0;
uintptr base_addr = pctrl->config.base_addr;
status = FADC_READ_REG32(base_addr, FADC_INTR_REG_OFFSET);
/* channel convert complete irq mask */
intrmask = FADC_READ_REG32(base_addr, FADC_INTRMASK_REG_OFFSET);
/* adc error interrupt */
if (status & FADC_INTR_REG_ERR)
{
/* clear error interrupt status */
FADC_SETBIT(base_addr, FADC_INTR_REG_OFFSET, FADC_INTR_REG_ERR);
/* write error clear register, adc_errclr_reg=0 */
FADC_WRITE_REG32(base_addr, FADC_ERRCLR_REG_OFFSET, 0);
FADC_CALL_INTR_EVENT_HANDLDER(pctrl, FADC_INTR_EVENT_ERROR);
}
if (status & FADC_INTR_REG_LIMIT_MASK)
{
for (channel = 0; channel < FADC_CHANNEL_NUM; channel++)
{
if (status & FADC_INTR_REG_DLIMIT(channel))
{
/* clear dlimit interrupt status */
FADC_SETBIT(base_addr, FADC_INTR_REG_OFFSET, FADC_INTR_REG_DLIMIT(channel));
FADC_CALL_INTR_EVENT_HANDLDER(pctrl, FADC_INTR_EVENT_DLIMIT);
}
if (status & FADC_INTR_REG_ULIMIT(channel))
{
/* clear ulimit interrupt status */
FADC_SETBIT(base_addr, FADC_INTR_REG_OFFSET, FADC_INTR_REG_ULIMIT(channel));
FADC_CALL_INTR_EVENT_HANDLDER(pctrl, FADC_INTR_EVENT_ULIMIT);
}
}
}
/* 有中断转换完成的情况下,根据adc_intr_reg寄存器的通道转换完成中断标志位bit0~7,读取转换结果 */
if (status & FADC_INTR_REG_COVFIN_MASK)
{
for (channel = 0; channel < FADC_CHANNEL_NUM; channel++)
{
if (status & FADC_INTR_REG_COVFIN(channel))
{
pctrl->value[channel] = FADC_READ_REG32(base_addr, FADC_COV_RESULT_REG_OFFSET(channel)) & FADC_COV_RESULT_REG_MASK;
FADC_CONVERT_COMPLETE(pctrl->convert_complete[channel]);
/* clear convert finish interrupt status */
FADC_SETBIT(base_addr, FADC_INTR_REG_OFFSET, FADC_INTR_REG_COVFIN(channel));
}
}
FADC_CALL_INTR_EVENT_HANDLDER(pctrl, FADC_INTR_EVENT_COVFIN);
}
else
{
}
return;
}
|