blob: 3bf69ccd225bbea7a06847dcfa5be7666652fa3f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
|
LOAD_REGION_DATA_FLASH DATA_FLASH_START NOCOMPRESS DATA_FLASH_LENGTH
{
__DATA_FLASH_start +0 EMPTY 0 {}
__DATA_FLASH_init +0 EMPTY 0 {}
__ddsc_DATA_FLASH_START +0 EMPTY 0 {}
.data_flash.startof +0 EMPTY 0
{
}
__RAM_start RAM_START +0 EMPTY 0 {}
__ddsc_RAM_START +0 EMPTY 0 {}
.ram.startof +0 EMPTY 0
{
}
__ram_dtc_vector +0 UNINIT
{
*(.bss.fsp_dtc_vector_table)
}
; ram initialized from data_flash
__ram_from_data_flash +0
{
; section.ram.from_data_flash
*(.ram_from_data_flash)
; section.ram.code_from_data_flash
*(.ram_code_from_data_flash)
}
} ; create a root region after the RAM init ERs for remainder of ROM ERs
LOAD_REGION_DATA_FLASH_JUMP +0 NOCOMPRESS
{
__data_flash_readonly +0 FIXED
{
; section.data_flash.readonly
*(.data_flash)
; section.data_flash.code
*(.data_flash_code)
}
__data_flash_noinit +0 FIXED UNINIT
{
; section.data_flash.noinit
*(.bss.data_flash_noinit)
}
__ddsc_DATA_FLASH_END AlignExpr(+0, 512) EMPTY 0 {}
.data_flash.endof AlignExpr(+0, 512) EMPTY 0
{
}
__DATA_FLASH_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__DATA_FLASH_end) - LoadBase(__DATA_FLASH_start)) <= DATA_FLASH_LENGTH )
}
LOAD_REGION_FLASH_GAP FLASH_GAP_START NOCOMPRESS FLASH_GAP_LENGTH
{
__FLASH_GAP_start +0 EMPTY 0 {}
__FLASH_GAP_init +0 EMPTY 0 {}
__ddsc_FLASH_START +0 EMPTY 0 {}
.flash.startof +0 EMPTY 0
{
}
; MCU vector table
_VECTORS +0 EMPTY 0 {}
__flash_gap_vectors +0 FIXED
{
*(.fixed_vectors, +FIRST)
*(.application_vectors)
}
; Sections that can be used to fill flash gap
__flash_gap_readonly_gap +0 FIXED
{
; section.flash.readonly_gap
; *bsp_linker.?*(.rodata.*)
*bsp_linker.?*(.rodata.*)
*(.flash_gap)
; section.flash.code_gap
; *startup.?*(.text.Reset_Handler)
*startup.?*(.text.Reset_Handler)
; *system.?*(.text.*)
*system.?*(.text.*)
*(.flash_gap_code)
}
__FLASH_GAP_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__FLASH_GAP_end) - LoadBase(__FLASH_GAP_start)) <= FLASH_GAP_LENGTH )
}
LOAD_REGION_FLASH FLASH_START NOCOMPRESS FLASH_LENGTH
{
__FLASH_start +0 EMPTY 0 {}
__FLASH_init +0 EMPTY 0 {}
__flash_noinit +0 FIXED UNINIT
{
; section.flash.noinit
*(.bss.flash_noinit)
}
__ram_from_data_flash_jump ImageLimit(__ram_from_data_flash) EMPTY 0 {}
; ram initialized from flash
__ram_from_flash +0
{
; section.ram.from_flash
*(.ram_from_flash)
; section.ram.code_from_flash
*(.ram_code_from_flash)
.ANY(+RW )
*(vtable)
}
; Non-initialized ram
__ram_noinit +0 UNINIT
{
; section.ram.noinit
; *(.bss.g_heap)
; In case this execution region becomes empty due to heap placement place dummy selector
$$.$$(.$$)
}
ARM_LIB_STACK +0 UNINIT EMPTY 0
{
}
ARM_LIB_HEAP +0 UNINIT
{
*(.bss.g_heap)
}
__post_heap +0 UNINIT
{
; *(.bss.g_main_stack)
*(.bss.g_main_stack)
*(.bss.ram_noinit)
*(.bss.noinit)
}
; Zeroed ram
__ram_zero +0
{
; section.ram.zero
*(.bss.ram)
.ANY(+ZI )
}
; Thread Stacks
__ram_thread_stack AlignExpr(+0, 8) UNINIT
{
*(.bss.stack?*)
}
__ddsc_RAM_END AlignExpr(+0, 512) EMPTY 0 {}
.ram.endof AlignExpr(+0, 512) EMPTY 0
{
}
__RAM_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__RAM_end) - LoadBase(__RAM_start)) <= RAM_LENGTH )
} ; create a root region after the RAM init ERs for remainder of ROM ERs
LOAD_REGION_FLASH_JUMP +0 NOCOMPRESS
{
__flash_readonly +0 FIXED
{
; section.flash.readonly
*(.flash)
; section.flash.code
*(.flash_code)
.ANY(+RO-CODE )
.ANY(+RO-DATA )
*(.mcuboot_sce9_key)
*(.version)
}
__init_array_start +0 EMPTY 0 {}
__flash_init_array +0 FIXED
{
*(.init_array.*)
*(.init_array)
}
__init_array_end +0 EMPTY 0 {}
__ddsc_FLASH_END AlignExpr(+0, 512) EMPTY 0 {}
.flash.endof AlignExpr(+0, 512) EMPTY 0
{
}
__FLASH_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__FLASH_end) - LoadBase(__FLASH_start)) <= FLASH_LENGTH )
}
LOAD_REGION_OPTION_SETTING_OFS0 OPTION_SETTING_OFS0_START NOCOMPRESS OPTION_SETTING_OFS0_LENGTH
{
__OPTION_SETTING_OFS0_start +0 EMPTY 0 {}
__OPTION_SETTING_OFS0_init +0 EMPTY 0 {}
__ddsc_OPTION_SETTING_OFS0_START +0 EMPTY 0 {}
.option_setting_ofs0.startof +0 EMPTY 0
{
}
; Option Function Select Register 0
__option_setting_ofs0_reg +0 FIXED
{
*(.option_setting_ofs0)
}
__ddsc_OPTION_SETTING_OFS0_END +0 EMPTY 0 {}
.option_setting_ofs0.endof +0 EMPTY 0
{
}
__OPTION_SETTING_OFS0_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__OPTION_SETTING_OFS0_end) - LoadBase(__OPTION_SETTING_OFS0_start)) <= OPTION_SETTING_OFS0_LENGTH )
}
LOAD_REGION_OPTION_SETTING_OFS1 OPTION_SETTING_OFS1_START NOCOMPRESS OPTION_SETTING_OFS1_LENGTH
{
__OPTION_SETTING_OFS1_start +0 EMPTY 0 {}
__OPTION_SETTING_OFS1_init +0 EMPTY 0 {}
__ddsc_OPTION_SETTING_OFS1_START +0 EMPTY 0 {}
.option_setting_ofs1.startof +0 EMPTY 0
{
}
; Option Function Select Register 1
__option_setting_ofs1_reg +0 FIXED
{
*(.option_setting_ofs1)
}
__ddsc_OPTION_SETTING_OFS1_END +0 EMPTY 0 {}
.option_setting_ofs1.endof +0 EMPTY 0
{
}
__OPTION_SETTING_OFS1_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__OPTION_SETTING_OFS1_end) - LoadBase(__OPTION_SETTING_OFS1_start)) <= OPTION_SETTING_OFS1_LENGTH )
}
LOAD_REGION_OPTION_SETTING_SECMPU OPTION_SETTING_SECMPU_START NOCOMPRESS OPTION_SETTING_SECMPU_LENGTH
{
__OPTION_SETTING_SECMPU_start +0 EMPTY 0 {}
__OPTION_SETTING_SECMPU_init +0 EMPTY 0 {}
__ddsc_OPTION_SETTING_SECMPU_START +0 EMPTY 0 {}
.option_setting_secmpu.startof +0 EMPTY 0
{
}
; Security MPU Registers
__option_setting_secmpu_reg +0 FIXED
{
*(.option_setting_secmpu)
}
__ddsc_OPTION_SETTING_SECMPU_END +0 EMPTY 0 {}
.option_setting_secmpu.endof +0 EMPTY 0
{
}
__OPTION_SETTING_SECMPU_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__OPTION_SETTING_SECMPU_end) - LoadBase(__OPTION_SETTING_SECMPU_start)) <= OPTION_SETTING_SECMPU_LENGTH )
}
LOAD_REGION_OPTION_SETTING_OSIS OPTION_SETTING_OSIS_START NOCOMPRESS OPTION_SETTING_OSIS_LENGTH
{
__OPTION_SETTING_OSIS_start +0 EMPTY 0 {}
__OPTION_SETTING_OSIS_init +0 EMPTY 0 {}
__ddsc_OPTION_SETTING_OSIS_START +0 EMPTY 0 {}
.option_setting_osis.startof +0 EMPTY 0
{
}
; OCD/Serial Programmer ID setting register
__option_setting_osis_reg +0 FIXED
{
*(.option_setting_osis)
}
__ddsc_OPTION_SETTING_OSIS_END +0 EMPTY 0 {}
.option_setting_osis.endof +0 EMPTY 0
{
}
__OPTION_SETTING_OSIS_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__OPTION_SETTING_OSIS_end) - LoadBase(__OPTION_SETTING_OSIS_start)) <= OPTION_SETTING_OSIS_LENGTH )
}
|
