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|
LOAD_REGION_DATA_FLASH DATA_FLASH_START NOCOMPRESS DATA_FLASH_LENGTH
{
__DATA_FLASH_start +0 EMPTY 0 {}
__DATA_FLASH_init +0 EMPTY 0 {}
__ddsc_DATA_FLASH_START +0 EMPTY 0 {}
.data_flash.startof +0 EMPTY 0
{
}
__RAM_start RAM_START +0 EMPTY 0 {}
__ddsc_RAM_START +0 EMPTY 0 {}
.ram.startof +0 EMPTY 0
{
}
__ram_dtc_vector +0 UNINIT
{
*(.bss.fsp_dtc_vector_table)
}
; ram initialized from data_flash
__ram_from_data_flash +0
{
; section.ram.from_data_flash
*(.ram_from_data_flash)
; section.ram.code_from_data_flash
*(.ram_code_from_data_flash)
}
} ; create a root region after the RAM init ERs for remainder of ROM ERs
LOAD_REGION_DATA_FLASH_JUMP +0 NOCOMPRESS
{
__data_flash_readonly +0 FIXED
{
; section.data_flash.readonly
*(.data_flash)
; section.data_flash.code
*(.data_flash_code)
}
__data_flash_noinit +0 FIXED UNINIT
{
; section.data_flash.noinit
*(.bss.data_flash_noinit)
}
__ddsc_DATA_FLASH_END AlignExpr(+0, 1024) EMPTY 0 {}
.data_flash.endof AlignExpr(+0, 1024) EMPTY 0
{
}
__DATA_FLASH_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__DATA_FLASH_end) - LoadBase(__DATA_FLASH_start)) <= DATA_FLASH_LENGTH )
}
LOAD_REGION_FLASH FLASH_START NOCOMPRESS FLASH_LENGTH
{
__FLASH_start +0 EMPTY 0 {}
__FLASH_init +0 EMPTY 0 {}
__ddsc_FLASH_START +0 EMPTY 0 {}
.flash.startof +0 EMPTY 0
{
}
; MCU vector table
_VECTORS +0 EMPTY 0 {}
__flash_vectors +0 FIXED
{
*(.fixed_vectors, +FIRST)
*(.application_vectors)
}
__flash_noinit +0 FIXED UNINIT
{
; section.flash.noinit
*(.bss.flash_noinit)
}
__ram_from_data_flash_jump ImageLimit(__ram_from_data_flash) EMPTY 0 {}
; ram initialized from flash
__ram_from_flash +0
{
; section.ram.from_flash
*(.ram_from_flash)
; section.ram.code_from_flash
*(.ram_code_from_flash)
.ANY(+RW )
*(vtable)
}
; Non-initialized, non-cached ram
__ram_noinit_nocache AlignExpr(+0, 32) UNINIT
{
; section.ram.noinit_nocache
*(.bss.ram_noinit_nocache)
}
; Zeroed, non-cached ram
__ram_zero_nocache +0
{
; section.ram.zero_nocache
*(.bss.ram_nocache)
}
; Execution region required to end align __ram_zero_nocache on ac6
__ram_zero_nocache_pad (ImageLimit(__ram_zero_nocache)) EMPTY (AlignExpr(ImageLimit(__ram_zero_nocache),32) - ImageLimit(__ram_zero_nocache)) {}
; Non-initialized ram
__ram_noinit +0 UNINIT
{
; section.ram.noinit
; *(.bss.g_heap)
; In case this execution region becomes empty due to heap placement place dummy selector
$$.$$(.$$)
}
ARM_LIB_STACK +0 UNINIT EMPTY 0
{
}
ARM_LIB_HEAP +0 UNINIT
{
*(.bss.g_heap)
}
__post_heap +0 UNINIT
{
; *(.bss.g_main_stack)
*(.bss.g_main_stack)
*(.bss.ram_noinit)
*(.bss.noinit)
}
; Zeroed ram
__ram_zero +0
{
; section.ram.zero
*(.bss.ram)
.ANY(+ZI )
}
; Thread Stacks
__ram_thread_stack AlignExpr(+0, 8) UNINIT
{
*(.bss.stack?*)
}
__ddsc_RAM_END AlignExpr(+0, 8192) EMPTY 0 {}
.ram.endof AlignExpr(+0, 8192) EMPTY 0
{
}
__ddsc_RAM_NSC AlignExpr(+0, 8192) EMPTY 0 {}
.ram.flat_nsc AlignExpr(+0, 8192) EMPTY 0
{
}
RAM_END +0 EMPTY 0 {}
SCatterAssert( (LoadBase(RAM_END) - LoadBase(__RAM_start)) <= RAM_LENGTH )
} ; create a root region after the RAM init ERs for remainder of ROM ERs
LOAD_REGION_FLASH_JUMP +0 NOCOMPRESS
{
__flash_readonly +0 FIXED
{
; section.flash.readonly
*(.flash)
; section.flash.code
*(.flash_code)
.ANY(+RO-CODE )
.ANY(+RO-DATA )
*(.mcuboot_sce9_key)
*(.version)
}
__init_array_start +0 EMPTY 0 {}
__flash_init_array +0 FIXED
{
*(.init_array.*)
*(.init_array)
}
__init_array_end +0 EMPTY 0 {}
__ddsc_FLASH_END AlignExpr(+0, 32768) EMPTY 0 {}
.flash.endof AlignExpr(+0, 32768) EMPTY 0
{
}
__ddsc_FLASH_NSC AlignExpr(+0, 32768) EMPTY 0 {}
.flash.flat_nsc AlignExpr(+0, 32768) EMPTY 0
{
}
__FLASH_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__FLASH_end) - LoadBase(__FLASH_start)) <= FLASH_LENGTH )
}
LOAD_REGION_OPTION_SETTING_OFS0 OPTION_SETTING_OFS0_START NOCOMPRESS OPTION_SETTING_OFS0_LENGTH
{
__OPTION_SETTING_OFS0_start +0 EMPTY 0 {}
__OPTION_SETTING_OFS0_init +0 EMPTY 0 {}
__ddsc_OPTION_SETTING_OFS0_START +0 EMPTY 0 {}
.option_setting_ofs0.startof +0 EMPTY 0
{
}
; Option Function Select Register 0 Secure
__option_setting_ofs0_reg +0 FIXED
{
*(.option_setting_ofs0)
}
__ddsc_OPTION_SETTING_OFS0_END +0 EMPTY 0 {}
.option_setting_ofs0.endof +0 EMPTY 0
{
}
__OPTION_SETTING_OFS0_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__OPTION_SETTING_OFS0_end) - LoadBase(__OPTION_SETTING_OFS0_start)) <= OPTION_SETTING_OFS0_LENGTH )
}
LOAD_REGION_OPTION_SETTING_OSIS OPTION_SETTING_OSIS_START NOCOMPRESS OPTION_SETTING_OSIS_LENGTH
{
__OPTION_SETTING_OSIS_start +0 EMPTY 0 {}
__OPTION_SETTING_OSIS_init +0 EMPTY 0 {}
__ddsc_OPTION_SETTING_OSIS_START +0 EMPTY 0 {}
.option_setting_osis.startof +0 EMPTY 0
{
}
; OCD/Serial Programmer ID setting register Secure
__option_setting_osis_reg +0 FIXED
{
*(.option_setting_osis)
}
__ddsc_OPTION_SETTING_OSIS_END +0 EMPTY 0 {}
.option_setting_osis.endof +0 EMPTY 0
{
}
__OPTION_SETTING_OSIS_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__OPTION_SETTING_OSIS_end) - LoadBase(__OPTION_SETTING_OSIS_start)) <= OPTION_SETTING_OSIS_LENGTH )
}
LOAD_REGION_OPTION_SETTING_OFS1_SEC OPTION_SETTING_OFS1_SEC_START NOCOMPRESS OPTION_SETTING_OFS1_SEC_LENGTH
{
__OPTION_SETTING_OFS1_SEC_start +0 EMPTY 0 {}
__OPTION_SETTING_OFS1_SEC_init +0 EMPTY 0 {}
__ddsc_OPTION_SETTING_OFS1_SEC_START +0 EMPTY 0 {}
.option_setting_ofs1_sec.startof +0 EMPTY 0
{
}
; Option Function Select Register 1 Secure
__option_setting_ofs1_sec_reg +0 FIXED
{
*(.option_setting_ofs1_sec)
}
__ddsc_OPTION_SETTING_OFS1_SEC_END +0 EMPTY 0 {}
.option_setting_ofs1_sec.endof +0 EMPTY 0
{
}
__OPTION_SETTING_OFS1_SEC_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__OPTION_SETTING_OFS1_SEC_end) - LoadBase(__OPTION_SETTING_OFS1_SEC_start)) <= OPTION_SETTING_OFS1_SEC_LENGTH )
}
LOAD_REGION_OPTION_SETTING_BPS_SEC OPTION_SETTING_BPS_SEC_START NOCOMPRESS OPTION_SETTING_BPS_SEC_LENGTH
{
__OPTION_SETTING_BPS_SEC_start +0 EMPTY 0 {}
__OPTION_SETTING_BPS_SEC_init +0 EMPTY 0 {}
__ddsc_OPTION_SETTING_BPS_SEC_START +0 EMPTY 0 {}
.option_setting_bps_sec.startof +0 EMPTY 0
{
}
; Block Protect Setting Register Secure
__option_setting_bps_sec_reg +0 FIXED
{
*(.option_setting_bps_sec)
}
__ddsc_OPTION_SETTING_BPS_SEC_END +0 EMPTY 0 {}
.option_setting_bps_sec.endof +0 EMPTY 0
{
}
__OPTION_SETTING_BPS_SEC_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__OPTION_SETTING_BPS_SEC_end) - LoadBase(__OPTION_SETTING_BPS_SEC_start)) <= OPTION_SETTING_BPS_SEC_LENGTH )
}
LOAD_REGION_OPTION_SETTING_PBPS_SEC OPTION_SETTING_PBPS_SEC_START NOCOMPRESS OPTION_SETTING_PBPS_SEC_LENGTH
{
__OPTION_SETTING_PBPS_SEC_start +0 EMPTY 0 {}
__OPTION_SETTING_PBPS_SEC_init +0 EMPTY 0 {}
__ddsc_OPTION_SETTING_PBPS_SEC_START +0 EMPTY 0 {}
.option_setting_pbps_sec.startof +0 EMPTY 0
{
}
; Permanent Block Protect Setting Register Secure
__option_setting_pbps_sec_reg +0 FIXED
{
*(.option_setting_pbps_sec)
}
__ddsc_OPTION_SETTING_PBPS_SEC_END +0 EMPTY 0 {}
.option_setting_pbps_sec.endof +0 EMPTY 0
{
}
__OPTION_SETTING_PBPS_SEC_end +0 EMPTY 0 {}
SCatterAssert( (LoadBase(__OPTION_SETTING_PBPS_SEC_end) - LoadBase(__OPTION_SETTING_PBPS_SEC_start)) <= OPTION_SETTING_PBPS_SEC_LENGTH )
}
|
