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/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-10-28 yuanjie first version
*/
#include <rtthread.h>
#include "hal_data.h"
#ifdef BSP_USING_HYPERRAM
#define DRV_DEBUG
#define LOG_TAG "drv.hyper"
#include <drv_log.h>
#define PSRAM_BANK_ADDR ((uint32_t)0x44000000UL) // XSPI0 CS1
#define PSRAM_SIZE ((uint32_t)0x2000000UL) // 32MBytes
#define PSRAM_DATA_WIDTH 16
#ifdef RT_USING_MEMHEAP_AS_HEAP
static struct rt_memheap system_heap;
#endif
static int HYPERRAM_Init(void)
{
int result = RT_EOK;
/* XSPI initial settings */
/* Initialize the PSRAM controller */
if (R_XSPI_HYPER_Open(&g_hyperbus0_ctrl, &g_hyperbus0_cfg) != FSP_SUCCESS)
{
LOG_E("HYPER RAM init failed!");
result = -RT_ERROR;
}
else
{
LOG_D("psram init success, mapped at 0x%X, size is %d bytes, data width is %d", PSRAM_BANK_ADDR, PSRAM_SIZE, PSRAM_DATA_WIDTH);
#ifdef RT_USING_MEMHEAP_AS_HEAP
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, PSRAM is initialized to the heap */
rt_memheap_init(&system_heap, "psram", (void *)PSRAM_BANK_ADDR, PSRAM_SIZE);
#endif
}
return result;
}
INIT_BOARD_EXPORT(HYPERRAM_Init);
#ifdef DRV_DEBUG
#ifdef FINSH_USING_MSH
int psram_test(void)
{
int i = 0;
uint32_t start_time = 0, time_cast = 0;
#if PSRAM_DATA_WIDTH == 8
char data_width = 1;
uint8_t data = 0;
#elif PSRAM_DATA_WIDTH == 16
char data_width = 2;
uint16_t data = 0;
#else
char data_width = 4;
uint32_t data = 0;
#endif
/* write data */
LOG_D("Writing the %ld bytes data, waiting....", PSRAM_SIZE);
start_time = rt_tick_get();
for (i = 0; i < PSRAM_SIZE / data_width; i++)
{
#if PSRAM_DATA_WIDTH == 8
*(__IO uint8_t *)(PSRAM_BANK_ADDR + i * data_width) = (uint8_t)0x55;
#elif PSRAM_DATA_WIDTH == 16
*(__IO uint16_t *)(PSRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5555;
#else
*(__IO uint32_t *)(PSRAM_BANK_ADDR + i * data_width) = (uint32_t)0x55555555;
#endif
}
time_cast = rt_tick_get() - start_time;
LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
/* read data */
LOG_D("start Reading and verifying data, waiting....");
for (i = 0; i < PSRAM_SIZE / data_width; i++)
{
#if PSRAM_DATA_WIDTH == 8
data = *(__IO uint8_t *)(PSRAM_BANK_ADDR + i * data_width);
if (data != 0x55)
{
LOG_E("PSRAM test failed!");
break;
}
#elif PSRAM_DATA_WIDTH == 16
data = *(__IO uint16_t *)(PSRAM_BANK_ADDR + i * data_width);
if (data != 0x5555)
{
LOG_E("PSRAM test failed!");
break;
}
#else
data = *(__IO uint32_t *)(PSRAM_BANK_ADDR + i * data_width);
if (data != 0x55555555)
{
LOG_E("PSRAM test failed!");
break;
}
#endif
}
if (i >= PSRAM_SIZE / data_width)
{
LOG_D("PSRAM test success!");
}
return RT_EOK;
}
MSH_CMD_EXPORT(psram_test, XSPI XIP hyper ram test)
#endif /* FINSH_USING_MSH */
#endif /* DRV_DEBUG */
#endif /* BSP_USING_HYPERRAM */
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