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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2019-2021 Rockchip Electronics Co., Ltd.
*/
#include "soc.h"
#include "hal_base.h"
#include "hal_def.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define SYSTEM_CLOCK (24000000U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[80];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
void CacheInit(void)
{
#if defined(HAL_ICACHE_MODULE_ENABLED) || defined(HAL_DCACHE_MODULE_ENABLED)
uint32_t status;
#endif
#if defined(HAL_ICACHE_MODULE_ENABLED)
/* config icache: mpu disable, stb disable, write through, hot buffer enable */
ICACHE->CACHE_CTRL |= (ICACHE_CACHE_CTRL_CACHE_EN_MASK | ICACHE_CACHE_CTRL_CACHE_WT_EN_MASK |
ICACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK);
ICACHE->CACHE_CTRL &= (~ICACHE_CACHE_CTRL_CACHE_STB_EN_MASK);
do {
status =
ICACHE->CACHE_STATUS & ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK;
} while (status == 0);
ICACHE->CACHE_CTRL &= ~ICACHE_CACHE_CTRL_CACHE_BYPASS_MASK;
#endif
#if defined(HAL_DCACHE_MODULE_ENABLED)
/* stb enable, stb_entry=7, stb_timeout enable, write back */
DCACHE->CACHE_CTRL |= DCACHE_CACHE_CTRL_CACHE_EN_MASK |
(7U << DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) |
DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK |
DCACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK;
DCACHE->STB_TIMEOUT_CTRL = 1;
do {
status =
DCACHE->CACHE_STATUS & DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK;
} while (status == 0);
DCACHE->CACHE_CTRL &= ~DCACHE_CACHE_CTRL_CACHE_BYPASS_MASK;
/* enable dap cache access for jtag protocol. don't modify the uncache data
* by jtag, the data will be inconsistent. */
GRF->MCU_CON0 |= GRF_MCU_CON0_M4_DAP_DCACHE_MASK;
#endif
}
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate(void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit(void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
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