1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
|
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-3-08 GuEe-GUI the first version
*/
#ifndef __CLK_RK_PLL_H__
#define __CLK_RK_PLL_H__
#include "clk-rk.h"
enum rockchip_pll_type
{
pll_type_rk3036,
pll_type_rk3066,
pll_type_rk3328,
pll_type_rk3399,
pll_type_rk3588,
pll_type_rk3588_core,
pll_type_rk3588_ddr,
};
struct rockchip_pll_rate_table
{
rt_ubase_t rate;
union
{
struct
{
/* For RK3066 */
rt_uint32_t nr;
rt_uint32_t nf;
rt_uint32_t no;
rt_uint32_t nb;
};
struct
{
/* For RK3036/RK3399 */
rt_uint32_t fbdiv;
rt_uint32_t postdiv1;
rt_uint32_t refdiv;
rt_uint32_t postdiv2;
rt_uint32_t dsmpd;
rt_uint32_t frac;
};
struct
{
/* For RK3588 */
rt_uint32_t m;
rt_uint32_t p;
rt_uint32_t s;
rt_uint32_t k;
};
};
};
#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
{ \
.rate = _rate##U, \
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
}
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac) \
{ \
.rate = _rate##U, \
.fbdiv = _fbdiv, \
.postdiv1 = _postdiv1, \
.refdiv = _refdiv, \
.postdiv2 = _postdiv2, \
.dsmpd = _dsmpd, \
.frac = _frac, \
}
#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
{ \
.rate = _rate##U, \
.p = _p, \
.m = _m, \
.s = _s, \
.k = _k, \
}
struct rockchip_pll_clk_cell
{
struct rockchip_clk_cell rk_cell;
enum rockchip_pll_type type;
int con_offset;
int mode_offset;
int mode_shift;
int lock_shift;
int grf_lock_offset;
int sel;
rt_ubase_t scaling;
#define ROCKCHIP_PLL_SYNC_RATE RT_BIT(0)
#define ROCKCHIP_PLL_FIXED_MODE RT_BIT(1)
#define ROCKCHIP_PLL_ALLOW_POWER_DOWN RT_BIT(2)
rt_uint8_t flags;
struct rockchip_pll_rate_table *rate_table;
};
#define PLL_RAW(_type, _id, _name, _pnames, _pnames_nr, _flags, _con, _mode, _mshift, _lshift, _glock, _pflags, _rtable) \
{ \
.rk_cell.cell.name = _name, \
.rk_cell.cell.parent_names = _pnames, \
.rk_cell.cell.parents_nr = _pnames_nr, \
.rk_cell.cell.flags = RT_CLK_F_GET_RATE_NOCACHE | _flags, \
.rk_cell.id = _id, \
.rk_cell.init = rockchip_pll_clk_cell_init, \
.rk_cell.setup = rockchip_pll_clk_cell_setup, \
.type = _type, \
.con_offset = _con, \
.mode_offset = _mode, \
.mode_shift = _mshift, \
.lock_shift = _lshift, \
.grf_lock_offset = _glock, \
.flags = _pflags, \
.rate_table = _rtable, \
}
#define PLL(_type, _id, _name, _pnames, _pnames_nr, _flags, _con, _mode, _mshift, _lshift, _glock, _pflags, _rtable) \
(void *)&(struct rockchip_pll_clk_cell)PLL_RAW(_type, _id, _name, _pnames, _pnames_nr, _flags, _con, _mode, _mshift, _lshift, _glock, _pflags, _rtable)
rt_inline struct rockchip_pll_clk_cell *cell_to_rockchip_pll_clk_cell(struct rt_clk_cell *cell)
{
struct rockchip_clk_cell *rk_cell = cell_to_rockchip_clk_cell(cell);
return rt_container_of(rk_cell, struct rockchip_pll_clk_cell, rk_cell);
}
void rockchip_pll_clk_cell_init(struct rockchip_clk_cell *rk_cell);
void rockchip_pll_clk_cell_setup(struct rockchip_clk_cell *rk_cell);
#endif /* __CLK_RK_PLL_H__ */
|
