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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__
#define __DT_BINDINGS_POWER_RK3368_POWER_H__
/* VD_CORE */
#define RK3368_PD_A53_L0 0
#define RK3368_PD_A53_L1 1
#define RK3368_PD_A53_L2 2
#define RK3368_PD_A53_L3 3
#define RK3368_PD_SCU_L 4
#define RK3368_PD_A53_B0 5
#define RK3368_PD_A53_B1 6
#define RK3368_PD_A53_B2 7
#define RK3368_PD_A53_B3 8
#define RK3368_PD_SCU_B 9
/* VD_LOGIC */
#define RK3368_PD_BUS 10
#define RK3368_PD_PERI 11
#define RK3368_PD_VIO 12
#define RK3368_PD_ALIVE 13
#define RK3368_PD_VIDEO 14
#define RK3368_PD_GPU_0 15
#define RK3368_PD_GPU_1 16
/* VD_PMU */
#define RK3368_PD_PMU 17
#endif /* __DT_BINDINGS_POWER_RK3368_POWER_H__ */
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