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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
/* kservice optimization */
/* Inter-Thread communication */
/* Memory Management */
/* RT-Thread Components */
/* DFS: device virtual file system */
/* Device Drivers */
/* Using USB */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Memory protection */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread board config */
/* RT-Thread rockchip common drivers */
/* RT-Thread rockchip RK2108 drivers */
/* Enable UART */
MEMORY
{
FLASH (rx) : ORIGIN = 0x18000000, LENGTH = 16M /* Nor Flash */
SRAM_I (rxw) : ORIGIN = 0x04000000, LENGTH = 1M /* SRAM */
SRAM_D (rxw) : ORIGIN = 0x20000000, LENGTH = 1M /* SRAM */
}
MAIN_STACK_SIZE = 0x400;
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
. = ALIGN(32);
KEEP(*(.vectors))
. = ALIGN(32);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
*(.rodata*)
*(COMMON)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
. = ALIGN(4);
KEEP(*(.eh_frame*))
} > SRAM_I
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > SRAM_I
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > SRAM_I
.ctors :
{
. = ALIGN(32);
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
. = ALIGN(32);
PROVIDE(__ctors_end__ = .);
} > SRAM_I
.dtors :
{
. = ALIGN(32);
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
. = ALIGN(32);
PROVIDE(__dtors_end__ = .);
} > SRAM_I
.copy.table :
{
. = ALIGN(32);
PROVIDE(__copy_table_start__ = .);
LONG (__etext)
LONG (__data_start__)
LONG ((__data_end__ - __data_start__) / 4)
PROVIDE(__copy_table_end__ = .);
} > SRAM_I
.zero.table :
{
. = ALIGN(32);
PROVIDE(__zero_table_start__ = .);
LONG (__bss_start__)
LONG ((__bss_end__ - __bss_start__) / 4)
PROVIDE(__zero_table_end__ = .);
} > SRAM_I
/**
* Location counter can end up 2byte aligned with narrow Thumb code but
* __etext is assumed by startup code to be the LMA of a section in RAM
* which must be 4byte aligned. In addition, 32byte cacheline alignment
* is required here, because of RK2108 with cache.
*/
__etext = ALIGN (32);
SRAM_DATA_DEST = ORIGIN(SRAM_D) + __etext - ORIGIN(SRAM_I);
.data SRAM_DATA_DEST : AT (__etext)
{
__data_start__ = ALIGN (32);
*(vtable)
*(.data)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
_gp = ABSOLUTE(.); /* Base of small data */
. = ALIGN(32);
/* All data end */
__data_end__ = .;
} > SRAM_D
.bss :
{
. = ALIGN(32);
PROVIDE(__bss_start__ = .);
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
. = ALIGN(32);
PROVIDE(__bss_end__ = .);
} > SRAM_D
.stack :
{
. = ALIGN(32);
__StackLimit = .;
. = . + MAIN_STACK_SIZE;
. = ALIGN(32);
__StackTop = .;
__stack = __StackTop;
} > SRAM_D
.heap :
{
. = ALIGN(32);
PROVIDE(__heap_begin = .);
__end__ = .;
PROVIDE(end = .);
. = ORIGIN(SRAM_D) + LENGTH(SRAM_D);
__HeapLimit = .;
PROVIDE(__heap_end = .);
} > SRAM_D
}
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