1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
|
/*
* Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik format file
*/
#include "drv_timer.h"
#ifdef RT_USING_CLOCK_TIME
#ifdef BSP_USING_TIM
//#define DRV_DEBUG
#define LOG_TAG "drv.clock_timer"
#include <drv_log.h>
#if !defined(BSP_USING_TIM0) && !defined(BSP_USING_TIM1) && !defined(BSP_USING_TIM2) && !defined(BSP_USING_TIM3) \
&& !defined(BSP_USING_TIM4) && !defined(BSP_USING_TIM5)
#error "Please define at least one BSP_USING_TIMx"
/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 120000000, \
.minfreq = 120000000, \
.maxcnt = 0xFFFFFFFF, \
.cntmode = CLOCK_TIMER_CNTMODE_DW, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_TIM0
#ifndef TIM0_CFG
#define TIM0_CFG \
{ \
.name = "timer0", \
.TIMRx = TIMR0, \
}
#endif /* TIM0_CFG */
#endif /* BSP_USING_TIM0 */
#ifdef BSP_USING_TIM1
#ifndef TIM1_CFG
#define TIM1_CFG \
{ \
.name = "timer1", \
.TIMRx = TIMR1, \
}
#endif /* TIM1_CFG */
#endif /* BSP_USING_TIM1 */
#ifdef BSP_USING_TIM2
#ifndef TIM2_CFG
#define TIM2_CFG \
{ \
.name = "timer2", \
.TIMRx = TIMR2, \
}
#endif /* TIM2_CFG */
#endif /* BSP_USING_TIM2 */
#ifdef BSP_USING_TIM3
#ifndef TIM3_CFG
#define TIM3_CFG \
{ \
.name = "timer3", \
.TIMRx = TIMR3, \
}
#endif /* TIM3_CFG */
#endif /* BSP_USING_TIM3 */
#ifdef BSP_USING_TIM4
#ifndef TIM4_CFG
#define TIM4_CFG \
{ \
.name = "timer4", \
.TIMRx = TIMR4, \
}
#endif /* TIM4_CFG */
#endif /* BSP_USING_TIM4 */
#ifdef BSP_USING_TIM5
#ifndef TIM5_CFG
#define TIM5_CFG \
{ \
.name = "timer5", \
.TIMRx = TIMR5, \
}
#endif /* TIM5_CFG */
#endif /* BSP_USING_TIM5 */
struct swm_clock_timer_cfg
{
char *name;
TIMR_TypeDef *TIMRx;
};
struct swm_clock_timer_device
{
struct swm_clock_timer_cfg *clock_timer_cfg;
rt_clock_timer_t time_device;
};
enum
{
#ifdef BSP_USING_TIM0
TIM0_INDEX,
#endif
#ifdef BSP_USING_TIM1
TIM1_INDEX,
#endif
#ifdef BSP_USING_TIM2
TIM2_INDEX,
#endif
#ifdef BSP_USING_TIM3
TIM3_INDEX,
#endif
#ifdef BSP_USING_TIM4
TIM4_INDEX,
#endif
#ifdef BSP_USING_TIM5
TIM5_INDEX,
#endif
};
static struct swm_clock_timer_cfg swm_clock_timer_cfg[] =
{
#ifdef BSP_USING_TIM0
TIM0_CFG,
#endif
#ifdef BSP_USING_TIM1
TIM1_CFG,
#endif
#ifdef BSP_USING_TIM2
TIM2_CFG,
#endif
#ifdef BSP_USING_TIM3
TIM3_CFG,
#endif
#ifdef BSP_USING_TIM4
TIM4_CFG,
#endif
#ifdef BSP_USING_TIM5
TIM5_CFG,
#endif
};
static struct swm_clock_timer_device clock_timer_obj[sizeof(swm_clock_timer_cfg) / sizeof(swm_clock_timer_cfg[0])] = {0};
static void swm_timer_configure(struct rt_clock_timer_device *timer_device, rt_uint32_t state)
{
struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
if (state)
{
clock_timer_cfg = timer_device->parent.user_data;
TIMR_Init(clock_timer_cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1);
timer_device->freq = SystemCoreClock;
}
}
static rt_err_t swm_timer_start(rt_clock_timer_t *timer_device, rt_uint32_t cnt, rt_clock_timer_mode_t opmode)
{
rt_err_t result = RT_EOK;
struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
clock_timer_cfg = timer_device->parent.user_data;
if (opmode == CLOCK_TIMER_MODE_ONESHOT)
{
/* set timer to single mode */
timer_device->mode = CLOCK_TIMER_MODE_ONESHOT;
}
else
{
timer_device->mode = CLOCK_TIMER_MODE_PERIOD;
}
TIMR_SetPeriod(clock_timer_cfg->TIMRx, cnt);
TIMR_Stop(clock_timer_cfg->TIMRx);
TIMR_Start(clock_timer_cfg->TIMRx);
return result;
}
static void swm_timer_stop(rt_clock_timer_t *timer_device)
{
struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
clock_timer_cfg = timer_device->parent.user_data;
/* stop timer */
TIMR_Stop(clock_timer_cfg->TIMRx);
}
static rt_uint32_t swm_timer_count_get(rt_clock_timer_t *timer_device)
{
struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
clock_timer_cfg = timer_device->parent.user_data;
return TIMR_GetCurValue(clock_timer_cfg->TIMRx);
}
static rt_err_t swm_timer_control(rt_clock_timer_t *timer_device, rt_uint32_t cmd, void *args)
{
struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL;
rt_err_t result = RT_EOK;
RT_ASSERT(timer_device != RT_NULL);
RT_ASSERT(args != RT_NULL);
clock_timer_cfg = timer_device->parent.user_data;
switch (cmd)
{
case CLOCK_TIMER_CTRL_FREQ_SET:
{
rt_uint32_t freq;
freq = *(rt_uint32_t *)args;
TIMR_Init(clock_timer_cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1);
}
break;
default:
{
result = -RT_ENOSYS;
}
break;
}
return result;
}
static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG;
static const struct rt_clock_timer_ops swm_timer_ops =
{
.init = swm_timer_configure,
.start = swm_timer_start,
.stop = swm_timer_stop,
.count_get = swm_timer_count_get,
.control = swm_timer_control};
void swm_timer_isr(rt_clock_timer_t *timer_device)
{
struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
clock_timer_cfg = timer_device->parent.user_data;
TIMR_INTClr(clock_timer_cfg->TIMRx);
rt_clock_timer_isr(timer_device);
}
#ifdef BSP_USING_TIM0
void TIMR0_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
swm_timer_isr(&(clock_timer_obj[TIM0_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM0
#ifdef BSP_USING_TIM1
void TIMR1_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
swm_timer_isr(&(clock_timer_obj[TIM1_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM1
#ifdef BSP_USING_TIM2
void TIMR2_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
swm_timer_isr(&(clock_timer_obj[TIM2_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM2
#ifdef BSP_USING_TIM3
void TIMR3_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
swm_timer_isr(&(clock_timer_obj[TIM3_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM3
#ifdef BSP_USING_TIM4
void TIMR4_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
swm_timer_isr(&(clock_timer_obj[TIM4_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM4
#ifdef BSP_USING_TIM5
void TIMR5_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
swm_timer_isr(&(clock_timer_obj[TIM5_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM5
static int swm_timer_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(swm_clock_timer_cfg) / sizeof(swm_clock_timer_cfg[0]); i++)
{
clock_timer_obj[i].clock_timer_cfg = &swm_clock_timer_cfg[i];
clock_timer_obj[i].time_device.info = &_info;
clock_timer_obj[i].time_device.ops = &swm_timer_ops;
result = rt_clock_timer_register(&clock_timer_obj[i].time_device, clock_timer_obj[i].clock_timer_cfg->name, clock_timer_obj[i].clock_timer_cfg);
if (result != RT_EOK)
{
LOG_E("%s register fail.", clock_timer_obj[i].clock_timer_cfg->name);
}
else
{
LOG_D("%s register success.", clock_timer_obj[i].clock_timer_cfg->name);
}
}
return result;
}
INIT_BOARD_EXPORT(swm_timer_init);
#endif /* BSP_USING_TIM */
#endif /* RT_USING_CLOCK_TIME */
|
