summaryrefslogtreecommitdiff
path: root/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c
blob: 0f8ff9d52b87ac3cffea4c033c7d0de7b202e628 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
//###########################################################################
//
// FILE:   F2837xD_Emif.c
//
// TITLE:  F2837xD EMIF Initialization & Support Functions.
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.05.00.00 $
// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
// $Copyright:
// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F2837xD_device.h"
#include "F2837xD_Examples.h"

//
// Emif1Initialize - This function initializes the EMIF1 to a known state.
//
void Emif1Initialize(void)
{
    EALLOW;
    //
    // Perform a Module soft reset on EMIF
    //
#ifdef CPU1
    DevCfgRegs.SOFTPRES1.all = 0x1;
   __asm (" nop");
    DevCfgRegs.SOFTPRES1.all = 0x0;
#endif
    EDIS;
}

//
// Emif2Initialize - This function initializes the EMIF2 to a known state.
//
void Emif2Initialize(void)
{
    EALLOW;
    //
    // Perform a Module soft reset on EMIF
    //
#ifdef CPU1
    DevCfgRegs.SOFTPRES1.all = 0x2;
   __asm (" nop");
    DevCfgRegs.SOFTPRES1.all = 0x0;
#endif
    EDIS;
}

//
// ASync_wait_config - Async wait configuration function
//
void ASync_wait_config(Uint16 inst, Uint16 wait_count, Uint16 wait_polarity)
{
    if (inst == 0)
    {
        //
        // 7:0 Maximum Extended Wait cycles.
        //
        Emif1Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count;

        //
        // 28 Wait Polarity for pad_wait_i[0].
        //
        Emif1Regs.ASYNC_WCCR.bit.WP0 = wait_polarity;
    }
    else
    {
        //
        // 7:0 Maximum Extended Wait cycles.
        //
        Emif2Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count;

        //
        // 28 Wait Polarity for pad_wait_i[0].
        //
        Emif2Regs.ASYNC_WCCR.bit.WP0 = wait_polarity;
    }
}

//
// ASync_cs2_config - Async CS2 Configuration
//
void ASync_cs2_config(Uint16 inst, Uint16 async_mem_data_width,
                      Uint16 turn_around_time, Uint16 r_hold_time,
                      Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold,
                      Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait,
                      Uint16 strobe_sel)
{
    if (inst == 0)
    {
        //
        // 1:0 Asynchronous Memory Size.
        // 3:2 Turn Around cycles.
        // 6:4 Read Strobe Hold cycles.
        // 12:7 Read Strobe Duration cycles.
        // 16:13 Read Strobe Setup cycles.
        // 19:17 Write Strobe Hold cycles.
        // 25:20 Write Strobe Duration cycles.
        // 29:26 Write Strobe Setup cycles.
        // 30 Extend Wait mode.
        // 31 Select Strobe mode.
        //
        Emif1Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width;
        Emif1Regs.ASYNC_CS2_CR.bit.TA= turn_around_time;
        Emif1Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time;
        Emif1Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time;
        Emif1Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup;
        Emif1Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold;
        Emif1Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe;
        Emif1Regs.ASYNC_CS2_CR.bit.W_SETUP  = w_setup;
        Emif1Regs.ASYNC_CS2_CR.bit.EW = extend_wait;
        Emif1Regs.ASYNC_CS2_CR.bit.SS = strobe_sel;
    }
    else
    {
        //
        // 1:0 Asynchronous Memory Size.
        // 3:2 Turn Around cycles.
        // 6:4 Read Strobe Hold cycles.
        // 12:7 Read Strobe Duration cycles.
        // 16:13 Read Strobe Setup cycles.
        // 19:17 Write Strobe Hold cycles.
        // 25:20 Write Strobe Duration cycles.
        // 29:26 Write Strobe Setup cycles.
        // 30 Extend Wait mode.
        // 31 Select Strobe mode.
        //
        Emif2Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width;
        Emif2Regs.ASYNC_CS2_CR.bit.TA= turn_around_time;
        Emif2Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time;
        Emif2Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time;
        Emif2Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup;
        Emif2Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold;
        Emif2Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe;
        Emif2Regs.ASYNC_CS2_CR.bit.W_SETUP  = w_setup;
        Emif2Regs.ASYNC_CS2_CR.bit.EW = extend_wait;
        Emif2Regs.ASYNC_CS2_CR.bit.SS = strobe_sel;
    }
}

//
// ASync_cs3_config - Async CS3 Configuration
//
void ASync_cs3_config(Uint16 inst, Uint16 async_mem_data_width,
                      Uint16 turn_around_time, Uint16 r_hold_time,
                      Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold,
                      Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait,
                      Uint16 strobe_sel)
{
    //
    // 1:0 Asynchronous Memory Size.
    // 3:2 Turn Around cycles.
    // 6:4 Read Strobe Hold cycles.
    // 12:7 Read Strobe Duration cycles.
    // 16:13 Read Strobe Setup cycles.
    // 19:17 Write Strobe Hold cycles.
    // 25:20 Write Strobe Duration cycles.
    // 29:26 Write Strobe Setup cycles.
    // 30 Extend Wait mode.
    // 31 Select Strobe mode.
    //
    Emif1Regs.ASYNC_CS3_CR.bit.ASIZE = async_mem_data_width;
    Emif1Regs.ASYNC_CS3_CR.bit.TA= turn_around_time;
    Emif1Regs.ASYNC_CS3_CR.bit.R_HOLD= r_hold_time;
    Emif1Regs.ASYNC_CS3_CR.bit.R_STROBE = r_strobe_time;
    Emif1Regs.ASYNC_CS3_CR.bit.R_SETUP = r_setup;
    Emif1Regs.ASYNC_CS3_CR.bit.W_HOLD = w_hold;
    Emif1Regs.ASYNC_CS3_CR.bit.W_STROBE = w_strobe;
    Emif1Regs.ASYNC_CS3_CR.bit.W_SETUP  = w_setup;
    Emif1Regs.ASYNC_CS3_CR.bit.EW = extend_wait;
    Emif1Regs.ASYNC_CS3_CR.bit.SS = strobe_sel;
}

//
// ASync_cs4_config - Async CS4 Configuration
//
void ASync_cs4_config(Uint16 inst, Uint16 async_mem_data_width,
                      Uint16 turn_around_time, Uint16 r_hold_time,
                      Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold,
                      Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait,
                      Uint16 strobe_sel)
{
    //
    // 1:0 Asynchronous Memory Size.
    // 3:2 Turn Around cycles.
    // 6:4 Read Strobe Hold cycles.
    // 12:7 Read Strobe Duration cycles.
    // 16:13 Read Strobe Setup cycles.
    // 19:17 Write Strobe Hold cycles.
    // 25:20 Write Strobe Duration cycles.
    // 29:26 Write Strobe Setup cycles.
    // 30 Extend Wait mode.
    // 31 Select Strobe mode.
    //
    Emif1Regs.ASYNC_CS4_CR.bit.ASIZE = async_mem_data_width;
    Emif1Regs.ASYNC_CS4_CR.bit.TA= turn_around_time;
    Emif1Regs.ASYNC_CS4_CR.bit.R_HOLD= r_hold_time;
    Emif1Regs.ASYNC_CS4_CR.bit.R_STROBE = r_strobe_time;
    Emif1Regs.ASYNC_CS4_CR.bit.R_SETUP = r_setup;
    Emif1Regs.ASYNC_CS4_CR.bit.W_HOLD = w_hold;
    Emif1Regs.ASYNC_CS4_CR.bit.W_STROBE = w_strobe;
    Emif1Regs.ASYNC_CS4_CR.bit.W_SETUP  = w_setup;
    Emif1Regs.ASYNC_CS4_CR.bit.EW = extend_wait;
    Emif1Regs.ASYNC_CS4_CR.bit.SS = strobe_sel;
}

#ifdef CPU1
//
// setup_emif1_pinmux_async_16bit - function for EMIF1 GPIO pin setup
//
void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel)
{
    Uint16 i;

    for (i=28; i<=52; i++)
    {
        if ((i != 42) && (i != 43))
        {
            GPIO_SetupPinMux(i,cpu_sel,2);
        }
    }
    for (i=63; i<=87; i++)
    {
        if (i != 84)
        {
            GPIO_SetupPinMux(i,cpu_sel,2);
        }
    }

    GPIO_SetupPinMux(88,cpu_sel,3);
    GPIO_SetupPinMux(89,cpu_sel,3);
    GPIO_SetupPinMux(90,cpu_sel,3);
    GPIO_SetupPinMux(91,cpu_sel,3);
    GPIO_SetupPinMux(92,cpu_sel,3);
    GPIO_SetupPinMux(93,cpu_sel,3);
    GPIO_SetupPinMux(94,cpu_sel,2);

    //
    //setup async mode and enable pull-ups for Data pins
    //
    for (i=69; i<=85; i++)
    {
        if (i != 84)
        {
            GPIO_SetupPinOptions(i,0,0x31); // GPIO_ASYNC||GPIO_PULLUP
        }
    }
}

//
// setup_emif1_pinmux_async_32bit - Setup pinmux for 32bit async
//
void setup_emif1_pinmux_async_32bit(Uint16 cpu_sel)
{
    Uint16 i;

    for (i=28; i<=87; i++)
    {
        if ((i != 42) && (i != 43) && (i != 84))
        {
            GPIO_SetupPinMux(i,cpu_sel,2);
        }
    }

    GPIO_SetupPinMux(88,cpu_sel,3);
    GPIO_SetupPinMux(89,cpu_sel,3);
    GPIO_SetupPinMux(90,cpu_sel,3);
    GPIO_SetupPinMux(91,cpu_sel,3);
    GPIO_SetupPinMux(92,cpu_sel,3);
    GPIO_SetupPinMux(93,cpu_sel,3);
    GPIO_SetupPinMux(94,cpu_sel,2);

    //
    //setup async mode for Data pins
    //
    for (i=53; i<=85; i++)
    {
        if (i != 84)
        {
            GPIO_SetupPinOptions(i,0,0x31);
        }
    }
}

//
// setup_emif2_pinmux_async_16bit - function for EMIF1 GPIO pin setup
//
void setup_emif2_pinmux_async_16bit(Uint16 cpu_sel)
{
    Uint16 i;

    for (i=96; i<=121; i++)
    {
        GPIO_SetupPinMux(i,cpu_sel,3);
    }

    for (i=53; i<=68; i++)
    {
        GPIO_SetupPinMux(i,cpu_sel,3);
    }

    //
    //setup async mode for Data pins
    //
    for (i=53; i<=68; i++)
    {
        GPIO_SetupPinOptions(i,0,0x31);
    }
}

//
// setup_emif1_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM
//
void setup_emif1_pinmux_sdram_16bit(Uint16 cpu_sel)
{
    int i;

    for (i=29; i<=52; i++)
    {
        if ((i != 42) && (i != 43))
        {
            GPIO_SetupPinMux(i,cpu_sel,2);
        }
    }

    for (i=69; i<=85; i++)
    {
        if (i != 84)
        {
            GPIO_SetupPinMux(i,cpu_sel,2);
        }
    }

    for(i=86; i<=93; i++)
    {
       GPIO_SetupPinMux(i,cpu_sel,3);
    }

    //
    //configure Data pins for Async mode
    //
    for (i = 69; i <= 85; i++)
    {
        if (i != 84)
        {
            GPIO_SetupPinOptions(i,0,0x31);
        }
    }

    GPIO_SetupPinOptions(88,0,0x31);
    GPIO_SetupPinOptions(89,0,0x31);
    GPIO_SetupPinOptions(90,0,0x31);
    GPIO_SetupPinOptions(91,0,0x31);
}

//
// setup_emif2_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM
//
void setup_emif2_pinmux_sdram_16bit(Uint16 cpu_sel)
{
    int i;

    for (i=53; i<=68; i++)
    {
        GPIO_SetupPinMux(i,cpu_sel,3);
    }
    for (i=96; i<=121; i++)
    {
        GPIO_SetupPinMux(i,cpu_sel,3);
    }

    //
    //configure Data pins for Async mode
    //
    for (i = 53; i <= 68; i++)
    {
        GPIO_SetupPinOptions(i,0,0x31);
    }
}

//
// setup_emif1_pinmux_sdram_32bit - Setup pinmux for 32bit SDRAM
//
void setup_emif1_pinmux_sdram_32bit(Uint16 cpu_sel)
{
    int i;

    for (i=28; i<=85; i++)
    {
        if ((i != 42) && (i != 43) && (i != 84))
        {
            GPIO_SetupPinMux(i,cpu_sel,2);
        }
    }

    for(i=86; i<=93; i++)
    {
        GPIO_SetupPinMux(i,cpu_sel,3);
    }

    GPIO_SetupPinMux(94,cpu_sel,2);

    //
    //configure Data pins for Async mode
    //
    for (i = 53; i <= 85; i++)
    {
        if (i != 84)
        {
            GPIO_SetupPinOptions(i,0,0x31);
        }
    }

    GPIO_SetupPinOptions(88,0,0x31);
    GPIO_SetupPinOptions(89,0,0x31);
    GPIO_SetupPinOptions(90,0,0x31);
    GPIO_SetupPinOptions(91,0,0x31);
 }

#endif // CPU1

//
// End of file
//