blob: 7921716b7fa4515807b7af8441ee490ad45634a8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
|
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-07-10 xqyjlj The first version.
*/
#include <drivers/clock_time.h>
static volatile unsigned long _init_cnt = 0;
static rt_bool_t _riscv_clock_registered = RT_FALSE;
static struct rt_clock_time_device _riscv_clock_dev;
extern rt_uint64_t rt_hw_get_clock_timer_freq(void);
static rt_uint64_t _riscv_clock_get_freq(struct rt_clock_time_device *dev)
{
RT_UNUSED(dev);
return rt_hw_get_clock_timer_freq();
}
static rt_uint64_t _riscv_clock_get_counter(struct rt_clock_time_device *dev)
{
unsigned long time_elapsed;
RT_UNUSED(dev);
__asm__ __volatile__("rdtime %0" : "=r"(time_elapsed));
return (rt_uint64_t)(time_elapsed - _init_cnt);
}
static rt_err_t _riscv_clock_set_timeout(struct rt_clock_time_device *dev, rt_uint64_t delta)
{
RT_UNUSED(dev);
RT_UNUSED(delta);
return -RT_ENOSYS;
}
static const struct rt_clock_time_ops _riscv_clock_ops =
{
_riscv_clock_get_freq,
_riscv_clock_get_counter,
_riscv_clock_set_timeout,
};
void rt_clock_time_source_init(void)
{
__asm__ __volatile__("rdtime %0" : "=r"(_init_cnt));
if (!_riscv_clock_registered)
{
rt_uint8_t caps = RT_CLOCK_TIME_CAP_SOURCE;
_riscv_clock_dev.ops = &_riscv_clock_ops;
_riscv_clock_dev.res_scale = RT_CLOCK_TIME_RESMUL;
_riscv_clock_dev.caps = caps;
rt_clock_time_device_register(&_riscv_clock_dev, "clock_time_rdtime", caps);
rt_clock_time_set_default_source(&_riscv_clock_dev);
_riscv_clock_registered = RT_TRUE;
}
}
|
