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menu "RISC-V Architecture Configuration"
config RT_USING_RISCV_NEW_COMMON
bool
select RT_USING_CPU_FFS
select RT_USING_HW_ATOMIC if RT_USING_SMP
select RT_PAGE_MPR_SIZE_DYNAMIC if ARCH_MM_MMU
help
Select the unified RISC-V architecture implementation. BSPs that do
not select this option continue to use the legacy implementation while
the architecture migration is in progress.
if RT_USING_RISCV_NEW_COMMON
config ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
bool
default n
config ARCH_RISCV_DISABLE_FENCE_I
bool
default n
config ARCH_RISCV_DISABLE_SFENCE_VMA_ASID
bool
default n
config ARCH_RISCV_M_MODE
bool
depends on !ARCH_MM_MMU
default n
config ARCH_RISCV_32E
bool
depends on ARCH_RISCV32
depends on !ARCH_MM_MMU
depends on !RT_USING_DM
config ARCH_RISCV_USING_IRQ_STACK
bool "Use a dedicated interrupt stack"
depends on !RT_USING_SMART
default y if ARCH_RISCV_M_MODE || !RT_USING_DM
help
Keep the saved exception frame on the interrupted thread stack, then
run C-level trap and interrupt handlers on a per-CPU interrupt stack.
This is recommended for MCU ports.
config ARCH_RISCV_IRQ_STACK_SIZE
int "Interrupt stack size per CPU"
depends on ARCH_RISCV_USING_IRQ_STACK
range 256 65536
default 1024
config RT_USING_USERSPACE_32BIT_LIMIT
bool "Enable userspace 32bit limit"
depends on ARCH_RISCV64
default n
config ARCH_TEXT_OFFSET
hex "Kernel image offset from RAM base"
default 0x200000 if ARCH_RISCV64
default 0x400000
config ARCH_RAM_OFFSET
hex "RAM base address"
default 0
config ARCH_SECONDARY_CPU_STACK_SIZE
int "Secondary CPU stack size"
depends on RT_USING_SMP
default 4096
config ARCH_HEAP_SIZE
hex "Size of system heap"
depends on RT_USING_DM
config ARCH_INIT_PAGE_SIZE
hex "Size of init page region"
depends on RT_USING_DM && ARCH_MM_MMU
default 0x200000
endif
endmenu
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