diff options
| author | Christos Papadopoulos <[email protected]> | 2026-05-13 15:00:54 +0200 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-05-13 09:00:54 -0400 |
| commit | 0dd6d28afb54c17eae485fa8e7c9e6a7999353ff (patch) | |
| tree | ac332a9f7e52f00d24a0e355a2d003157d0d4eaf | |
| parent | 42adda44573b7c0062138818749437e6baf1044f (diff) | |
Fixed MPIE being cleared leading to have interrupts being disable after an mret instruction (#522)
* Fixed MPIE being cleared leading to have interrupts being disable when returning from machine mode
* Removed wrong register operand and replaced by immediate value
| -rw-r--r-- | ports/risc-v64/gnu/src/tx_thread_context_restore.S | 27 |
1 files changed, 10 insertions, 17 deletions
diff --git a/ports/risc-v64/gnu/src/tx_thread_context_restore.S b/ports/risc-v64/gnu/src/tx_thread_context_restore.S index 4473a39b..b73b485d 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_restore.S @@ -175,18 +175,10 @@ _tx_thread_context_restore: Set MPIE and restore MPP to Machine, preserve other fields. */ csrr t1, mstatus + li t2, 0x1880 // Set MPP(0x1800) | MPIE(0x80) - /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ - - li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) - - /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, - preserve everything except the bits we will modify. */ - - li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE - and t1, t1, t4 - or t1, t1, t3 + or t1, t1, t2 // MPP and MPIE are now set. All other bits are preserved + andi t1, t1, ~0x8 // Clear MIE, Hardware will restore it from MPIE #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state @@ -352,14 +344,15 @@ _tx_thread_no_preempt_restore: ld t0, 30*8(sp) // Recover mepc csrw mepc, t0 // Setup mepc - /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */ + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. + Set MPIE and restore MPP to Machine, preserve other fields. */ csrr t1, mstatus - li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode - li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE - and t1, t1, t4 - or t1, t1, t3 + li t2, 0x1880 // Set MPP(0x1800) | MPIE(0x80) + + or t1, t1, t2 // MPP and MPIE are now set. All other bits are preserved + andi t1, t1, ~0x8 // Clear MIE, Hardware will restore it from MPIE #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) li t0, 0x2000 // Set FS bits for FP state |